JPH0683655A - Data transfer error detector - Google Patents

Abstract

PURPOSE:To surely detect in real time the errors caused by the transfer of data at the transmitter side with a simple configuration. CONSTITUTION:A data transfer error detector is provided with the parity generating circuits 4 and 5 which are provided in the transmitter/receiver devices and generate the parity bits when the data are transmitted and received to adds these parity bits to the data, and a comparator circuit 6 which is provided in a main transmitter/receiver device and compares the transmission/reception data having the parity bits imparted by the respective parity generating circuits 4 and 5 with each other to detect the data transfer errors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer error detecting device for detecting an error during data transfer between master and slave.

[0002]

2. Description of the Related Art For example, when data is transferred between personal computers, if these personal computers have intelligence, these personal computers use software to process a part of the transferred data such as parity or checksum. Is added to monitor the error occurrence.

On the other hand, in data transfer between personal computers having no intelligence, it is not possible to monitor the occurrence of an error such as a parity check as described above. This enables factory automation (F
It is essential to monitor the occurrence of an error in a place such as A) where it is affected by noise from the outside or where there is a high risk of disconnection, and a personal computer without intelligence cannot be used.

Further, the error occurrence is monitored by the receiving side personal computer among the personal computers, and the error occurrence monitoring by the transmitting side personal computer is easier to process for data transfer again.

[0005]

As described above, an error occurrence such as a parity check cannot be monitored during data transfer between personal computers having no intelligence.

Therefore, an object of the present invention is to provide a data transfer error detection device which can detect an error occurrence in data transfer in real time with a simple structure.

[0007]

SUMMARY OF THE INVENTION The present invention is a data transfer error detecting device for detecting an error in data transfer between transmitting and receiving devices, wherein a parity bit is generated when transmitting and receiving data provided in each transmitting and receiving device. A plurality of parity generation circuits for adding data to the data, and a comparison circuit that is provided in the main transmission / reception device of each transmission / reception device and compares each transmission / reception data to which a parity bit is added by each parity generation circuit to detect an error. A data transfer error detecting device is provided for the purpose of achieving the above object.

[0008]

By providing such means, each parity generation circuit provided in each transmission / reception device at the time of data transfer between each transmission / reception device generates a parity bit and adds it to each data of transmission / reception, and compares it. The circuit detects the error by comparing each data to which the parity bit is added by each parity generating circuit of these transmitting and receiving devices.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data transfer error detecting device. The master personal computer 1 and the slave personal computer 2 are connected by a data transfer bus 3.

A master personal computer 1 is provided with a parity generation circuit 4 and is connected to a data transfer bus 3, and a slave personal computer 2 is also provided.
Similarly to the master, a parity generating circuit 5 is provided and is connected to the data transfer bus 3. Both of the parity generation circuits 4 and 5 have a function of taking in the data on the data transfer bus 3 and adding a parity bit. The parity generation circuit 4 provided on the master side
Is connected to the comparison circuit 6 provided on the master side, and the output terminal of the parity generation circuit 5 provided on the slave side is connected to the comparison circuit 6 provided on the master side via the parity transfer line 7. Has been done. Buffers 8 and 9 are connected to the parity transfer line 7.

The comparison circuit 6 is composed of an exclusive NOR circuit. The output terminal of the parity generation circuit 4 is connected to one input terminal of the comparison circuit 6 and the parity transfer line 7 is connected to the other input terminal. The output terminal of the parity generation circuit 5 is connected via. The output terminal of the comparison circuit 6 is connected to the J terminal of the J-type flip-flop 10.

A clock clk is input to the J-type flip-flop 10 and a reset signal is input to the K terminal. The error signal E is output from the Q terminal of the J-type flip-flop 10. The data transfer bus 3 has buffers 11, 12 and 1 on the master side and the slave side, respectively.
3, 14 are connected. Next, the operation of the apparatus configured as described above will be described.

First, the master personal computer 1
A case where data is transferred from the slave to the slave personal computer 2 will be described. Personal computer 1
When the data is loaded on the data transfer bus 3 at, the data is input to the parity generation circuit 4 together with the data.
Further, this data passes through the buffer 12 and is transmitted through the data transfer bus 3 to reach the slave personal computer 2 to be fetched and inputted to the parity generating circuit 5.

The parity generation circuits 4 and 5 add a parity bit to the input data and output it. Of these, the parity bit added data output from the parity generation circuit 4 is input to one input terminal of the comparison circuit 6, and the parity bit added data output from the parity generation circuit 5 is transmitted through the parity transfer line 7. Then, the other input terminal is input to the comparison circuit 6.

The comparison circuit 7 compares each bit of the data input to each input terminal and outputs a high level signal when the bits are different. This high-level signal is input to the J terminal of the J-type flip-flop 10, and the J-type flip-flop 10 receives the clock clk and outputs the high-level error signal E from the Q terminal. Therefore, the master personal computer 1 detects the error occurrence during data transfer by monitoring the error signal E.

Next, the slave personal computer 2
Data transfer from the master computer to the master personal computer 1 will be described. When data is put on the data transfer bus 3 in the personal computer 2, the data is input to the parity generation circuit 5 together with the data. or,
This data passes through the buffer 13 and is transmitted through the data transfer bus 3 to reach the master personal computer 1 to be fetched and input to the parity generation circuit 4.

However, these parity generation circuits 4, 5
Adds parity bits to the input data in the same manner as described above. Of these, the parity bit added data output from the parity generation circuit 5 is the parity transfer line 7.
Is transmitted and input to the other input terminal of the comparison circuit 6, and the data with the parity bit output from the parity generation circuit 4 is input to one input terminal of the comparison circuit 6.

The comparison circuit 7 compares each bit of the data input to each input terminal and outputs a high level signal when the bits are different. This high-level signal is received by the J-type flip-flop 10, and the J-type flip-flop 10 receives the clock clk and outputs the high-level error signal E from the Q terminal. Therefore, the master personal computer 1 detects the error occurrence during data transfer by monitoring the error signal E.

As described above, in the above-described embodiment, the parity bit is added to the transfer data by the parity generating circuits 4 and 5 when the data is transferred between the master and slave personal computers 1 and 2, and the comparison circuit 6 is added. With this configuration, the parity generation circuits 4 and 5 are configured to detect the error by comparing each data to which the parity bit is added. Therefore, the error occurrence in the data transfer can be performed in real time in the master personal computer 1 with a simple configuration. Can be reliably detected. This allows the master personal computer 1 to monitor the occurrence of errors on both sides of the master and slave.

The present invention is not limited to the above-mentioned one embodiment, and may be modified within the scope of the invention. For example, by making the buffer 8 of the parity transfer line 7 in the slave personal computer 2 an open collector or a three-state buffer, it is possible to support a system in which the connection of the personal computers is one to many. Further, the comparison circuit 6 is not limited to the exclusive NOR circuit, but other comparison circuits may be used.

[0022]

As described above in detail, according to the present invention, it is possible to provide a data transfer error detecting device capable of reliably detecting an error occurrence in data transfer in real time on the transmitting side with a simple structure.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a data transfer error detection device according to the present invention.

[Explanation of symbols]

1, 2 ... Personal computer, 3 ... Data transfer bus, 4, 5 ... Parity generating circuit, 6 ... Comparison circuit, 7 ... Parity transfer line, 10 ... J-type flip-flop.

Claims (1)

[Claims] 1. A data transfer error detection device for detecting an error in data transfer between transmission / reception devices,
A plurality of parity generation circuits provided in each of the transmission / reception devices to generate a parity bit at the time of transmission / reception of data to add to the data, and a parity bit generated by each of the parity generation circuits provided in the main transmission / reception device among the transmission / reception devices. A data transfer error detection device, comprising: a comparison circuit that compares the respective transmitted and received data to detect an error.