KR920005139B1 - Td-bus matching circuit - Google Patents

Abstract

The circuit includes a maintenance processor (MP), and a buffer means (1) connected to a TD-bus. A shift register means (3) is connected to the buffer means (1), and an address decoder means (2) receives the address of an alarm access control unit assembly. An RDY signal generating means (4) receives RDY signals from the maintenance processor (MP), and a data buffer means (5) is connected to the shift register means (3). A parity generating/detecting and error signal generating means (6) is connected to the means (3)(4)(5). With the circuit, the errors of the TD-bus and other malfunctions are promptly detected.

Description

TD-bus matching circuit for alarm collector

1 is a block diagram showing the configuration of the present invention.

2 is a timing diagram of each part of the RDY signal generator of FIG.

3 is a timing diagram of the parity error signal generator of FIG.

* Explanation of symbols for main parts of the drawings

1: RS-422 transmit / receive buffer 2: Address decoder circuit

3: shift register 4: RDY signal generating signal

5: Data buffer 6: Parity generation / detection and error signal generation circuit

The present invention collects all the alarms generated by the TDX-10 system, which is an electronic switchboard, and has a parity generation / detection function of the alarm collection device that notifies the status of the status to a maintenance processor that is a higher processor. It relates to a matching circuit.

The Alam Access Control Unit Assembly (AACU) (hereinafter referred to as AACU) communicates with the Maintenance Processor (MP) via the TD bus, and the TD bus communicates with the frame synchronization signal (FS). When the mode, address, and parity data, which are performed in an interrupt manner and transmitted with the FS, are received and match the unique address of the AACU, the AACU is activated. The active AACU determines the operation mode by mode data and transmits an output ready signal (ORDY: Output RDY) to the maintenance processor indicating that the data is ready to be transmitted and received. The transmission and reception of data is performed together with the ORDY signal, and the transmission and reception of data is also terminated by the termination of the ORDY signal. In the event of mode and transmission / reception data errors, the parity generation / detection circuit detects this and generates a parer error signal (RERR), which is then quickly transmitted to the maintenance processor via the TD-bus.

An object of the present invention is to notify that there is an error in the TD-bus operation as described above and to prevent a malfunction due to false data.

In order to achieve the above object, the present invention provides a transmission and reception buffer means connected to a maintenance processor MP and a TD bus, a shift register means connected to the transmission and reception buffer means, and an alarm collecting device AACU. A unique address is input and is connected to the address decoder means connected to the transmission and reception buffer, the RDYE signal is input from the maintenance processor MP, and the RDY signal generating means is connected to the transmission and reception buffer means and the shift register means, and the shift register means. It consists of connected data buffer means, said shift register means and said RDY signal generating means, and parity generation / detection and error signal generating means connected to said data buffer means, and quickly to said maintenance processor MP via a TD-bus. And prevents malfunction due to errors and incorrect data of the TD bus. The.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram showing the configuration of the present invention, FIG. 2 is a timing diagram of each part of the RDY signal generator of FIG. 1, and FIG. 3 is a timing diagram of the parity error signal generator of FIG. A buffer, 2 is an address decoder circuit, 3 is a shift register, 4 is an RDY signal generation circuit, 5 is a data buffer, and 6 is a parity generation / detection and error signal generation circuit, respectively.

As shown in FIG. 1, the present invention maintains an RS-422 transmit / receive buffer 1 corresponding to a TD-bus interface and a shift register 3 for converting serial data into parallel data and parallel data into serial data. The address decoder 2 for comparing the address coming from the maintenance processor MP with the unique address of the AACU, the RDY signal generating circuit 4 for transmitting and receiving data, the data buffer circuit 5 and the parity generation The parity generation / detection and parity error signal generation circuit 6 corresponding to the detection / detection section is returned.

The redundant RS-422 transmit / receive buffer (1) uses 96174, 96175, which is an auto driver and receiver, and the TD-bus signals are clock (625KHz), FS, mode / address 0 to mode / address 3, transmit / receive data (TxD, RxD ), RDY, and TV-SEL signals, and receive the TB-SEL signal to generate an enable signal for the active bus to select a redundant bus. That is, if two TB-SEL signals maintain the same level, the B side selects the TD bus of the A side.

The address decoder circuit 2 uses two 4-bit comparators 74F85 to compare and match the 8-bit address received from the RS-422 transmit / receive buffer 1 with the unique address of the alarm collection unit (AACU). Is active and sends an address check (ADDRCK) signal to the parity error signal generation circuit 6.

In order to receive the mode / address 0 to the mode / address 3, shift registers 74F164 (3), which are four serial / parallel changing circuits, were used. The shift clock is generated using the FS and the clock. Enable parity generation / detection of the shifted mode / address 0 to mode / address 3 in the shift register and the four parity generation / detection (74F280) of the error generation circuit 6, and enable mode / address buffers. The signal is loaded onto the internal data bus.

In case of the received data, the shifted signal is shifted to 9 clocks generated by the extended ready signal (ERDY) and the clock. The shifted 8-bit received data and 1-bit parity data are generated by parity generation / detection and error signal generation signals (6). Using one parit generation / detection of 74F280, the received data is stored in the data buffer by the receive data buffer enable signal.

The parity generation / detection circuit adopting the odd parity in the parity generation / detection and error signal generation circuit 6 uses the eighth bit of each mode / address 0 to 3 signals and one bit parity bit at the end of the received data. The error is checked horizontally across the signal line and the parity error signal generator is notified of the occurrence of a parity error and the address parity error (MPRTERR) and data parity error (DPRTERR) signals.

The data to be transmitted is first stored in the data buffer 5 by the transmit data buffer enable signal, and then one bit of parity is generated using one parity generator / detector 74F280 to generate 8 bits of transmitted data and parallel / serial conversion. The shift register 74F323 (6), which is a circuit, is loaded. In this case, the shift register operation mode is changed from the parallel loading mode to the shift write mode by the ERDY signal. The loaded transmission data is shifted to the clock and nine clocks generated by the ERDY and ORDY signals, and ends with the termination of the ERDY signal, and the shift register 3 transitions to the parallel mode again.

The RDY signal generation circuit 4 is enabled by the RDYE signal, and consists of three D flip-flops 74F74 and one counter 74F161 to generate the ERDY and ORDY signals. In addition, circuits are provided to supply the loading and shift clocks to the transmit and receive shift registers. The timing diagram of the RDY signal generation circuit 6 is as shown in FIG.

The parity generation / detection and error signal generator 6 is composed of five D flip-flops to generate a mode, address and data parity error signal (PERR), and the FS, ORDY, ERDY, clock, DPRTER, MPRTER and ADDRCK signals. It is used to generate a PERR that keeps low for 0.5 clock after one clock when the FS and RDY signals go high, and informs the maintenance processor (MP) of the occurrence of an error. The timing diagram of the parity error signal generation circuit of the parity generation / detection and error signal generation circuit 6 is as shown in FIG.

The present invention configured and operated as described above receives a mode, address, and parity data transmitted from the maintenance processor (MP) together with the FS through the TD bus, and uses the same for parity generation / detection. If it matches with the unique address of, the alarm collecting device (AACU) is active and the active alarm collecting window (AACU) determines the operation mode by the mode data, and generates the ORDY signal for transmitting / receiving data and uses it for parity generation / detection. In addition, the data is transmitted and received through the TD-bus along with the ORDY signal.The data transmission and reception is terminated by the termination of the ORDY signal, and the parity disable strap is placed on the alarm collecting unit (AACU) to select the use of parity. Parity generation / detection circuit (6) Document states that are detected to generate the parity error signal (PERR) and this maintenance quickly transmitted to the processor (MP) error in TD- O bus operation has the effect of preventing the undercoating reuk AACU malfunction due to data.

Claims (1)

Transmission / receiving buffer means (1) connected to the maintenance processor (MP) and the TD-bus, shift register means (3) connected to the transmission / reception buffer means (1), and alarm collection window (AACU) unique address from the alarm collecting device (AACU). Is input and an RDYE signal is input from the address decoder means 2 connected to the transmission / reception buffer 1 and the maintenance processor MP, and the RDY signal is connected to the transmission / reception buffer means 1 and the shift register means 3. Generation means 4, data buffer means 5 connected to the shift resist means 3, the shift register means 3 and the RDY signal generating means 4, and parity connected to the data buffer means 5 Alarming, characterized in that it comprises a generation / detection and error signal generating means (6) to quickly transfer to the maintenance processor (MP) through the TD-bus and to prevent malfunction due to errors and data of the TD-bus gathering Value (AACU) TD- bus matching circuit.

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