KR930011652B1 - Electronic exchange - Google Patents

Abstract

The unit which collects and processes the alarms generated in a full electronic switching system comprises a control section for supervising interface and frame synchronizing signals, a bus impedence matching section for receiving and transmitting data, a control signal generating section, a memory for saving data, and a buffer section for receiving a hardware device alarm information and a characteristic address.

Description

Alarm Collector of Electronic Switch

1 is a block diagram showing a schematic configuration of an electro-electric exchanger to which the present invention is applied.

2 is a detailed block diagram showing an alarm collecting device according to the present invention.

FIG. 3 is a detailed block diagram showing the configuration of the control signal generator of FIG.

* Explanation of symbols for main parts of the drawings

100: maintenance processor 200: to

263: alarm collecting device 300:

363: hardware device 270: memory

271: control unit 272: buffer unit

273: bus matching circuit section 274: control signal generating section

401: address decoder circuit 402: shift register

403: RDY signal generating circuit 404: data buffer

405: parity generator / detector error signal generator

The present invention relates to an alarm collecting device that performs a function of collecting and processing an alarm generated in hardware by applying an on-demand semiconductor in an all-electronic exchanger.

Conventional alarm processing accepts and processes up to 64 alarm information per alarm collection device (AACU: Alarm Access Control Board Unit, hereinafter called AACU).

The present invention can accommodate up to 128 alarm information per AACU, and an object of the present invention is to provide an alarm collecting device of an electronic switchgear that improves cost reduction and reliability.

In order to achieve the above object, the present invention provides an alarm collecting device for an electronic switch, comprising: control means for monitoring an RS-232C interface and a frame synchronizing signal (FS), bus matching means connected to the control means, and transmitting and receiving data. A control signal generating means connected to the control means and a bus matching means, a memory means connected to the control means and a bus matching means and storing data, a hardware device alarm connected to the control means and a memory means and a control signal generating means It consists of buffer means for receiving information and unique address, characterized in that the alarm is collected and processed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows an embodiment of the present invention.

In the figure, 100 denotes a maintenance processor, 200 to 263 denotes AACU, and 300 to 363 denote hardware devices.

The alarm processing in the electronic switchboard includes a maintenance processor 100, up to 64 AACUs 200 to 263 connected to the maintenance processor 100, and a hardware device 300 connected to each AACU 200 to 263, respectively. To 363).

The AACUs 200 to 263 collect alarm information generated from each hardware device 300 to 363, and the collected alarm information of each hardware device 300 to 363 sets a TTL level “high” or high impedance state as an alarm state. It must have a TTL level blow or ground state as normal and couple the ground line together.

Each of the AACUs 200 to 263 has a unique address, and an alarm device collected by a polling scheme of a maintenance processor 100 (MP: Maintenance Process (MP)) in a serial manner of 1 byte unit is used. It is transmitted to the MP 100 through a TD-bus (Telephony Device-Bus). The alert information transmitted to the MP 100 indicates whether there is a state change of the acceptance information and the current state of each information.

2 is a detailed block diagram showing an alarm collecting device of the electronic switch according to the present invention.

In the drawing, reference numeral 270 denotes a memory unit, 271 a controller, 272 a buffer unit, 273 a bus matching circuit unit, and 274 a control signal generator.

The alarm collector of the electronic switchgear allows the external memory to be accessed by operating the mode "3" and monitors the RS-232C interface signal and the frame sync signal (hereinafter referred to as FS) and interrupts the TD- The control unit 271 performing a bus operation transmits an FS signal to the control unit 271, receives a mode / address signal, and transmits / receives data to and from the MP 100 through a redundant TD-bus in a serial manner of 1 byte. An 8-bit address that is connected to the bus matching circuit unit 273, the bus matching circuit unit 273, and the control unit 271 and receives a mode / address and comes from the MP 100 and the unique addresses of the AACUs 200 to 263. Parity bit generation / detection usage can be selected so that the parity error signal is generated when the parity error signal is transmitted / received in the mode / address and transmission / reception. A control signal generator 274 which informs a life, a memory unit 270 which is connected to the control unit 271 and the control signal generator 274 and stores mode / address data according to a mode / address buffer control signal; It is connected to the memory unit 270, the control unit 271 and the control signal generation unit 200 and receives the 128 hardware device (300 to 363) alarm information and the unique address of the AACU (200 to 263) and to the buffer control signal It consists of a buffer unit 272 for storing data in the memory unit 270.

If the address received from the bus matching circuit unit 273 matches its own address, the corresponding AACU 200 to 263 transmits the collected alarm information to the MP 100 by performing TD-bus communication with the MP 100. The AACUs 200 to 263 whose addresses do not match continuously monitor 128 alarm information. By using the parity selectable for the reliability of the TD-bus, it is quickly delivered to the MP 100 in case of a parity error, indicating that there is an error in the TD-bus operation and preventing the malfunction of the AACU (200 to 263) due to false data. To improve it.

The control unit 271 is composed of a microprocessor and the memory unit 270 is composed of a 256K bit EPROM and a 64K bit SRAM. In addition, the buffer unit 272 is composed of 17 8-bit buffer, and the bus matching circuit unit 273 is composed of a differential driver and a receiver.

3 is a detailed block diagram of the control signal generator 274.

In the drawing, reference numeral 401 denotes an address decoder circuit, 402 denotes a shift register, 403 denotes an RDY signal generating circuit, 404 denotes a data buffer, and 405 denotes a parity generation / detector error signal generating circuit.

As shown in FIG. 3, the control signal generator 274 includes a shift register 402 for converting serial data into parallel data and an address from the maintenance processor (MP) 100. An address decoder circuit 401 for comparing an alarm collecting device (AACU) unique address, the RDY signal generating circuit 403 for transmitting and receiving data, and the data connected to the shift register 402. And a parity generation / detection and parity error signal generation circuit 405 connected to the buffer 404 and the shift register 402 and the data buffer 404.

The address decoder circuit 401 uses two 4-bit comparators, and compares the 8-bit address received from the bus matching circuit unit 273 with the unique address of the alarm collection unit (AACU), and matches the corresponding AACU (200 to 263). ) Is active and sends an address check (ADDRCK) signal to the parity generation / detection and parity error signal generation circuit 405.

In order to receive the mode / address 0 to the mode / address 3, the shift register 402, which is four serial / parallel conversion circuits, is used, and the shift clock is generated using the FS and the clock. In the shift register 402, the mode / address 0 to the mode / address 3 to the parity generation / detection and the four parity generation / detectors of the error generation circuit 405 are used. It is loaded onto the internal data bus by the enable signal.

In case of the received data, the shifted signal is shifted to 9 clocks generated by the extended ready signal (ERDY) and the clock. The shifted 8-bit received data and 1-bit parity data are generated / detected and the error signal generating circuit 405 Using one parity generator / detector, the received data is stored in the data buffer by the receive data buffer enable signal.

In the parity generation / detection and error signal generation circuit 405, the parity generation / detection circuit adopting odd parity uses the eighth bit of each mode / address 0 to 3 signals and one bit at the end of the received data. The error is checked horizontally and the parity error signal generator is notified of the occurrence of the error using the mode and address parity error (MPRTERR) and data parity error (DPRTERR) signals.

The data to be transmitted is first stored in the data buffer 404 by the transmit data buffer enable signal, and then a single parity generator / detector is used to generate 1 bit of parity, thereby shifting the 8 bits into a parallel / serial conversion circuit. In this case, the shift register operation mode is changed from the parallel loading mode to the shift write mode by the ERDY signal. The loaded transmit data is shifted to the clock and nine clocks generated by the ERDY and ORDY signals, terminated with the end of the ERDY signal, and the shift register 402 transitions back to parallel mode.

The RDY signal generation circuit 403 is enabled by the RDYE signal and consists of three D flip-flops and one counter to generate the ERDY and ORDY signals. In addition, circuits are provided to provide the loading and shift clocks to the transmit and receive shift registers.

The parity generation / detection and error signal generation circuit 405 consists of five D flops to generate the mode, address, and data parity error signals (PERR), FS, ORDY, ERDY, clock, DPRTER, MPRTER, and ADDRCK signals. Use 1 to generate a PERR that remains low for 0.5 clock after 1 clock when the FS and RDY signals go high, and notifies the maintenance processor (MP) of the occurrence of an error.

As described above, the present invention can handle the alarm generated in the electronic switchboard simply and quickly, and also has the effect of reducing the cost and improving the reliability.

Claims (2)

An alarm collecting apparatus of a full wave exchanger; Control means 271 for monitoring the RS-232C interface and the frame synchronizing signal FS; Bus matching means (273) connected to the control means (271) and transmitting and receiving data; A control signal generator 280 connected to the control means 271 and the bus matching means 273; Memory means (270) connected to the control means (271) and the bus matching means (273) and storing data; And a buffer means (272) connected to the control means (271), the memory means (270) and the control signal generating means (274) and receiving hardware device alarm information and a unique address. 2. The control signal generating means (274) according to claim 1, wherein the control signal generating means (274) includes a shift register means (402) connected to the bus matching means (273), an address decoder means (401) connected to the bus matching means (273), and the bus matching. RDY signal generating means 403 connected to the means 273 and the shift register means 3, data buffer means 404 connected to the shift register means 402, the shift register means 402 and the RDY signal generating means ( 403, and parity generation / detection and error signal generation means (405) connected to the data buffer means (404).

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