JP2845049B2 - Status change monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
In a device in which a plurality of units performing one-to-multi communication between the U and the CPU via the data bus are mounted, the CPU changes the state of the units in order to monitor and control the plurality of units. Regarding the monitoring method.

[0002]

2. Description of the Related Art An apparatus such as a base station of a digital mobile telephone system includes a plurality of radio transmission / reception units (hereinafter referred to as transmission / reception units) for performing radio communication with a mobile station, and a mobile station via each transmission / reception unit. It comprises a common control unit that controls connection such as calling and receiving.

The CPU of the common control unit transmits and receives call control data to and from each transmission / reception unit connected to the data bus in a multi-drop manner via the interface unit, and controls connection of calls.

Each transmission / reception unit is formed of a printed board package and is connected to a common control unit in the same frame via a data bus, and each transmission / reception unit is assigned transmission / reception data to the own unit via the data bus. The data bus is used in a time-sharing manner by transmitting the data bus serially in a time slot.

[0005] The interface unit converts data serially transferred from each transmission / reception package via the data bus into parallel data, and receives the data by writing the data into a two-port RAM. The CPU via the system bus
The user accesses the two-port RAM at a convenient timing to fetch and process the received data. For this purpose, the interface unit has a data transmission / reception circuit that converts received data into a form that can be accessed and processed by the CPU, and a two-port RAM that temporarily buffers data to be transmitted / received.

On the other hand, in addition to performing the main processing for the above-described call control, the CPU also performs monitoring control processing for normal operation of each package, such as failure of each transmission / reception package and power supply state monitoring.

Conventionally, a supervisory control bus for transmitting and receiving supervisory control signals has been provided between the package and the CPU, in addition to a data bus for exchanging main signals, to exchange supervisory control signals.

[0008]

As described above, in the prior art, between the communication control unit and a plurality of transmission / reception packages,
Two buses, a data bus for transmitting and receiving main data and a supervisory control bus for transmitting and receiving supervisory control information, are provided. Then, in order to make it possible to arbitrarily access the monitoring control information transmitted and received from each transmission / reception package via the monitoring control bus from the system bus on the CPU side, a register for temporarily holding state information is interfaced with the package. It was provided in the face club. However, in a mobile radio base station apparatus or the like having a very large number of packages to be monitored and controlled, the number of registers is increased, and there is a problem that the hardware scale of the interface unit is increased. For example, if there are 72 packages to be monitored and a status register and a control register each having 8 bits are required, 144 8-bit registers need to be provided in the interface unit.
It was physically impossible.

Further, since the CPU periodically reads the status information from the status register and checks for the presence / absence of a status change by software, the software process for monitoring and control places a heavy burden on the CPU.

[0010] The present invention has been made in view of the above problems, and reduces the load on the CPU during monitoring and control processing, and increases the number of wires and registers for monitoring and control even when the number of units to be monitored and controlled increases. It is an object of the present invention to provide a state change monitoring method that does not cause a state change.

[0011]

FIG. 1 is a block diagram of a state change monitoring system according to the present invention. As shown in FIG. 1, the above-mentioned problem is caused by a plurality of transmission / reception units 1-1 to 1-n which are connected to the data bus 5 in a multi-drop manner and transmit main data to the CPU 4 via the data bus. An interface unit 3 that receives the main data of the interface unit 3 and temporarily stores the main data in a two-port RAM, and a CPU 4 that receives the main data stored in the interface unit 3 via a system bus 6 and processes the main data. Each transmission / reception unit
This is a method for monitoring the abnormal status of 1-1 to 1-n. Each transmission / reception unit 1-1 to 1-n adds the new and old status information of its own unit and the status change presence / absence information to the main data. A transmission / reception control unit 11 for transmitting to the bus 5 is provided.
A two-port RAM 32 that stores both the old and new state information together with the main data received from each unit, and a state change presence / absence information in the received data is monitored, and a state change detection pulse is output when a state change is detected. A detection unit 33, a unit number output unit 35 that outputs the unit number of the transmission / reception unit that is the transmission source of the currently received reception data, and a unit number output by the unit number output unit at the timing of the state change detection pulse. By writing, a FIFO type unit number register 34 for holding the number of the status change unit and notifying the CPU 4 of an interrupt is provided.
U4, upon receiving the interrupt notification, reads the contents of the unit number register 34, recognizes the state change occurrence unit, and
The state change monitoring method of the present invention is characterized in that the state change item is known from the new and old state information of the corresponding address of the port RAM 32.

[0012]

The CPU interrupts the CPU only when the interface unit detects a state change of any of the transmission / reception units. Therefore, the CPU reads the unit number register by a predetermined interruption process and determines the unit number having the state change. The state information can be obtained by knowing and reading the data in the two-port RAM corresponding to the number.

Therefore, it is only necessary to hold only the address of the transmission / reception package in which the status has changed, and it is not necessary to provide registers for the number of units to be monitored so that all status information can be stored. The number can be reduced. Further, the CPU does not need to periodically read the state information to detect the state change, and is notified only when the state change occurs. Therefore, the time dedicated to the main data control processing increases and the use efficiency is improved. . Further, since the data bus is shared by the main data and the supervisory control signal, there is no need to provide a dedicated supervisory control bus, and the number of wirings can be reduced.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a state monitoring system according to the present invention. FIG. 1 is a configuration diagram of a state change monitoring method according to the present invention,
FIG. 2 is an address map of the reception data register on the 2-port RAM. Here, "Receive data on 2-port RAM"
Data register ”is as if it were received on a 2-port RAM.
It means a storage area that is expanded like a register,
A normal 2-port RAM that stores received data.
U.

In FIG. 1, 1-1 to 1-n are a plurality of transmitting / receiving units, 2 is a common control unit, 3 is provided in the common control unit, and an interface unit for relaying a system bus and a data bus is provided. The CPU 5 is a data bus to which transmission / reception units are multi-drop connected and through which data transmitted / received between the transmission / reception package and the common control unit passes.

In the transmission / reception units 1-1 to 1-n, the transmission / reception control unit 11 includes, in the main data for call control received from the wireless section, a change between the current and old state information of the unit and the state information between the two. Then, a transmission frame is created by adding state change presence / absence information indicating whether or not there has been received, and transmitted to the data bus 5 in the time slot allocated to the own unit.

The interface unit 3 includes a transmission / reception control unit 31,
It has a two-port RAM 32, a state change detection unit 33, a unit number register 34, and a unit number output unit 35. The transmission / reception control unit 31 of the interface unit performs serial-to-parallel conversion of serial reception data from a plurality of transmission / reception units sequentially transmitted in the respective time slots via the data bus 5, extracts necessary data, and performs 2-port Write to the reception register provided for the transmission / reception unit on the RAM 32, and output the reception timing signal to the unit number.
It is sent to the force unit 35.

The two-port RAM 32 has two ports that are asynchronously writable / read accessible and can simultaneously read from both ports. The transmission / reception control unit 31 of the interface unit and the system bus 6 of the CPU are connected to each other. Each has its own access.

FIG. 2 is an address map of the reception data register of the 2-port RAM. For example, an area corresponding to each transmission / reception unit number is provided with an area for monitoring control data following main data, and data for current and old state information is provided. And supervisory control data are written.

The state change detection unit 33 constantly monitors the state change presence / absence information transmitted by being carried on a specific bit of the received frame, and when the state change is detected in the received data of a certain time slot, the state change detection unit 33 changes the state. Outputs a detection pulse. On the other hand, the unit number output section 35 constantly outputs the unit number data (corresponding to the time slot number) corresponding to the time slot received via the transmission / reception control section 31 to the unit number register 34 composed of a FIFO memory. I have. The unit number at that time is written to the unit number register 34 by the state change detection pulse.

The unit number register 34 is, for example, a shift register having an 8-bit width, and can hold a predetermined number of number data. The unit number register 34 is a FIFO memory which is read from the oldest data by read access, and stores some data. During this time, an "L" level empty signal EP is output. This signal is used as an interrupt notification signal
U4 is notified. The CPU 4 monitors the interrupt notification signal. When detecting the interrupt notification signal, the CPU 4 accesses the unit address register 34 via the system bus 6 to read out the oldest data and determine the transmission / reception unit number at which the status change has occurred. recognize. Then, the CPU 4 accesses the status information address in the reception register of the transmission / reception unit on the 2-port RAM 32 via the system bus 6, reads the current / old status information, and performs a predetermined process.

[0022]

As described above, according to the present invention,
In a system having a plurality of transmitting and receiving units for performing main data communication with a CPU in a one-to-many manner via a serial data bus, monitoring of status information when the CPU performs monitoring control of each unit is performed by a monitoring control bus. There is an effect that it can be performed without providing a monitoring control register for each unit or without increasing the load on the CPU. Also,
By increasing the storage capacity of the two-port RAM, it is possible to easily cope with the increase in the number of monitoring control target units and the number of monitoring control items.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a state change monitoring method according to the present invention.

FIG. 2 is an address map of a reception data register on a 2-port RAM.

[Explanation of symbols]

1-1 to 1-n: transmission / reception unit, 11: transmission / reception control unit, 2 ...
Common control section, 3 interface section, 31 transmission / reception control section, 32 2-port RAM, 32a reception register, 33 state change detection section, 34 unit number register, 35 unit number output section, 4 CPU 5, data bus, 6 system bus

Claims (1)

(57) [Claims] A plurality of transmission / reception units (1-1 to 1-n) connected to a data bus (5) in a multi-drop manner and transmitting main data to the CPU (4) via the data bus;
An interface unit (3) for receiving the main data from (5) and temporarily storing it in a two-port RAM, and fetching and processing the main data stored in the interface unit (3) via a system bus (6). A device having a CPU (4).
The PU (4) monitors the status change of each transmission / reception unit (1-1 to 1-n). Transmission / reception control unit (11) that adds status information and status change presence / absence information and sends it to the data bus (5)
In the interface unit (3), a 2-port RAM (32) that stores both the new and old state information together with the main data received from each unit, and the status change presence / absence information in the received data is monitored. State change detection unit (33) that outputs a state change detection pulse when a change is detected
And a unit number output unit (35) that outputs the unit number of the transmission / reception unit that is the source of the currently received reception data.
A unit number in a FIFO format for writing the unit number output by the unit number output unit at the timing of the state change detection pulse, thereby holding the state change occurrence unit number and notifying the CPU (4) of an interrupt. register
The CPU (4) reads the contents of the unit number register (34) upon receipt of the interrupt notification, recognizes the state change occurrence unit, and recognizes the corresponding address of the 2-port RAM (32). A state change monitoring method characterized in that a state change item is known from new and old state information.