JPH03223940A - Data memory monitoring circuit - Google Patents

Abstract

PURPOSE:To directly monitor a bit train in a data memory where a circuit is set by checking the input/output data themselves on the data memory in all valid addresses. CONSTITUTION:A monitoring address counter 12 is counted up from '0' for each cycle of a sequential counter 11. When an address detecting part 13 detects that the coincidence is secured between the monitoring address outputted from the counter 12 and the set address of a control memory 30, a coincident pulse transmitting part 14 latches the input data on a data memory 20 via a data latch part 15 in the timing of the address to be monitored as a set address of the memory 30. Then a data coincidence detecting part 16 checks whether or not the latched data is coincident with the data read out of the memory 20 in the following single cycle of the counter 11 and according to the same set address of the memory 30. As a result, a bit train can be directly monitored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data memory monitoring circuit for monitoring failures in a line setting data memory used in a communication device in digital communication or data transmission.

[Conventional technology]

Conventionally, this type of data memory monitoring circuit adds one parity bit to the input data pit string supplied to the data memory and stores it in the data memory. The data memory is monitored by checking the parity of the output parity bit.

[Problem to be solved by the invention]

The conventional data memory monitoring circuit described above adds one bit of odd or even parity to an input data pit string and stores it in the data memory, and then checks the parity bit added to the output data pit string of the data memory. Since the data memory is monitored, it is possible to detect errors in an odd number of bits in the input/output data pit string, but it is impossible to detect errors in an even number of bits. There is a drawback. Furthermore, in detecting a pass baton check using an unused pit string, there is a drawback in that only fixed addresses can be monitored in the data memory.

[Means to solve the problem]

A data memory monitoring circuit according to the present invention counts up in synchronization with the input data and outputs a current signal in a data memory monitoring circuit that monitors a data memory that stores input data and outputs output data. a sequential counter, a monitoring address counter that counts up every cycle of the sequential counter and outputs a monitoring address of the data memory, and detects a match between a set address for controlling the data memory and the monitoring address. and an address detection unit that outputs an address match signal when those addresses match;
a match pulse sending section that compares the count signal and the monitoring address in response to the address match signal and sends out a latch pulse when these values match; a data latch unit that latches input data and outputs the latched data; and a data latch unit that detects a match between the output data and the latched data and outputs a match detection result only when the set address is received. It is characterized by having a coincidence detection section.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a data memory monitoring circuit 10 according to one embodiment of the present invention is for monitoring failures in a data memory 20 that stores input data and outputs output data.

The data memory monitoring circuit 10 includes a sequential counter 11 that counts up in synchronization with input data and outputs a count signal, and a monitor that counts up every cycle of the sequential counter 11 and outputs a monitoring address of the data memory 20. Address counter 12 and control memory 3 for controlling data memory 20
An address detecting section 13 detects a match between the set address of the data memory 20 outputted from 0 and a monitoring address, and outputs an address match signal when these addresses match, and a counter in response to the address match signal. A coincidence pulse sending unit 14 that compares the signal and the monitoring address and sends out a latch pulse when these values match; and a matching pulse sending unit 14 that latches the input data of the data memory 20 in response to the latch pulse, and transmits the latched data. Only when the data latch section 15 which outputs the data and the setting address supplied from the control memory 30 is received, a match is detected between the output data output from the data memory 20 and the latched data, and the match detection result is output. The data matching detection unit 16 has a data matching detection unit 16.

The monitoring address counter 12 is counted up from 0'' every cycle of the sequential counter 11.The address detection unit 13 detects that the monitoring address output from the monitoring address counter 12 matches the set address of the control memory 30. is detected, the coincidence pulse sending unit 14 transfers the input data of the data memory 20 to the data latch unit 1 at the timing of the monitored address as the setting address of the control memory 30.
Latch at 5. The data match detection unit 16 detects whether or not this latched data matches the data read out from the data memory 20 according to the same set address of the control memory 30 in the next cycle of the sequential counter 11. .

〔Effect of the invention〕

As explained above, the present invention enables line setting by checking the input/output data of the data memory itself at all valid addresses for the setting address of the control memory that determines the input/output data of the data memory. Directly convert the bit string in the data memory that is being
Moreover, there is an effect that monitoring can be performed without omission.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data memory monitoring circuit according to an embodiment of the present invention together with a data memory and its peripheral circuits. 10...Data memory monitoring circuit, 11...Sequential counter, 12...Monitoring address counter, 1
3...Address detection unit, 14...Coincidence pulse sending unit, 15...Data latch unit, 16...Data coincidence detection unit.

Claims (1)

[Claims] 1. In a data memory monitoring circuit that monitors a data memory that stores input data and outputs output data, a sequential counter that counts up in synchronization with the input data and outputs a count signal; A monitoring address counter that counts up every cycle and outputs the monitoring address of the data memory, and a monitoring address counter that detects a match between a set address for controlling the data memory and the monitoring address, and that these addresses match. an address detection unit that outputs an address match signal when the address match signal is reached; and a match pulse that responds to the address match signal, compares the count signal and the monitoring address, and sends out a latch pulse when these values match. a data latch unit that latches the input data and outputs the latched data in response to the latch pulse; and a data latch unit that latches the input data and outputs the latched data in response to the latch pulse; 1. A data memory monitoring circuit comprising: a data coincidence detection section that performs coincidence detection and outputs a coincidence detection result.