JPH02301339A - Bus type information transmitter - Google Patents

Abstract

PURPOSE:To direct the operating direction of an output actuator or the like in the slave station of an automatic machine in the safety side by storing output definition information at a faulty state sent in advance from a master station in an output slave station, storing the level of an output terminal of the output slave station into the state before the generation of a fault at the faulty state according to the storage content or resetting the storage content. CONSTITUTION:The transmission format of serial information by one frame is constituted of a header part, an address part designating a specific slave station, a mode part, a data bit and a reply bit in total 10 and several bits. Depending on the content of the mode part, the case is distinguished into the case of inputting the information from the master station to the slave station, the case of outputting the information to the slave station, and the case of the output whether it is kept to the state before the fault detection or released when the slave station detects the fault of the transmission line. Thus, whether an actuator or the like connecting to the output terminal of the output slave station is held to the state before detection or released when the slave station detects the fault of the transmission line according to the mode part. Thus, the mechanism of the automatic machine is operated in a safe state.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention connects a master station and a plurality of slave stations through a single transmission path, and uses serial information to communicate between the master station and slave stations using one bit. The present invention relates to a bus-type information transmission device that mutually transmits input and output information.

Conventional Technology In recent years, industrial automatic machines have become more sophisticated, and it is not uncommon for machines to use more than 100 sensors and actuators. In addition, automatic machines are organized into lines within factories, and mutual information exchange is almost always necessary. In order to reduce wiring within or between equipment, input/output control units called remote I10s are placed throughout the equipment as slave stations, and the wiring to sensors and actuators is connected to these slave stations. A method of reducing wiring by serially transmitting information by connecting a master station connected to a microcomputer that performs comprehensive control of equipment to a slave station with a single cable has entered the practical stage.

Intel Corporation's BITB in the United States is a bus-type transmission system.
The US Toiro system has been put into practical use. Figure 12 is BIT
It is a diagram of a wiring-saving system using BUS. 1 is a sensor, 2 is an actuator such as a solenoid valve, 3 and 3a
is an input slave station, and 4 is an output slave station. Reference numeral 5 denotes a master station, which exchanges information with these slave stations 3, 4.3a via a transmission line 6, and connects a sensor 1 to the slave stations 3, 4.3a.
．． The state of 1a and the actuator 2 are controlled. 'The transmission line 6 employs a differential type R8485, and connections to each slave station 3, 4, and 3a are made using twisted pair cables. The transmission format for one frame is 5DLC as shown in FIG.

Problems to be Solved by the Invention In the conventional transmission system described above, one frame is small for one address (7 bytes, or 56 bits).Also, it is difficult to obtain sensor input information from a slave station. Then, first, the master station sends information in a format containing the address of the slave station to the slave station over the transmission path, and the process is completed by obtaining information transmitted from the slave station in the same format.

Therefore, to obtain 1 bit of information, more than twice the transmission time of 56 bits is required. And the time is the same even when obtaining 8-bit information.

Many industrial automatic machines have mechanisms that require high-speed movement, and in order to accommodate these movements, high-speed transmission is required because the long transmission format described above would not be able to keep up with the speed. Eliminating malfunctions caused by noise is extremely important for industrial automatic machines, but the problem is that the higher the transmission speed, the more susceptible they become to noise.

On the other hand, industrial automatic machines will operate abnormally if the transmission line between them and the slave stations that control sensors and actuators is disconnected, so it is necessary to constantly monitor whether the slave stations are connected to the bus-type transmission line. For this purpose, communication similar to the above must be performed, and high speed is increasingly required.

Furthermore, if an accident occurs in which the transmission line is disconnected for some reason during the operation of the automatic machine, the movement of the actuator cannot be controlled by the master station, resulting in an unsafe condition.

In view of the above-mentioned problems, the present invention provides a short transmission format to reduce the transmission speed, and when the transmission line is disconnected, the output operation of the actuator, etc. is stored in the state immediately before the disconnection or is turned off. The present invention provides a bus-type information transmission device that can be controlled in a manner that enables the following.

Means for Solving the Problems In order to solve the above problems, the bus type information transmission device of the present invention has a transmission format of serial information for -11 frames in a header part and an address for specifying a specific slave station. It consists of a total of more than 10 bits: a part, a mode part, a data bit, and a response bit, and has the following characteristics.

In the first invention, depending on the contents of the mode section, when the master station inputs information from the slave station, when outputs information to the slave station, and when the slave station detects an abnormality in the transmission path, the output is sent to the abnormality detection. Means for distinguishing when setting whether to maintain the previous state or turning off, and for the slave station to set input information in the data bit specified by the address part when inputting information from the slave station. and means for the master station to set output information in the data bit when outputting, and information for setting whether to maintain the output in the state before the abnormality detection or turn it off when the abnormality is detected. means for setting the data bit by the master station; means for detecting an abnormality in the transmission line provided in the slave station; and storing information set by the master station in the data bit, and outputting the output when the abnormality is detected. It consists of a means to maintain the state before abnormality detection or to turn it off.

A second invention is characterized in that the master station sets the output to the transmission line in a high impedance state at the timing of the response bit;
l by the slave station specified in the address field in the response bit.
a resistor for setting the potential of the transmission line when the corresponding slave station does not exist, and a master station that monitors the potential of the transmission line at the timing of the response bit and determines whether or not a slave station exists. means for the slave station to set input information in the data bits specified in the address field when inputting information from the slave station; and means for the master station to set output information to the data bits when outputting information; It consists of a means for setting.

According to the first invention, with the above configuration, the information of the slave station specified in the address field and the mode field can be immediately input or output as data bits in one frame of serial information. Is the transmission time short (or is it?).Then, when the slave station detects an abnormality in the transmission path, the mode section determines whether the actuator, etc. connected to the output terminal of the output slave station should be kept in the state before the abnormality was detected, or whether it should be turned off. can be set, allowing automatic machine mechanisms to operate in a safe state.

In the second invention, the response bit of the serial information is set to 1 if the slave station specified in the address field and the mode field is normal, so at this timing the master station can determine which slave station is connected to the transmission line. Since it can be immediately determined whether there is a disconnection or a failure, the master station can control the output of other normal slave stations in a safe direction.

Embodiment Hereinafter, a bus-type information transmission device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a master station circuit of a bus-type information transmission device in this embodiment. Reference numeral 9 represents a bus terminal for connection to a bus serving as a signal transmission path. A microcomputer 10 decodes or controls the input/output information of the sensors and actuators of the slave stations through a bus terminal, and exchanges the contents as input and output information with a higher-level control device. o
po.

OPl, OF2 are output lines, IPO, fPl are human power lines, I
RT is an interrupt line. Reference numeral 11 is a 3-state output buffer, and the output state can be controlled into three states: HIGH, LOW, and high impedance. OPI output line is HI
When GH, the state of OPO is output as is, and when the output line of OPI is LOW (=logic 0), it becomes high impedance. 12 is a large power buffer. 13 is a window comparator, when the voltage level of bus terminal 9 is -VE or more +V
When the output is below 1, the output I P 1 is HI GH (=mJ11
). (V E let V S (7) Approximately 1/3
~1/2) Therefore, when the 3-state output buffer 11 is at high impedance and nothing is connected to the bus terminal 9, the voltage level at the bus terminal 9 will be divided by the two resistors R1 and will be about O volts. Output IPI becomes HIGH.

Reference numeral 14 denotes an interval timer, which oscillates at the same cycle as the clock cycle of the serial signal at the bus terminal 9. The output line OPI of the microcomputer 10 operates at HIGH and generates the IPT signal at the above period.

FIG. 2 shows the transmission format for one frame in this embodiment. As shown in the figure, one frame consists of a start bit, 2 bits in the mode part, and ? Address part 5 bits, data bit, parity bit, response bit, stop 3
Consists of bits. The mode section selects an input slave station and an output slave station for the same address, and maintains the output before the error occurs in the event of an error such as a disconnection of the transmission line. , or "turn off the output unconditionally". The address part is for specifying the number of the slave station, and in this embodiment, 5 bits, that is, 32 pieces can be specified. Figure 3~
FIG. 5 shows the signal output waveform from the master station to the bus terminal 9. The start bit must be “1” and the stop part must be “1”.
0". When the data bit is in the input mode as shown in FIG. 3, that is, when the mode part is "01", the 3-state output buffer 11 of the master station is in a high impedance state,
The bus terminal voltage is approximately Ov. Furthermore, in the output mode of FIGS. 4 and 5 and the abnormal output definition mode, the data bit becomes a control signal for the output of the slave station for outputting the address of the master station. When the mode part is "10", the specified slave station is turned on when the data bit is "1", and turned off when it is "0". Also, when the mode part is "Ol", when the slave station detects an abnormality as described later, if the data bit is "1", the output will be turned off unconditionally, and if it is "0", the output will be held. It constitutes the internal circuit of the slave station. Since the parity bit determines the output level of the slave station when the master station is in the input mode, the output buffer 11 of the master station is controlled to a high impedance state. In the output mode, the master station sets the odd parity output of 9 bits from the start bit to the data bit as the parity bit. The response bit represents a response signal from the slave station to the master station, and the output buffer 11 is always in a high impedance state at this timing. Therefore, as described above, by monitoring the output of the window comparator 13 at this timing, the master station can immediately determine whether or not the designated slave station is connected.

In FIG. 6, in order to output the signals as shown in FIG. 3, the microcomputer 10 connects output lines OPO, OPI and input line ip.
The order table for controlling o and tpi is shown. Also, Figure 7 shows the 4th
It is an order table corresponding to the figure. Note that R in the figure indicates reading the voltage level of the bus terminal. The timing of the transition of the sequence number in the order table is determined by the interrupt signal IRT from the interval timer 14.

FIG. 8 shows a circuit configuration diagram of the input slave station in this embodiment. FIG. 9 shows the control timing diagram. In FIG. 8, 9 is the same bus terminal as above, 15.15a is a large power buffer, and 16, 16a.

16b is a 3-state output buffer, 17 + 17
a.

17 b and 17 c are three-man-powered AND gates, 18 is a D flip-flop circuit, and 19 is a parity generation circuit.
Outputs odd parity for 8-bit input. 20 is a timing generation circuit, which receives the signal SI from the bus terminal 9.
Detecting the rising edge of G, SFT, T, , T2 .
It generates signals T,,LD,. 21 is a 7-bit shift register which is controlled by the shift pulse signal SFT.
Serial information is temporarily stored from the bus terminal 9. 22 is a mode determination circuit which decodes the signal of the mode part of the serial information (see Figure 2), and when the content is "01", the IN
Output a signal. 23 is a switch group that specifies the address of the slave station, and +Vcc is 224, which indicates "logic 1".
2 is an address match detection circuit, which outputs a match signal AEQ when the signals of the switch group 23 and the address part of the serial information (see FIG. 2) match. In this figure, '0OIIOJ' is set in the switch group 23 as the address of the slave station.

In Fig. 9, the master station reads the input state of the slave station whose address is '0OIIOJ. When the BUS signal shown in the figure is input to bus terminal 9, the SFT pulse output from timing generation circuit A causes a shift. Register A stores data in the mode section and address section, respectively. Then, since the address matches the address of this slave station, the output AEQ signal of the address coincidence detection circuit 24 becomes "logic 1", and the IN signal of the mode determination circuit 22 becomes "logic 1". Further, the signal level of the sensor signal input terminal 7 is set in the D flip-flop circuit 18 by the LD and pulse signals. Then, at the timing when the T signal is output, the output DI of the D flip-flop circuit 18 that stores the signal level of the sensor signal input terminal 7 is output from the output buffer 16.
The signal is output to the bus terminal 9 via the bus terminal 9 and becomes a data bit.

Furthermore, since the output DI of the D flip-flop 18 is input to the input parity generation circuit 19, the odd parity output of this content and the contents of the mode field and the address field is the next T.
It is output to the bus terminal 9 at the output timing of the two signals and becomes a parity bit. At the timing of the T signal, it is output to the bus terminal 9 as a response bit to the transmission line in the form of logic IJ.The broken line portion of the US signal indicates that the signal level has been determined by the slave station.

FIG. 10 shows a circuit configuration diagram of the output slave station in this embodiment. Items marked with the same numbers as in Figure 8 are
This circuit has exactly the same function as the circuit shown in the figure, and its explanation will be omitted. 17d and 17e are 3-man AND gates, 18a and 1
8b is a 079117077 circuit, 25 is a two-manpower OR gate, 26 is a two-manpower NAND gate, and 27 is a two-manpower output buffer with a NAND gate. Output buffer 27
By setting the output to LOW level, the °r actuator etc. can be turned on. 28 is a timing generation circuit, and bus terminal 9
Detecting the rising edge of the signal S[G from 'E' in FIG.
FT, T3. A signal called LD2 is generated. 29 is a 9-bit shift register, which receives a pre-engineered shift pulse signal SF.
T temporarily stores the serial information from the bus terminal 9. 30 is a parity generation circuit which outputs an even parity output POUT for 9 bits of input information. The mode determination circuit 22 decodes the signal in the mode part of the serial information, and when the content is "l.0", the OUT signal is set to "logic 1".
”, and when it is “11”, the EMG signal is set to “logic 1”. 31 is a bus level abnormality detection circuit which detects that the voltage level of the bus terminal 9 is OV for at least 4 bits of transmission time or more and that the output slave station is not connected to the transmission path. It is constructed using the window comparator, interval timer, etc. (
(not shown) Furthermore, the address of this output slave station is set to '00101 J' by the switch group 23.

FIG. 11 will be explained. In the first frame, the master station outputs "
1", and the second frame sets "logic O" as the definition of abnormal output for the same slave station. First, explaining the first frame, the timing generation circuit 28 detects the rising edge of the SIG signal and outputs nine shift pulse SFT signals. As a result, the mode section, address section, data bit, and parity bit are set in the shift register 29. Since the address part of the serial information is roololJ, the output AEQ signal of the address-number configuration circuit 24 is output at HIGH level. When the contents of the shift register 29 sent from the master station are correctly set, the output POUT of the parity generation circuit 30 becomes a HIGH level because the sum of logical 1 bits is an even number. On the other hand, since the mode part is "lO", the data bit to which the OUT signal is output is "l", so the AND
D flip-flop circuit 18a via gate 17d
"Logic 1" is set to "Logic 1".

When an abnormal signal such as noise enters the transmission path and the contents of the shift register 29 are incorrect, a parity error occurs, and the output of the parity generation circuit 30 becomes LOW level, and the AND gate 17d is not opened, causing a D flip. 70 tubes retain their previous state.

Therefore, if a parity error is found in the serial information, the output remains in its previous state. When the T3 signal is output, the output of the AND gate 17c becomes HIGH level, and the 3-state output buffer 16b is opened.
HrGH (=
Logic l) is output.

In the second frame, when the ninth shift pulse SFT appears, the mode determination circuit 22 outputs an EMG signal. Also, as in the first frame, the address match signal AEQ and the parity output POUT are also at the HIGH level, so the AND gate 17e is opened and the LD2 signal changes the data bit content "0" to the D flip-flop circuit 18b. Set it to Then in this case, AND
The outputs of the gates 2 and 6 go to HIGH level, and the output level of the output terminal 8 controlled by the AND gate 27 is the same as the content of the D flip-flop circuit 18a, so that the abnormality output holding mode is set. On the other hand, if the D flip-flop circuit 18b is set to "1",
When the output of the bus level abnormality detection circuit 31 is at HIGH level, that is, when the slave station is disconnected from the bus terminal 9, the output of the NAD gate 26 becomes LOW level, and the output terminal 8 is turned off unconditionally.

In the above explanation, in order to detect whether serial information on the transmission path is being transmitted correctly between the master station and slave stations, a parity bit is provided in the transmission format, and the address field, mode field, and data bits are Although error detection is performed by calculating all even parities, even if the transmission format is changed to other error detection methods such as sum check or pi-phase code check, the slave station which is the aim of the present invention It goes without saying that the same principle can be used to check for the presence or absence of a bus or to detect a disconnection with the bus.

Effects of the Invention As described above, the present invention connects a master station and a plurality of slave stations through a single transmission path, and mutually transmits input/output information between the master station and slave stations using serial information. In a bus-type transmission system, the serial information transmission format includes an address section and a mode section.

A data bit and a response bit are provided, and the address part specifies the slave station, and the mode part specifies input, output, and output definition in the event of an error. Output definition information in the event of an abnormality is stored, and according to the stored contents, the output terminals of actuators, etc. controlled by the output slave station in the event of an abnormality are maintained in the state before the occurrence of the abnormality, or are turned off unconditionally. The internal circuit is configured to allow this.

Therefore, when a trouble occurs due to an abnormality in the transmission line,
It has the advantage of being able to move the output actuator of a slave station in an automatic machine in a safe direction.

On the other hand, the master station puts the transmission line in a high impedance state at the timing of outputting the response bit in the transmission frame, and the slave station selected by the address section and mode section sets the voltage level of the transmission line to HIGH. Therefore, the master station can monitor the voltage of the transmission line using a built-in window comparator and immediately detect an abnormal condition such as a specified slave station being out of order or disconnected from the transmission line. As a result, other output slave stations can be controlled to be held or turned off on the safe side in the same way as above.

On the other hand, the transmission frame of the present invention is simpler and shorter than the conventional example, and 1-bit human output control information can be exchanged at high speed by sending 1 frame from the master station to the slave station. It can meet the needs for short-time transmission of automatic machines that require high performance.

[Brief explanation of the drawing]

FIG. 1 is a bus type information diagram in one embodiment of the present invention;
Figure 5 is a timing chart of signals output from the master station to the bus based on the same transmission format, and Figure 6 is a diagram showing the input mode, output mode, and output definition mode in the event of an abnormality, respectively. A diagram showing the control order of the control lines of the microcomputer of the master station in the manual mode, FIG. 7 is a diagram showing the same control order in the same output mode, and FIG. 8 is a circuit configuration diagram of the input slave station in the same embodiment. , FIG. 9 is a control timing diagram thereof, FIG. 10 is a circuit configuration diagram of an output slave station in the same embodiment, and FIG. 11 is a control timing diagram thereof.
Figure 12 shows a conventional example of bus type 9...bus terminals,
10...Microcomputer, 11...
...3-state output buffer, 12... Large power buffer, 13... Window comparator, 14
...Interval timer, 16.16a. 16b...3-state output buffer, 18,1
88'. 18b...D flip-flop circuit, 19...
... Parity generation circuit, 20 ... Timing generation circuit, 21 ... Shift register, 22.
...Mode determination circuit, 23...Address setting switch, 24...Address-number configuration circuit, 28...Timing generation circuit, 29...
...Shift register, 30...Parity generation circuit, 31...Bus level abnormality detection circuit, R1,
R2...Resistance. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 2 Figure 3 Figure 4 Parity Figure 5 Figure 12--One person card Figure 6
x---ㅅ、Otoret Figure 7 Figure 9 EQ

Claims (2)

[Claims] (1) Bus-type information in which a master station and multiple slave stations are connected in a seamless manner through a single transmission line, and the master station and slave stations mutually transmit 1-bit digital input/output information using serial information. In the transmission device, the serial information consists of a header section, an address section for specifying a specific slave station, a mode section, and data bits, and the master station receives information from the slave station according to the contents of the mode section. It is possible to distinguish between inputting information, outputting information to a slave station, and setting whether to maintain the output state before the abnormality detection or turn off the output when the slave station detects an abnormality in the transmission path. , means for the slave station to set input information in the data bits specified by the address section when inputting information from the slave station, and means for the master station to set output information in the data bits when outputting information. and means for the master station to set information in the data bits to set the output to maintain the state before the abnormality detection or to turn off the output when the abnormality is detected, and a transmission path provided in the slave station. The device comprises means for detecting an abnormality, and means for storing information set by the master station in the data bit, and when detecting the abnormality, maintains the output in the state before the abnormality detection or turns off the output. A bus-type information transmission device featuring: (2) Bus-type information in which a master station and multiple slave stations are connected in a seamless manner through a single transmission path, and the master station and slave stations mutually transmit 1-bit digital input/output information using serial information. In the transmission device, the serial information consists of a header section, an address section for specifying a specific slave station, a data bit, and a response bit, and at the timing of the response bit, the master station outputs to the transmission path. means for setting the response bit to 1 by the slave station specified in the address section; a resistor for setting the potential of the transmission line when the corresponding slave station does not exist; means for monitoring the potential of the transmission path at the timing of the response bit and determining whether a slave station exists; 1. A bus type information transmission device comprising means for setting information, and means for a master station to set output information in the data bits when outputting information to a slave station.