JPS61154334A - Time slot diagnose system - Google Patents

Abstract

PURPOSE:To obtain a data highway system with high reliability by applying self-diagnosis to a time slot detection circuit group in each communication controller. CONSTITUTION:When a data arrives in a communication controller and a synchronizing flag detecting circuit 41 detects a synchronizing flag, a time slot TS counter circuit 43 counts a TS, the count is used as a TS number and transmitted to a TS comparison circuit 51 via a TS switching circuit 46. The circuit 51 compares the TS number set in a TS setting circuit 52 with the TS number from the circuit 43, and when they are coincident, a data in the TS is stored in a register 47 in the line adaptor part 62 and transmitted to a data terminal device 61. A TS number of the adaptor part 62 being an object of diagnosis execution is written to a line control address register LCAR 54 of a microprocessor uPC 64 at a reception time band of a frame header, transmitted to the circuit 51 via the circuit 46, the result of comparison is written in an external register of the uPC 64, and when the TS number transmitted by the uPC 64 and the TS number set by the circuit 52 are coincident, it is discriminated that the circuits 51, 52 are operated normally.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data highway system, and in particular, at least one highway monitoring device and a plurality of communication control devices are connected to a circular data transmission path, and the data The present invention relates to a time slot diagnosis method in a time division multiplex data highway system in which time slots in frames flowing on a transmission path are fixedly assigned to each communication control device and data is exchanged between the communication control devices.

[Conventional technology]

In recent years, data highway systems that apply optical communication technology have been actively developed. In the time division multiplex data highway system, each communication control device is given a fixed time slot number (address), and the arrived time slot number is compared with the time slot number given to its own device. A method is used in which data is received in a time slot and data is written into the time slot.

[Problem that the invention seeks to solve]

By the way, in such a system, when the used time slot setting circuit and the time slot comparison circuit stop working properly for some reason, they may communicate with a totally unrelated communication control device, or Data communication may become impossible. When such a situation occurs, communication of all communication control devices connected to the circular data transmission path must be temporarily interrupted, and many system maintainers must spend a great deal of time to find the fault. No.

An object of the present invention is to provide a highly reliable data highway system by self-diagnosing the time slot detection circuit group in each communication control device in order to eliminate the above drawbacks. It is in.

[Means for Solving the Problems] In order to solve the above problems, the present invention connects at least one highway monitoring device and a plurality of communication control devices to a circular data transmission path, and connects at least one highway monitoring device and a plurality of communication control devices to the data transmission path. 2 time slots in the frame flowing through are fixedly assigned to each of the communication control devices, and when the communication control device detects the time slot corresponding to its own device using a time slot detection circuit provided within its own device. In a time division multiplexing data highway system that transmits and receives data using the time slots, the communication control device includes means for providing a diagnostic time slot number to the time slot detection section, and the time slot detection section. means for reading and checking the output of the time slot detector, and providing the diagnostic time slot number to the time slot detector in a time zone other than the time zone in which the allocated time slot is received from the data transmission path; It is characterized by being configured to check the normality of.

[For production]

The present invention includes a circuit unit that provides a diagnostic time slot number to a time slot detection unit provided in a communication control device on the data highway, instead of a normal time slot number detected from data on the data highway. In addition, a circuit section is provided to read and check the output (match/mismatch information@) of the time slot detection section.
The diagnosis of the time slot detection unit is performed during a time period when a time slot is not supposed to arrive.

Malfunction of the time slot detection unit may cause communication confusion and lead to system down. However, according to the present invention, the normality of the time slot detection unit can be checked as appropriate, and in the event of an abnormality, the system can be checked immediately. By taking measures such as disconnecting the communication control device, it is possible to prevent situations such as system down.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a diagram showing the concept of a data highway system. 1 is a circular data transmission line, 2 is a highway monitoring device,
3 to 12 are communication control devices, 13 is a network monitoring device, and 14 to 23 are data terminals. The highway monitoring device 2 transmits original frames, adjusts loop-to-circle delay times, and monitors failure states of the communication control devices 14 to 23 connected to the circular data transmission path. The network monitoring device 13 has a function of displaying various types of information collected by the highway monitoring device 2 and sending various commands to the highway monitoring device 2 by key-in from an operator.

FIG. 3 is a diagram showing frames flowing on the circular data transmission path used in the present invention. As is clear from the figure, a frame consists of a frame header section and a time slot section.

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention. In the figure, 31 is an input side transmission line, 32 is an output side transmission line, 33 is a receiver circuit, 34 is a descrambling circuit, 35 is a serial/parallel conversion register, 36, 37 is a data buffer register, and 38 is a parallel transmission line with a switch. /Serial conversion register, 39 is a scramble circuit, 40 is a driver circuit, 4
1 is a synchronization flag detection circuit, 42 is a clock circuit, 43 is a time slot counter circuit, 44 is a data switching circuit,
45 is a data register, 46 is a time slot switching circuit, 47 is a reception data buffer register, 48 is a parallel/serial conversion register, 49 is a transmission buffer register, 50 is a serial/parallel conversion register, 51 is a time slot comparison circuit,
52 is a time slot setting circuit, 53 is a microprocessor, 54 is a line control address register (LCAR), and 55 is a read-only memory (R
OM), 56 is random access memory (RAM)
, 57 is the MPU common bus, 58 is the data in bus, 59
is the data out bus, 60 is the time slot hash, 61
62 is a data terminal, 62 is a line correspondence section, 63 is an external register, 64 is a microprocessor section, and 65 is a line control data register (LCDR).

The operation of the embodiment is as follows.

First, when power is turned on to the communication control device, the microprocessor (MPU) 53, read-only memory
(ROM) 55, random access memory (RAM)
) 56, the MPU common bus 57 writes into the line control data register (LCDR) 65 the time slot number used by each line corresponding section 62 of the own communication control device. The written time slot number is written to the time slot setting circuit 52 via the data switching circuit 44 and the data out bus 59.

The transmission data generated at the data terminal 61 is transmitted to the line corresponding section 6
The signal is temporarily stored in the transmission buffer register 49 via the serial/parallel conversion register 50 in 2.

The frame that enters from the input side transmission line 31 is sent to the receiver circuit 3
3. Descrambling circuit 34, series/parallel ripple circuit 3
9. The signal is sent to the output transmission line 32 via the driver circuit 40.

When a frame arrives, the synchronization flag detection circuit 41 starts detecting the synchronization flag. It is sent to the time slot comparison circuit 51 via the synchronization flag loft switching circuit 46 and the time slot bus 60.

The time slot comparison circuit 51 compares the time slot number set by the time slot setting circuit 52 and the time slot number sent from the time slot counter circuit 43. If the comparison results in a match, the time slot is addressed to the own line corresponding unit, so the data in the time slot is temporarily stored in the received data buffer register 47 in the line corresponding unit 62, and parallel/serial conversion is performed. It is sent to the data terminal 61 via the register 48.

On the other hand, data from the data terminal 61 is stored in the transmission bus register 49, so the data input bus 5
8. The data is sent to data buffer registers (36, 37, 38) at appropriate locations via the data register 45, and sent to the output side transmission line 32 via the scramble circuit 39 and driver circuit 40.

What has been described above is the operation during time slot reception, and the present invention further adds the operation described below during frame header reception to ensure the normality of the time slot setting circuit 52 and the time slot comparison circuit 51. A function to check using the microprocessor unit 64 has been added.

The time zone of the frame header is the time slot counter 4.
3 is not working. During the time period, write the time slot number of the line corresponding section to which the diagnosis is to be performed in the line control address register (LCAR) 54,
Time slot switching circuit 46, time slot bus 60
The comparison result is sent to the time slot comparison circuit 51 via the external register 63 of the microprocessor section 64.
Since the time slot number sent by the microprocessor unit 64 matches the time slot number set in the time slot setting circuit 52, the time slot setting circuit 52 and the time slot comparison circuit 51 are normal. This makes it possible to determine that the system is operating properly.

〔Effect of the invention〕

As explained above, in the present invention, during the frame header reception period, the microprocessor section instructs the time slot number to be diagnosed, and the time slot number set in the time slot setting circuit and the designated time By comparing the slot numbers, it can be determined whether the time slot setting circuit and the time slot comparison circuit are operating normally. As a result, in the present invention, it is possible to check the normality of the time slot detection circuit that should always be used, and even in the event of a failure, the defective location can be found without stopping the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention, FIG. 2 is a diagram showing the concept of a data highway system, and FIG. 3 is a diagram showing frames flowing on a circular data transmission path used in the present invention. It is. In FIG. 1, 43 is a time slot counter circuit;
46 is a timeslot switching circuit, 51 is a timeslot comparison circuit, 52 is a timeslot setting circuit, 53 is a microprocessor, 54 is a line control address register, 64 is a microprocessor section, 65 is a line control data register. It is a register. -y? '、"＋、・

Claims (1)

[Claims] At least one highway monitoring device and a plurality of communication control devices are connected to a circular data transmission path, time slots within a frame flowing on the data transmission path are fixedly assigned to each of the communication control devices, and the communication control device is controlled by When a device detects the time slot corresponding to the device using a time slot detection circuit provided within the device, the device uses the time slot to transmit and receive data. A control device is provided with means for giving a diagnosis time slot number to the time slot detection section, and means for reading and checking the output of the time slot detection section, and receiving the assigned time slot from the data transmission path. A time slot diagnosis method characterized in that the diagnosis time slot number is given to the time slot detection unit in a time zone other than the time slot, and the normality of the time slot detection unit is checked.