JPH0349438A - Common bus monitoring and processing system - Google Patents

Abstract

PURPOSE:To detect the presence or absence of a fault on a common bus without increasing the number of common buses by comparing the same test patterns sent through different common buses. CONSTITUTION:A demultiplex section 4 demultiplexing a multiplex frame consists of a means 44 generating a test pattern comprising an optional bit pattern and a means 45 inserting the generated test pattern to a frame header of the multiplex frame, and a low speed interface section 5 forming an interface at a terminal equipment side is provided with a means 52 detecting a time slot location of the test pattern from a frame header of a frame to be sent, and a means 53 detecting the occurrence of a data error by comparing the test pattern on the common bus 6 with the test pattern on other common bus 6 when a time slot location is detected. Thus, the occurrence of a fault on the common bus is detected without increasing the number of common buses.

Description

[Detailed Description of the Invention] [Summary] Common bus monitoring processing in a communication system configured to separate multiple frames multiplexed according to a time division multiplexing method and transmit them to a terminal side interface via a common bus. Regarding the method, without increasing the number of common buses,
The demultiplexer, which separates multiplexed frames for the purpose of detecting the occurrence of an abnormality on the common bus, includes a means for generating a test pattern consisting of an arbitrary bit pattern, and a means for generating a test pattern consisting of an arbitrary bit pattern, and a means for converting the generated test pattern into the frame header of the multiplexed frame. The low-speed interface section forming the terminal side interface includes means for detecting the time slot position of the test pattern from the frame header of the transmitted frame, and means for detecting the time slot position. Sometimes, it is a means to detect whether a data error has occurred by comparing the test pattern on the common bus on which the time slot of the data used by itself is carried with the test pattern on other common buses. We will arrange to prepare for this. [Industrial Application Field] The present invention relates to common bus monitoring in a communication system that separates multiple frames multiplexed according to a time division multiplexing method and transmits the separated frames to a terminal side interface via a common bus. The present invention relates to a processing method, and particularly relates to a common bus monitoring processing method that makes it possible to detect whether or not an abnormality has occurred on a common bus without increasing the number of buses on the common bus.

In a communication system that performs data transmission according to the time division multiplexing method, a configuration is adopted in which multiplexed frames sent from the main line are separated and transmitted to multiple terminal side interfaces via a common bus. In such a configuration, if an abnormality occurs on the common bus, abnormal data will be sent to the terminal side interface, resulting in incorrect data processing. From now on, it will be necessary to provide a means to monitor the common bus, but in order to simplify the device configuration, it is possible to implement this means without increasing the number of common buses. preferable.

[Conventional technology]

For example, in a communication system such as a LAN, as shown in FIG.
The precept will be to connect with and,
As shown in FIG. 5, each of these nodes 2 includes a demultiplexer 4 that separates multiplexed frames transmitted via the communication line 1, and a demultiplexer 4 that receives frames separated by the demultiplexer 4. A low-speed interface section 5 serving as an interface for the terminal 3 is provided, and data transmission is performed according to a common bus 6 provided between the demultiplexing section 4 and the low-speed interface section 5. ing. FIG. 6 illustrates the structure of data transmission between the demultiplexer 4 and the low-speed interface 5. As shown in this figure, the demultiplexer 40 of the demultiplexer 4 separates the multiplexed frames transmitted via the communication line l and distributes them to the low-speed common bus 6, and also controls the control means of the low-speed interface unit 5. 50 detects the time slot position allocated to its own low-speed interface section 5 by counting the time slot clocks sent from the demultiplexing section 4, and selects the corresponding game 1-50.
By controlling the opening of 51-t, the necessary data transmission is realized. Here, 7 is a control line for transmitting a time slot clock (a clock synchronized with the time slot of a frame) and a frame start pulse (a pulse representing the start time of a transmission frame).

In such a structure, conventionally, a method using a parity check method has been used to detect the occurrence of a failure in the common bus 6 that performs data transmission between the demultiplexing section 4 and the low-speed interface section 5. I was hiring. In other words, by adding a parity bit and performing a parity check on the bits of the data received on the low-speed interface section 5 side, it is possible to detect whether or not a fault has occurred in the common bus 6. be.

[Problem to be solved by the invention]

However, when the parity check method is used, it is necessary to add one bus to the data path in order to transmit the parity bit. Accordingly, this prior art has the problem that in order to monitor the common bus 6, the number of buses must be increased by the number of bus groups separated by the demultiplexer means 40. For this,
If the number of interface lines that can be used in the low-speed interface unit 5 is limited, there is a problem in that a monitoring system for the common bus 6 cannot be provided. Furthermore, since it is necessary to provide a parity check circuit for each bus, there is also the problem that the circuit scale of the low-speed interface section 5 becomes large.

The present invention has been made in view of the above circumstances, and provides a communication system in which multiple frames are separated and transmitted to a terminal side interface via a common bus.
The purpose of this paper is to provide a new common bus monitoring processing method that can detect the occurrence of an abnormality on a common bus without increasing the number of buses. [Means for Solving the Problems] FIG. 1 is a diagram showing the principle structure of the present invention.

In the figure, the same parts as those explained in FIG. 6 are indicated by the same symbols. Reference numeral 41 denotes clock generation means, including a frame start pulse generation stage 42 for generating a pulse synchronized with the start point of transmission of a separated frame, and a time slot for generating a time slot crosslock synchronized with the time slot of the frame. 44 is a test pattern generation means that generates a test pattern consisting of an arbitrary bit pattern; 45 is a test pattern insertion means that generates a test pattern generated by the test pattern generation means 44; 51a is a test pattern for inserting a test pattern into the frame header of a multiplex frame;
It is one of the gates of the game 1.51-i explained in the figure, and opens and closes the common bus 6 on which the time slot assigned for the low-speed interface section 5 is installed. What is the gate, 5lb is the 6th
The gates other than the gate 51a among the gates 51-i and 52 are test time slot detection means, which count the time slot clocks transmitted from the clock generation means 4l. , detecting the time slot position where the test pattern is inserted from the frame header of the transmitted frame; 5
Reference numeral 3 denotes a comparison means, which compares the test pattern passing through the gate 51a and the test pattern passing through one of the selected data 5lb.

[Effect]

In the present invention, when the test time slot position provided in the frame header of a multiplex frame is detected according to the frame start pulse and time slot clock generated by the clock generating means 4l, the test pattern insertion stage 45 performs the following steps. A process of inserting a test pattern of an arbitrary bit pattern generated by the test pattern generating means 44 into the test time slot is executed. When the test pattern is inserted into the frame header of the multiplexed frame in this way, the demultiplexer means 40 allocates this test pattern to the frame header of each frame to be separated when the multiplexed frame is separated, and each common bus 6 to the low-speed interface section 5.

On the other hand, the test time slot detection means 52 inserts a test pattern from the frame header of the transmitted frame in accordance with the transmitted frame start pulse from the clock generation stage 41 and the time slot clock. When the test time slot position is detected,
Control is performed to open the gate 51a and any one of the gates 5lb. In this way, the same test patterns transmitted via different common buses 6 are input to the comparison stage 53, and when the two test patterns are the same, the comparison means 53 The common bus 6 between the separation unit 4 and the low-speed interface unit 5 is determined to be normal, and conversely, when it is different, it is determined to be abnormal.
Processing is performed to output a display signal to that effect.

As described above, in the present invention, the common bus 6 between the demultiplexer 4 and the low-speed interface 5 can be monitored without adding the number of buses. Moreover, since the test pattern generated by the test pattern generating means 44 is not limited to a specific one, the common bus 6 can be monitored with high reliability. (Examples) Hereinafter, the present invention will be explained in detail according to Examples.

FIG. 2 shows the structure of an embodiment of the present invention. In the figure, the same parts as those explained in FIG. 1 and FIG. 6 are indicated by the same symbols. Reference numeral 45a denotes an insertion time slot detection means, which detects the insertion of a test pattern provided in the frame header of multiple frames by counting the generated time slot clocks starting from the generated frame start pulse. 45b is a selector means for detecting the time slot position, and when the insertion time slot detection stage 45a detects the test time slot position, the test pattern generated by the test pattern generation means 44 is transferred to the demultiplexer. 54 outputs the transmitted multiplexed frame to the demultiplexer means 40 when the insertion time slot detection means 45a detects a time slot position other than the test time slot position; First output gate, an even number of which are provided}5 1-
i (i=0 to n, where n is an odd number) that opens and closes the output of the gate 51-i assigned with an odd number in accordance with a control signal from the control means 50, 55
is the second output gate, and an even number of gates are provided}
Gates 51- to which even numbers are assigned within 51-i
56 is a monitoring result output gate which outputs the comparison result of the comparison means 53 in accordance with the control signal from the control means 50.

In this system, each low-speed interface section 5 of the plurality of low-speed interface sections 5 is assigned in advance which identification number of the common bus 6 to be used. That is, for example, the low-speed interface unit 5 in the figure is configured to know that there is a time slot assigned to it on the common bus 6 with the identification number #0. Next, the operation of the embodiment configured in this manner will be explained. The insertion time slot detection means 45a has a multiplex filter L/-4.
When detecting the test time slot position provided in the frame header, the selector stage 45b sends the test pattern generated by the test pattern generating means 44 to the demultiplexer means 40 while the time slot position is being detected. Process to output. In this way,
When a test pattern is inserted into the test time slot of the frame header of a multiplexed frame, the frame headers of all the frames on the common bus 6 identified by #0 to #n in the figure are inserted according to the processing of the demultiplexer means 40. The same test pattern is inserted into the test pattern and transmitted to the low-speed interface section 5. On the other hand, the 1,000-stage control 50 of the low-speed interface section 5
The system counts the transmitted time slot clock starting from the transmitted frame start pulse, and when it detects the test time slot position provided in the frame header of the transmitted frame, it automatically Opens the gate 51-j connected to the common bus 6 on which the data time slot used by game} 5 1 −(j+1
) is opened, and other games connected to the common bus 6}51-i are not opened. At this time, the monitoring result output gate 56 is also opened, and the first output gate 54 and the second output gate 55 are not opened in order to prevent the test pattern from flowing to the subsequent stage. Process. When the gates are controlled in this way, the same test pattern transmitted via different common buses 6 will be input to the comparison means 53. Based on this test pattern, the comparison stage 53 determines that when the two test patterns are detected as the same, the common bus 6 between the demultiplexer 4 and the low-speed interface 5 is normal. It is determined that an output signal to that effect is output to the subsequent stage via the opened monitoring result output gate 56, and when it is detected that the two test patterns are not the same, the common bus 6 is abnormal. By determining this and outputting an output signal to that effect to the subsequent stage, the common bus 6 monitoring process is executed.

Then, when the control means 50 detects the time slot position of the original data transmitted following the frame header by counting the transmitted time slot clocks, the control means 50 detects the time slot position of the original data transmitted following the frame header, and then detects the time slot position of the original data transmitted following the frame header. The game 51-j connected to the common bus 6 is opened again, and the other games 5Li connected to the common bus 6 are not opened. And at this time,
The original signal that is transmitted is opened by opening the output gate connected to the first output gate 54 or the second output gate 55 and closing the other output gate. The data will be processed to be output to the subsequent stage, and the necessary data transmission will be executed. Note that at this time, the monitoring result output game 156 is controlled to be closed because the test pattern signals are not being compared.

FIG. 3 shows a time chart of the gate opening/closing control explained above. In the figure, C' represents the tie that opens and closes the gate 51-i, "d" represents the tie that opens and closes the first and second output gates 54 and 55, and e" is the opening/closing tie ξ of the monitoring result output gate 56
It represents the Although the illustrated embodiments have been described above, the present invention is not limited thereto. For example, in the embodiment, in order to simplify the configuration of the low-speed interface section 5, the common bus 6 is divided into those with even and odd identification numbers, and the assigned common buses 6 are assigned even identification numbers. , the common bus 6 having an odd identification number is selected as the common bus 6 to be compared;
Although a process has been disclosed in which when the assigned common bus 6 has an odd identification number, the common bus 6 with an even identification number is selected as the common bus 6 to be compared. It is not limited to . [Effects of the Invention] As explained above, according to the present invention, it becomes possible to monitor the common bus 6 between the demultiplexer 4 and the low-speed interface 5 without increasing the number of buses. Moreover, since the test pattern generated by the test pattern generating means 44 is not limited to a specific one, the common bus 6 can be monitored with high reliability.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle structure of the present invention, Figure 2 is a diagram of an embodiment of the invention, Figure 3 is a time chart of gate opening/closing control, timing diagrams Figures 4, 5, and 6. The figure is an explanatory diagram for explaining the conventional technology. In the figure, 1 is a communication line, 2 is a node, 3 is a terminal, 4 is a demultiplexer, 5 is a low-speed interface, 6 is a common bus, and 7
4o is a control line, 4o is a demultiplexer means, 44 is a test pattern generation means, 45 is a test pattern insertion means, 50 is a control means, 5l is a gate, 53 is a comparison means, 5
4 is the first output gate, 55 is the second output gate, 56
is the monitoring result output gate.

Claims (1)

[Scope of Claims] A demultiplexing unit (4) that separates multiplexed frames multiplexed according to a time division multiplexing method, a plurality of low-speed interface units (5) that receive the separated frames, and the demultiplexing unit (4) and a common bus (6) that performs frame transmission by commonly connecting the low-speed interface section (5), and the low-speed interface section (5) is allocated to itself. In a communication system that processes frames transmitted via a common bus (6) so as to select and output them, the demultiplexer (4) includes test pattern generation means for generating a test pattern consisting of an arbitrary bit pattern. (44
), and test pattern insertion means (45) for inserting the generated test pattern into the frame header of the multiplex frame.
and the low-speed interface section (5).
The test time slot detection means (52) detects the time slot position of the test pattern from the frame header of the transmitted frame, and when the time slot position is detected, the test time slot detection means (52) detects the time slot position of the test pattern from the frame header of the frame being transmitted. By comparing the test pattern transmitted via the common bus (6) on which the time slot is carried with the test pattern transmitted via another common bus (6), data errors can be detected. A common bus monitoring processing method characterized by comprising a comparison means (53) for detecting the presence or absence of a common bus.