JPH0682762B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a position detection mark for setting mutual positions of pattern formation.

[Prior Art] Conventionally, in a manufacturing process of a semiconductor device, required elements are formed on a main surface of a semiconductor wafer by sequentially laminating diffusion layers, thin layers, and the like, which include a plurality of steps. In order to set mutual positions for pattern formation, a position detection mark is usually formed on a part of a semiconductor wafer, and the position of the pattern in each process is set by detecting this position detection mark in a subsequent process. This position detection mark needs to be sequentially formed for each of a plurality of steps that require position adjustment, in order to perform position adjustment with high accuracy.

For example, in the step of opening the element contact hole, it is necessary to form an alignment mark for aligning the pattern of the electrode wiring layer in a later step. FIG. 3 is a sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. As shown in FIG. 3, the contact hole A is formed by opening the insulating film 7 covering the element forming region, and at the same time, the opening B is used as an alignment mark on the insulating film 7 on the region other than the element forming region. To form. The step of the opening B is used as it is as an alignment mark to carry out the electrode wiring in the next step.

[Problems to be Solved by the Invention]

The conventional semiconductor device described above has a drawback in that the upper layer wiring is broken due to the step of the contact hole, as compared with the multilayer wiring structure which has been accompanied by the recent high integration of semiconductor chips. Therefore, in order to facilitate the formation of the upper electrode wiring layer, a structure in which the inside of the contact hole is filled with a conductive material such as polycrystalline silicon to flatten the surface of the contact hole is recently used. However, in such a structure, since the opening used as the alignment mark has almost the same width as the contact hole, when the contact hole is buried, the opening is also buried and the surface of the opening is flattened. However, there is a drawback that at the time of alignment, the signal intensity of the reflected light from the alignment mark and the analysis light cannot be sufficiently obtained, and it does not serve as the alignment mark. To avoid this problem, the surface of the semiconductor wafer is partially etched to form a level difference, which is used as a position detection mark in a process independent from the process of opening the element contact hole, and the position of the electrode wiring pattern is aligned with this. It is also possible to do.
However, in this case, since the electrode wiring pattern is not directly aligned with the element contact pattern, there is a drawback that mutual alignment cannot be performed with high precision.

An object of the present invention is to provide a semiconductor device in which the alignment mark exists even when the inside of the contact hole is filled with polycrystalline silicon or the like.

[Means for Solving the Problems]

In the semiconductor device of the present invention, a conductive material is embedded in an insulating film provided on an element formation region divided by a field insulating film on one main upper surface of a semiconductor substrate and a first opening provided in the insulating film. And a recess formed in the upper surface of the conductor material in which a second opening having a width that is twice or more the width of the contact hole is buried in a region other than the element formation region. Composed of.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of a semiconductor device of the present invention, and FIGS. 2 (a) and 2 (b) are first views.
FIG. 8 is a cross-sectional view of the semiconductor chip in process order for explaining the manufacturing method of the example in the drawing. In this embodiment, the manufacturing process of a MOS transistor will be described as an example.

As shown in FIG. 2 (a), an element formation region is formed by forming a field oxide film 2 on the main surface of the P-type silicon substrate 1. In this element formation region, an N ⁺ diffusion region layer 6 serving as a source and a drain, a gate oxide film 3, for example 0.35
μm thick polycrystalline silicon gate electrode 4, eg 0.02
An oxide film 5 having a thickness of μm is sequentially formed. Next, the phosphosilicate glass film 7 is deposited on the entire surface of the substrate to a thickness of 0.8 μm, for example. Next, a contact hole A for the source / drain diffusion layer of the transistor is formed, for example, with an opening width of 1.0 μm,
Open at a depth of 0.8 μm. At the same time, the position detection mark forming opening B is opened, for example, with an opening width of 2.4 μm and a depth of 1.0 μm. Next, as shown in FIG. 2 (b), phosphorus-doped polycrystalline silicon 8 having a low resistance is deposited to a thickness of, for example, 1.5 μm by a vapor phase epitaxy method. At this time, the polycrystalline silicon 8 is in a state of being almost flat on the contact hole A having a small width dimension, but on the wide opening B is about 0.
A recess 9a of about 6 μm is generated. Next, the polycrystalline silicon 8 is anisotropically dry-etched until the phosphosilicate glass film 7 is exposed, as shown in FIG.
On the contact hole A, a flat polycrystalline silicon surface is obtained, and on the opening B, the recess 9a remains as the recess 9b and can be used as a position detection mark.

In the present embodiment, polycrystalline silicon was used as the material for filling the opening, but other conductor materials can achieve the same effect.

〔The invention's effect〕

As described above, according to the present invention, the width of the contact hole is 2
By opening an opening having a width more than twice as large as the contact hole at the same time, even if a conductor material is embedded in the contact hole, a recess that can be used as a position detection mark exists on the opening. That is, since the position detection mark can be formed in the same process as the formation of the element contact hole, it is possible to prevent an increase in the number of manufacturing steps, and at the same time, to perform alignment with the element contact pattern using the position detection mark. There is an effect that relative position error can be eliminated and highly accurate position setting can be performed.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of a semiconductor device of the present invention, and FIGS. 2 (a) and 2 (b) are first views.
FIG. 3 is a sectional view of a semiconductor chip showing the order of steps for explaining the manufacturing method of the embodiment shown in the figure, and FIG. 3 is a sectional view of the semiconductor chip for explaining an example of a conventional semiconductor device. 1 ... P-type silicon substrate, 2 ... field oxide film, 3
...... Gate oxide film, 4 …… Polycrystalline silicon gate electrode,
5 ... Oxide film, 6 ... N ⁺ type diffusion layer, 7 ... Phosphosilicate glass film, 8 ... Polycrystalline silicon, 9a, 9b ... Recesses.

Claims (1)

[Claims] 1. An insulating film provided on an element forming region divided by a field insulating film on one main upper surface of a semiconductor substrate, and a conductor material embedded in a first opening provided in the insulating film. The formed contact hole and the second formed in a region other than the element formation region with a width twice or more the width of the contact hole.
And a recess formed on the upper surface of the conductor material in which the opening of the semiconductor device is embedded.