JPH0684733A - Semiconductor integrated circuit device, its manufacture, and semiconductor integrated circuit manufacturing device - Google Patents

Abstract

PURPOSE:To use an optical alignment detecting method when two devices formed on different substrates are overlapped. CONSTITUTION:A substrate 120 provided with a semiconductor integrated circuit device on its front surface and a groove 100 on its rear surface is used. A reference pattern 100 is formed on the rear surface of the substrate 120 and, after aligning the substrate 120 by using the pattern 100, the pattern 50 of the semiconductor integrated circuit device on the front surface of the substrate is formed. Since the substrate has the reference pattern 100 on its rear surface, semiconductor integrated circuits formed on the surfaces of two substrates can be stuck to each other with extremely high accuracy. In addition, when an alignment pattern is formed on the rear surface of the substrate, a manufacturing method by which a semiconductor integrated circuit device can be formed on the surface of the substrate with high accuracy even when the surface of the substrate becomes invisible from an optical system for alignment can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device suitable for miniaturization capable of high integration and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a planer semiconductor device forming technique in which semiconductor devices are integrated and formed on a semiconductor substrate, fine processing has become possible by using a photoresist method. This is because the photoresist method can perform fine patterning of about the wavelength of light by using optical resolution. Further, in the photoresist method, "positioning" for correcting the patterning position of the next formed layer can be performed by optically detecting the pattern position of the previously formed layer. The outline of the photoresist method will be described below.

In a typical photoresist method, a photosensitive organic material (resist) is applied on a semiconductor substrate, a shadow is projected onto a mask pattern shape by a projector to expose it, and the resist is removed from the exposed area by a developing process. However, this is a method of accurately reproducing the original mask pattern on the substrate. For example, when forming a groove on the substrate surface, a groove pattern having a desired pattern can be formed by forming a groove pattern with a resist and anisotropically etching the substrate using this resist as a mask.

The planar semiconductor device forming technique is to deposit a plurality of layers while processing them by using this photoresist method. With this planar semiconductor device forming technique, a semiconductor device having necessary electric characteristics is formed. In order to stack these multiple layers, when processing,
It is necessary to match the pattern exactly with the other layers.
Therefore, first, a groove serving as a reference pattern is formed on the substrate, and then, when patterning by the photoresist method, alignment is performed. In the alignment, the light beam is partially scanned on the substrate before the actual resist exposure.
By analyzing the reflected light from the reference pattern during the scan, the position of the reference pattern is accurately captured. Then, when the resist is exposed, by correcting the relative position with respect to the reference position, the mask pattern can be accurately overlapped with another layer.

FIG. 6 is a diagram showing a conventional pattern alignment method. When the groove and the cap layer 61 corresponding to the metal wiring layer are formed on the semiconductor substrate by using the conventional technique, first, as shown in FIG. 6, the relative position of the groove 100, which is the reference pattern, formed on the substrate surface. The groove 50 is formed by aligning with. Next, the cap layer 61
The cap layer 61 can be formed so as to cover the groove 50 by aligning the reference pattern 100 also when forming the groove.

[0006]

However, as shown in FIG. 7, when two devices formed on different substrates are stacked, the reference patterns of grooves 100 and 110 are formed on the bonding surface. Therefore, the grooves 100 and 110 cannot be detected, and there arises a problem that the above optical alignment detection method cannot be used.

Therefore, the present invention provides a semiconductor integrated circuit device which can use an optical alignment detection method when stacking two devices formed on different substrates, and a manufacturing method thereof.

[0008]

As shown in FIG. 4, a semiconductor integrated circuit is formed on the front surface and a substrate 120 having a groove 100 on the back surface is used.

Further, as shown in FIGS. 2 and 3, a reference pattern 100 is formed on the back surface of the substrate, alignment is performed using the reference pattern 100, and then the pattern of the semiconductor integrated circuit device is formed on the front surface of the substrate. A semiconductor integrated circuit device is manufactured by the manufacturing method for forming.

Further, in order to realize the manufacturing method, a semiconductor integrated circuit manufacturing apparatus for aligning the substrate using a groove formed on the back surface of the substrate is used.

[0011]

When the substrate 121 similar to the substrate 120 is joined,
Cap 61 of substrate 120 and cap 62 of substrate 121
Both pattern positions of the groove 10 formed on the back surface
The relative position between 0 and the groove 110 can be accurately obtained. Therefore, the substrate 120 and the substrate 121 can be connected without directly observing the cap 61 and the cap 62.

Further, since the reference pattern 110 is formed on the side opposite to the joint surface, an optical alignment detection method can be used.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An outline of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be described with reference to FIGS. Figure 1
Is a plane layout, but the groove 100 is arranged on the back surface of the substrate. Here, two of the groove 100 and the cap 61 are schematically illustrated.
An example of two patterns is shown as a typical structure. The cap layer 61 corresponds to the metal wiring layer in the semiconductor integrated circuit device.

FIG. 2 shows a substrate 120 forming the semiconductor integrated circuit device of the present invention. The substrate 120 has the groove 50 formed on the front surface thereof, and the groove 100 is formed on the rear surface of the substrate. The groove 50 is formed as a result of patterning by determining the relative position with respect to the groove 100.

In FIG. 3, when forming the cap layer 61 arranged so as to cover the groove 50, the relative position to the groove 100 formed on the back surface of the substrate 120 is determined to determine the pattern position on the substrate surface. .

In FIG. 4, the substrate 120 and the substrate 121 have their joint surfaces facing each other. Here, the substrate 121 is shown in FIG.
A cap 62 is formed in the same manner as in FIG.
When the caps 61 and 62 are connected, both pattern positions can be accurately obtained as relative positions of the groove 100 and the groove 110 formed on the back surface. Therefore, both layers can be brought into contact with each other without directly observing the cap 61 and the cap 62.

In FIG. 5, the connection layer 63 is selectively formed between the contacted layers.

8 to 30 show the first embodiment of the present invention. Example 1 shows a process of forming an element in which a MOS transistor and a bipolar transistor are combined.

First, a groove 100 to be a reference pattern is formed on the back surface of a P-type silicon single crystal substrate (FIG. 8). Next,
Chemical vapor deposition (Chemical Vapor Depo)
A silicon nitride film having a thickness of 100 nm is deposited on the surface of the substrate by the following method. Then, the reference pattern 100 is used for alignment to pattern the active region. Then, the element isolation region 91 is formed by the thermal oxidation film having a thickness of 500 nm by the known selective oxidation method.
0 is formed (FIG. 9). FIG. 9 shows that after the oxide film 910 is formed,
The figure shows the silicon nitride layer removed by wet etching.

A thermal oxide film of 10 nm is formed on the substrate.
Then, polycrystalline silicon doped with phosphorus at a high concentration and made conductive is deposited to a thickness of 200 nm by the CVD method. After that, alignment is performed using the reference pattern 100,
The gate 500 is patterned by the photoresist method. The gate 500 is formed by anisotropically etching the substrate using the pattern (FIG. 10).

The polycrystalline silicon layer on the back surface of the substrate deposited by the CVD method in the step shown in FIG. 10 is removed. Using the gate 500 as a mask, arsenic is ion-implanted into the substrate at 5 × 10 ¹⁵ cm ⁻³ and heat-treated to form the source / drain diffusion layer electrodes 300. BPSG by CVD method
Is deposited to a thickness of 500 nm and flattened by heat treatment (FIG. 1).
1).

After that, contact holes to the diffusion layer electrode and the gate electrode are opened in the BPSG (FIG. 12). Here, the patterning of the contact holes is also aligned using the reference pattern 100.

After depositing 100 nm of tungsten by the sputtering method, 300 nm of tungsten is deposited by the CVD method. The wiring layers 600, 601 and 602 are patterned and aligned by using the reference pattern 100 and processed by etching (FIG. 13).

On the substrate, a 500 nm flattened interlayer film is deposited by a CVD method using a silicon oxide film and an inorganic coating film (FIG. 14).

The second contact is opened in the specific wiring layer 602 by aligning it using the reference pattern 100 (FIG. 15).

Tungsten having a thickness of 500 nm is deposited by the sputtering method and aligned with the reference pattern 100 to form the wiring 800 (FIG. 16).

A second reference pattern 110 is formed on the back surface of the second substrate (FIG. 17).

The bipolar transistor forming process shown up to FIG. 29 can be performed in parallel with the MOS transistor forming process.

The silicon nitride film 980 is formed by the CVD method 2
00 nm is deposited. The buried layer is patterned by using the reference pattern 110 for alignment, and the silicon nitride film 980 is processed to expose the substrate surface. Then, antimony is diffused at a high concentration to form a buried layer 450 (FIG. 18).

The silicon nitride film layer 980 on the substrate surface is removed, and a single crystal silicon layer 520 is deposited on the substrate surface by the epitaxial growth method to a thickness of 1000 nm (FIG. 19).

The silicon nitride film 981 is formed into 2 by the CVD method.
After being deposited to a thickness of 00 nm, alignment is performed using the reference pattern 110 to pattern the active region (see FIG. 2).
0).

Using the silicon nitride film 981 as a mask, the single crystal silicon layer 520 on the substrate surface is formed with hydrazine to a thickness of 50.
Etching is performed to 0 nm (FIG. 21).

The silicon nitride film 981 is used as a mask to thermally oxidize the substrate to 1000 nm to form an element isolation region 920. Then, the silicon nitride film 981 was removed by wet etching (FIG. 22).

Boron is ion-implanted using the resist pattern aligned with the reference pattern 110 as a mask to form the base 420. Further, phosphorus is ion-implanted to form the extraction layer 455 from the embedding layer 450 (FIG. 23).

After forming a thermal oxide film having a thickness of 10 nm, an oxide film 931 having a thickness of 50 nm is deposited by the CVD method. After that, the emitter opening is patterned by using the reference pattern 110 for alignment, and the substrate surface is exposed by wet etching (FIG. 24).

Polycrystalline silicon doped with phosphorus at a high concentration is deposited to a thickness of 150 nm by the CVD method, and the emitter pattern 460 is aligned by using the reference pattern 110.
Forming and processing. By heat treatment, phosphorus is diffused from the substrate 460 to form the emitter 410 (FIG. 25).

After depositing BPSG of 500 nm by the CVD method, it is flattened by heat treatment and aligned with the reference pattern 110 to open contact holes in each electrode (FIG. 26).

Tungsten of 500 is formed by the sputtering method.
Then, the wiring layers 700, 701 and 702 are patterned by aligning with the reference pattern 110 and processed (FIG. 27).

A flattened 500 nm interlayer film is formed by a silicon oxide film and an inorganic coating film by the CVD method.
Then, the second contact is formed on the specific wiring 702 by aligning using the reference pattern 110 (FIG. 2).
8).

500 nm of tungsten is deposited by the sputtering method. Then, the wiring 801 is formed in alignment with the reference pattern 110 (FIG. 29).

The substrate shown in FIG. 16 and the substrate shown in FIG. 29 are overlapped with each other on the surface on which the semiconductor element is formed (FIG. 30).

According to this forming method, the wiring 800 of the substrate shown in FIG. 16 and the wiring 801 of the substrate shown in FIG.
Can know the relative positions of the reference patterns 100 and 110, respectively, so that they can be accurately overlapped.
Therefore, the wirings 800 and 801 can face each other at an interval of 1000 nm. Here, the connection layer 803 of the wirings 800 and 801 is further formed by selectively growing tungsten to a thickness of 500 nm by the CVD method.
A semiconductor device in which an S transistor and a bipolar transistor are integrated can be obtained.

In the first embodiment, since the substrate on which the MOS transistor is formed and the substrate on which the bipolar transistor is formed are separate substrates, the semiconductor is easier to form than the MOS transistor and the bipolar transistor are formed on the same substrate. Integrated circuits can be manufactured. By connecting both substrates as described above, it is possible to obtain a semiconductor integrated circuit device having the same performance as in the case where the MOS transistor and the bipolar transistor are formed on the same substrate. In addition, one of the substrates may be one in which only the wiring that functions as a jumper line is formed instead of the transistor.

In the first embodiment described above, the case where substrates of almost the same type are stacked is explained, but in the second embodiment, the case where substrates of different sizes are used as shown in FIG. 31 is shown. At this time, in the substrate on one side, the reference pattern 110 may be formed on the substrate surface. Also, the caps 61 and 62
It is possible to form the welded connection layer by using a low melting point metal for the caps 61 and 62, and then heat treating the caps.

Further, as a third embodiment, as shown in FIG. 32, the positions of the patterns formed on the two substrates can be aligned with the pattern of the connection layer 63.
That is, from the relative position of 100 and 110, the cap 6
The positions 1 and 62 can be arranged at positions that match the pattern 63 to be formed next.

[0046]

Since the semiconductor integrated circuit device of the present invention has the reference pattern on the back surface of the substrate, the semiconductor integrated circuits on the two substrate surfaces are bonded with extremely high accuracy by the optical alignment method. You can Therefore, a semiconductor integrated circuit device having a high degree of integration can be easily manufactured.

Further, by forming the alignment pattern on the back surface, it is possible to provide a manufacturing method for forming the semiconductor integrated circuit device on the substrate surface with high accuracy even if the substrate surface cannot be seen by the alignment optical system.

[Brief description of drawings]

FIG. 1 is a device plan view showing an outline of the present invention.

FIG. 2 is a sectional view of an element showing an outline of the present invention.

FIG. 3 is an element cross-sectional view showing an outline of the present invention.

FIG. 4 is an element cross-sectional view showing an outline of the present invention.

FIG. 5 is an element cross-sectional view showing an outline of the present invention.

FIG. 6 is a sectional view of an element showing a conventional method.

FIG. 7 is an element cross-sectional view showing a conventional method.

FIG. 8 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 9 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 10 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 11 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 12 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 13 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 14 is an element cross-sectional structure diagram showing an element forming process of Example 1 of the present invention.

FIG. 15 is an element cross-sectional structure diagram showing an element formation process of Example 1 of the present invention.

FIG. 16 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 17 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 18 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 19 is an element cross-sectional structure diagram showing an element formation process of Example 1 of the present invention.

FIG. 20 is an element cross-sectional structure diagram showing an element formation process of Example 1 of the present invention.

FIG. 21 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 22 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 23 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 24 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 25 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 26 is an element cross-sectional structure diagram showing an element formation process of Example 1 of the present invention.

FIG. 27 is an element cross-sectional structural diagram showing an element forming process of Example 1 of the present invention.

FIG. 28 is an element cross-sectional structure diagram showing the element formation process of Example 1 of the present invention.

FIG. 29 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 30 is an element cross-sectional structural view showing an element forming process of Example 1 of the present invention.

FIG. 31 is an element cross-sectional structural view showing the features of Embodiment 2 of the present invention.

FIG. 32 is a cross-sectional structural view of an element showing the features of Example 3 of the present invention.

[Explanation of symbols]

50: groove, 61, 62: cap layer, 63: inter-substrate connecting layer, 100, 110: reference pattern, 120, 121: substrate, 300: diffusion layer electrode, 420: base, 450: buried layer, 455: Extraction layer, 410, 460: Emitter, 500: Gate, 520: Silicon, 600, 601, 602, 700, 701, 702, 8
00, 801: Wiring layer, 803: Connection layer, 910, 920: Element isolation insulating film, 931: Silicon oxide film, 980, 981: Silicon nitride film.

Claims (6)

[Claims] 1. A semiconductor integrated circuit device having a substrate on the front surface of which a semiconductor integrated circuit is formed, and an alignment groove for determining the position of the semiconductor integrated circuit on the back surface of the substrate. . 2. A semiconductor integrated circuit device having a semiconductor integrated circuit formed on the front surface thereof and two substrates having on the back surface thereof alignment grooves for determining the position of the semiconductor integrated circuit. A semiconductor integrated circuit including only MOS transistors is formed on a substrate, and a semiconductor integrated circuit including only bipolar transistors is formed on the other substrate so that the MOS transistor and the bipolar transistor are electrically connected. 2 above
A semiconductor integrated circuit device characterized in that two substrates are bonded together. 3. A semiconductor integrated circuit device having a semiconductor integrated circuit formed on the front surface thereof and two substrates having on the back surface thereof alignment grooves for determining the position of the semiconductor integrated circuit. A semiconductor integrated circuit including only MOS transistors is formed on a substrate, and a semiconductor integrated circuit including only wiring is formed on the other substrate.
A semiconductor integrated circuit device characterized in that the two substrates are bonded so that the MOS transistor and the wiring are electrically connected. 4. A step of forming a reference pattern on the back surface of the substrate, and a step of forming a pattern of the semiconductor integrated circuit device on the front surface of the substrate after performing alignment using the reference pattern. And method for manufacturing a semiconductor integrated circuit device. 5. When connecting a semiconductor integrated circuit formed on the surface of a substrate having a groove on its back surface to a semiconductor integrated circuit formed on the surface of another substrate, alignment is performed using the groove. A method of manufacturing a semiconductor integrated circuit device having a feature. 6. A semiconductor integrated circuit manufacturing apparatus for forming a semiconductor integrated circuit on a front surface of a substrate, wherein the substrate is aligned using a groove formed on the back surface of the substrate. apparatus.