JPH0675809A - Test circuit of microcomputer - Google Patents

Abstract

PURPOSE:To shorten the test time by leading out test data to an external terminal through a second buffer circuit whose size is larger than size of a first buffer circuit, in the case of evaluating the test. CONSTITUTION:Gate channel width of a CMOS inverter in the inside of a buffer 6 is set so as to become larger than gate channel width of a CMOS inverter in the inside of a buffer 5. In such a state, an output allowing signal ALW and a test signal TEST are applied through an inverter 8, and an AND gate 7 executes operation control of the buffer 5 by an AND output of these two inputs. Also, the output allowing signal ALW and the test signal TEST are applied, and an AND gate 9 executes operation control of the buffer 6 by an AND output of these two inputs. In this case, since the ALW and the TEST both become '1', the buffer 6 is operated by the AND output of '1' of the AND gate 9, and output data DOUT which rises and falls steeply is lead out to an external terminal 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer test circuit.

[0002]

2. Description of the Related Art Usually, when an element constituting a microcomputer is printed on a wafer by a mask in a manufacturing process, thereafter, the microcomputer is tested in the state of the wafer. That is, the correctness / wrongness of data arithmetically processed in the microcomputer is determined. In this case, the input / output port of the microcomputer and the external terminal of the tester are connected, the data prepared in advance by the tester is taken into the microcomputer through the input / output port, and the data processed in the microcomputer is input / output. The data is taken into the tester again through the port, and the correctness of the operation data is judged inside the tester.

Here, the input / output port of the microcomputer is generally used in common whether it is used for test evaluation of operation data or used as a mass-produced product. Therefore, when using the microcomputer by connecting it to an external device other than the test, in order to prevent the external device from malfunctioning due to the influence of harmonic components contained in the calculation data output from the microcomputer, The size of the MOS transistor that constitutes the inverter has been set to some extent small. This prevents the output data of the microcomputer from abruptly changing, that is, suppresses the generation of harmonic components due to the abrupt change, and prevents the external device (for example, VTR) from malfunctioning.

[0004]

However, in the test evaluation of the operation data of the microcomputer,
If the size of the MOS transistor forming the inverter inside the input / output port is small, the rising and falling of the output data will be delayed for a predetermined time. Therefore, when the test evaluation of a plurality of microcomputers is repeated,
As a result, there was a problem that it took a lot of test time.

Therefore, it is an object of the present invention to provide a test circuit for a microcomputer, which can shorten the test time when performing test evaluation of the operation data of the microcomputer.

[0006]

The present invention has been made to solve the above-mentioned problems. First, in a microcomputer that is connected to an external terminal of an external device and can output at least data. A first buffer circuit which takes in predetermined data and outputs it to the external terminal, and a second buffer circuit which takes in the predetermined data and outputs it to the external terminal and which is larger in size than the first buffer circuit
Buffer circuit, and an operation control circuit for inhibiting the operation of the first buffer circuit and permitting the operation of the second buffer circuit based on a test signal for setting the microcomputer in a test state. The test data processed in the microcomputer is derived from the external terminal via the second buffer circuit.

Next, in a microcomputer which is connected to an external terminal of an external device and can output at least data, a first buffer circuit which takes in predetermined data and outputs it to the external terminal, and the predetermined data is taken in. And the operation of the first buffer circuit based on a second buffer circuit of the same size as the first buffer circuit, which is derived to the external terminal at At the same time, an operation control circuit for permitting the operation of the second buffer circuit, and deriving test data processed inside the microcomputer from the external terminal via the first and second buffer circuits. Is characterized by.

[0008]

According to the first aspect of the present invention, when performing test evaluation of the operation data of the microcomputer, the test data is sent to the external terminal via the second buffer circuit which is larger in size than the first buffer circuit. Can be derived. Further, according to the second aspect, the test data can be derived from the external terminal via the first and second buffer circuits having the same size. This makes it possible to reduce the test time.

[0009]

The details of the present invention will be described in detail with reference to the drawings. In FIG. 4, the microcomputer (1) has a built-in CPU (2) for performing arithmetic processing and an input / output port (3) for inputting / outputting predetermined data. The input / output port (3) is connected to an external terminal (4) of an external device (not shown) such as a tester or VTR. The external terminal (4) is a terminal of the tester in the manufacturing process in which the microcomputer (1) is masked on the wafer, and is used for consumer after the microcomputer (1) is mass-produced. Alternatively, it may be a terminal provided in an industrial electronic device or the like.

D _IN is connected from the input / output port (3) to the CPU
Input data, D _OUT , taken in (2) is CPU
The output data is subjected to a predetermined arithmetic processing in (2) and is led to the external terminal (4) via the input / output port (3).
Also, ALW has output data D _OUT as input / output port (3)
Is an output permission signal for permitting output from, and becomes “1” when instructing output permission. Further, TEST is a test signal for putting the microcomputer (1) into a test state, and becomes "1" when instructing the test state.

For example, when performing a test evaluation of the operation data of the CPU (2) of the microcomputer (1) in the state of the wafer, the input / output port (3) and the external terminal (4) of the tester are connected. By giving a test instruction from the tester to the microcomputer (1) in advance, C
Based on the test signal TEST of "1" obtained from PU (2), the input / output port (3) is set to a state in which test data can be input / output. In this state, when the input data D _IN prepared in advance by the tester is taken into the CPU (2) through the input / output port (3), the arithmetic processing instructed by the tester is performed inside the CPU (2). Then, the input / output port (3) becomes ready to output with the output permission signal ALW of "1", and the output data D _{OUT as the} calculation result is derived from the external terminal (4) via the input / output port (3). It will be. This output data D _OUT is judged as correct or incorrect inside the tester. This is an outline of data input / output of the microcomputer (1) at the time of test, and the details of the inside of the input / output port (3) will be described below.

FIG. 1 is a circuit diagram showing an embodiment of the input / output port (3). It should be noted that the same reference numerals are given to the same portions between FIG. 1 and FIG. In FIG. 1, (5) is a buffer (first buffer circuit) that takes in the output data D _OUT and leads it to the external terminal (4), and (6) also takes in the output data D _OUT and outputs it to the external terminal (4). It is a buffer (second buffer circuit) leading to 4). Here, the buffer (6) is adjusted so that the output change of the buffer (6) becomes steep.
Is set to be larger than the size of the buffer (5). That is, the gate channel width of the CMOS inverter inside the buffer (6) is set to the CMO inside the buffer (5).
It is made larger than the gate channel width of the S inverter. (7) is an AND gate, which is an output enable signal ALW
And the test signal TEST are applied through the inverter (8), and the operation of the buffer (5) is controlled by the logical product output of the two inputs. Similarly, (9) is an AND gate for outputting the output enable signal ALW and the test signal TEST.
Is applied, and the operation of the buffer (6) is controlled by the logical product output of the two inputs.

FIG. 2 shows a specific structure of the buffers (5) and (6). The NAND gate (10), the NOR gate (11), the inverter (12), and the CMOS-connected MOS transistors (13) ( 14). NAND gate (10) and NO of each buffer (5) (6)
The output data D _OUT is applied to one input of the R gate (11). In addition, the NAND configuring the buffer (5)
The logical product output of the AND gate (7) is applied to the other input of the gate (10) and the other input of the NOR gate (11) via the inverter (12). Further, the NOR gate (11) via the other input of the NAND gate (10) and the inverter (12) which form the buffer (6)
The AND output of the AND gate (9) is applied to the other input of the.

Therefore, when the output data D _OUT processed by the CPU (2) is tested and evaluated, the output permission signal A
Since the LW and the test signal TEST are both "1",
The buffer (6) operates by the logical product output of "1" of the AND gate (9), and the output data D _OUT having a sharp rise and fall is derived to the external terminal (4). As a result, the delay of rising and falling of the output data D _OUT is prevented, and the test evaluation can be performed in a short time. On the other hand, when the output data D _OUT processed by the mass-produced microcomputer (1) is derived to the external terminal (4), the output permission signal ALW becomes “1” and the test signal TEST becomes “0”. For that reason, A
The buffer (5) operates by the logical product output of "1" of the ND gate (7), and the output data D _OUT having a gentle rise and fall is derived to the external terminal (4). This prevents the generation of harmonic components due to changes in the output data D _OUT , and the external device can
It will operate normally based on _OUT .

FIG. 3 is a circuit diagram showing another embodiment of the present invention, and the same portions between FIG. 3 and FIG. 4 are designated by the same reference numerals. In FIG. 3, the buffers (15) and (16) have the same size, and take in the output data D _OUT and derive it at the external terminal (4). Reference numeral (17) is an AND gate to which the output enable signal ALW and the test signal TEST are applied, and the operation of the buffer (16) is controlled by the logical product output of the two inputs. Here, when the output data D _OUT is derived to the external terminal (4) in the test evaluation, the output enable signal ALW and the test signal TEST are both “1”, so that the buffers (15) and (16) operate together. , The output data D _OUT is combined via the buffers (15) and (16) and is output to the external terminal (4). That is, since the output currents of the buffers (15) and (16) merge, the rising and falling edges of the output data D _OUT become steep, delay at the time of level change is prevented, and test evaluation can be performed in a short time. . On the other hand, normally, when the output data D _OUT is derived to the external terminal (4), only the buffer (15) operates because the test signal TEST is “0”, and the harmonic components with a gentle rise and fall. The output data D _OUT that does not include is derived to the external terminal (4), and the external device can be operated normally.

As described above, the buffers (5) and (6) having different sizes are provided to switch the buffer between the test of the microcomputer (1) and the normal operation.
Or, the buffers (15) and (16) of the same size are provided,
When testing the microcomputer (1), the buffer (1
5) By using (16) at the same time, the test evaluation time of the output data during the test can be shortened, and the malfunction of the external device due to the harmonic component of the output data during the normal operation can be prevented.

[0017]

According to the first aspect of the present invention, when the test evaluation of the operation data of the microcomputer is performed, the test data is externally transmitted through the second buffer circuit which is larger in size than the first buffer circuit. Can be led to the terminal. Further, according to the second aspect, the test data can be derived from the external terminal via the first and second buffer circuits having the same size. Therefore, the test time can be shortened, and further, there can be obtained an advantage that the external device can be prevented from malfunctioning due to the harmonic component contained in the output data of the microcomputer during the normal operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of the buffer of FIGS. 1 and 3.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram for explaining an outline of the present invention.

[Explanation of symbols]

 (1) Microcomputer (3) Input / output port (4) External terminal (5) (6) (15) (16) Buffer (7) (9) (17) AND gate (8) Inverter

Claims (3)

[Claims] 1. A microcomputer connected to an external terminal of an external device and capable of outputting at least data, comprising: a first buffer circuit for fetching predetermined data and deriving it to the external terminal; and fetching the predetermined data. Leading to the external terminal,
Based on a second buffer circuit having a size larger than that of the first buffer circuit and a test signal for setting the microcomputer in a test state, the operation of the first buffer circuit is prohibited and the second buffer circuit is operated. An operation control circuit for permitting the operation of the buffer circuit, wherein the test data processed in the microcomputer is derived from the external terminal via the second buffer circuit. circuit. 2. The first and second buffer circuits each have a CMOS-connected inverter for outputting data, and a gate channel of a MOS transistor forming the inverter of the second buffer circuit. The width corresponds to the MO that constitutes the inverter of the first buffer circuit.
2. The test circuit for the microcomputer according to claim 1, wherein the gate channel width of the S transistor is larger than that of the S transistor. 3. A microcomputer connected to an external terminal of an external device and capable of outputting at least data, comprising: a first buffer circuit which takes in predetermined data and outputs it to the external terminal; Leading to the external terminal,
Based on a second buffer circuit of the same size as the first buffer circuit and a test signal for putting the microcomputer in a test state, the operation of the first buffer circuit and the operation of the second buffer circuit are performed simultaneously. An operation control circuit for permitting an operation, wherein test data processed in the microcomputer is derived from the external terminal via the first and second buffer circuits. circuit.