JPH06195305A - Bus floating preventing circuit - Google Patents

Abstract

PURPOSE:To obtain the bus floating preventing circuit which can set potential on a 3-state bus of the inside to potential of a desired level, in the case a reset signal is applied. CONSTITUTION:The circuit contains an inverter 40 and a NOR gate 42. An output signal of the inverter 40 is connected to one input terminal of the NOR gate 42, and an output terminal of the NOR gate 42 is connected to an input terminal of the inverter 40. Also, an output terminal of the inverter 40 is connected to a 3-state bus, as well. Moreover, to the other input terminal of the NOR gate 42, an 'H' significant reset signal RSTH is applied. Accordingly, when the reset signal RSTH is applied to the NOR gate, an output signal of the NOR gate 42 becomes forcibly an 'L' level, and as a result, potential on the 3-state bus becomes forcibly an 'H' level. Therefore, potential on the 3-state bus immediately after reset can always be set to an 'H' level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal line circuit system called a bus system. In particular, it relates to a floating prevention circuit of a 3-state buffer connected to a 3-state bus.

[0002]

2. Description of the Related Art Conventionally, in order to avoid wiring of signal lines in a complicated electronic circuit, wiring of signal lines by a so-called bus system is performed. In recent years, wiring of signal lines by this bus system has been performed even in LSIs and the like. The bus-based signal line wiring allows signals to be exchanged relatively smoothly between a large number of electronic circuits.

A 3-state bus using a 3-state buffer as a buffer connected to the bus is widely used because it is relatively easy to increase the number of circuits connected to the bus. A schematic diagram showing an example of such a 3-state bus is shown in FIG. In FIG. 4, the 3-state buffer 10 is shown.
An example in which a, 10b, and 10c are connected is shown. Two input buffers 12a and 12b are also connected to the 3-state bus of FIG. The three-state buffers 10a, 10b, 10c have data D1, D2,
D3 is output to the 3-state bus. At this time, since two or more signals cannot appear on the 3-state bus at the same time, the enable signals EN1, EN2, and EN3 are supplied to each 3-state buffer, and only one 3-state buffer is provided at a time. It is exclusively controlled to be driven. By controlling these enable signals accurately, theoretically, no two or more signals compete on the three-state bus. Note that the 3-state buffer 1
0 (a, b, c) is the enable signal EN (1, 2,
When the non-driving state is set in 3), the output terminals of the three-state buffers 10 (a, b, c) are in the high impedance state (High-Z). As described above, the “3 states” of the 3-state bus is derived from the fact that there is a “high impedance state” in addition to “H” and “L”. That is, each of the three-state buffers 10 (a, b, c) keeps its output terminal in the high impedance state when it is in the non-driving state. There is no.

As described above, in the 3-state bus, the electric state on the bus is a high impedance state unless any of the 3-state buffers 10 is driven. However, in such a state, the potential on the bus becomes unstable, which may cause unstable circuit operation. Therefore, conventionally, a latch circuit having a weak driving capability, a pull-up element, or the like is connected to the 3-state bus so that the potential on the bus does not become unstable even when neither of the 3-state buffers is driven. ing. That is, by attaching a latch circuit or pull-up element having a weak driving capability, the potential is fixed to "H" or "L" (by the latch circuit) or "H" (by the pull-up element). You can An example of such a latch circuit is shown in FIG. As shown in FIG. 5, the latch circuit 14 includes two inverters 14
It is a circuit in which a and 14b are connected in a loop shape, and one of the input (output) terminals is connected to the 3-state bus. By connecting such a latch circuit 14 to the 3-state bus, the potential on the 3-state bus becomes "H".
Or “L” can be set. Since the latch circuit 14 does not affect the signal output from the other 3-state buffer 10 connected to the 3-state bus, its driving capability is weakly suppressed.

Further, when such a 3-state bus is not applied, that is, when the 3-state buffer is not used, a multiplexer as shown in FIG. It is possible to configure an equivalent circuit. As shown in FIG. 6, one of the data signals D1, D2, D3, D4 is supplied to the input buffers 16a, 16b by the enable signals EN2, EN3, EN4. In this way, by connecting the multiplexers 18a, 18b, 18c in multiple stages, it is possible to select and output any one of the plurality of data signals. As described above, according to the circuit configuration using the multiplexer shown in FIG. 6, it is possible to prevent the competition between the respective signals without applying the bus system. However, unlike the bus system, many signal lines are used. It is no longer possible to avoid routing the wiring. Particularly, in the internal circuit of an LSI in recent years, the number of signal lines thereof is enormous, so that the method shown in FIG. 6 can only be locally adopted. Also,
In the method of connecting the multiplexers in multiple stages as shown in FIG. 6, there is a problem that the delay of the data signal becomes large as the number of connected stages of the multiplexer increases. Therefore, also from this point, the circuit system using the multiplexer can hardly be adopted.

[0006]

As described above, the bus system using the 3-state buffer is an indispensable circuit technology in the internal circuit of the present LSI and other circuits. However, when a reset signal is applied to the LSI when the power is turned on, all the 3-state buffers that output signals to the 3-state bus may be in a non-driving state, that is, the output terminals thereof may be in a high impedance state. . In such a case, the potential on the 3-state bus is not fixed and becomes unstable. Then, the input voltage of an input buffer or the like that receives a signal on the 3-state bus is not fixed, and in the case of CMOS, it may cause latch-up or the like, which may cause element destruction. As described above, in the past, the voltage on the 3-state bus may not be stable at a very short moment when the power is turned on. However, when the operation of the LSI starts and some data is input, any of the 3 The state buffer drives the 3-state bus, and the unstable state described above will be removed soon.

However, when testing the function of the LSI, the instability of the voltage on the 3-state bus when the power is turned on hinders the function test, and as shown in FIG. 7, for example. It is necessary to eliminate voltage instability on the 3-state bus by performing processing prior to testing.

FIG. 7 shows a flow chart of an operation for removing this voltage instability. As shown in FIG. 7, when power is turned on in step ST7-1, so-called power-on reset is first applied to this LSI in step ST7-2. This power-on reset is performed by externally applying a reset signal to the LSI for a predetermined period.

In the functional test of LSI, generally, I
The C tester is used, but this IC tester is the LSI
It also monitors the power supply current. Next step ST7-3
In, it is confirmed whether or not the circuit is stable, that is, whether or not the potential on the 3-state bus is stable as described above. The magnitude of the power supply current is used for this determination. That is, LS using CMOS
In I, the consumption current hardly flows if the input voltage of the input buffer or the like is set to either the “H” level or the “L” level. The potential on the 3-state bus is still unstable, and it is determined that the circuit is not stable.

If the result of this determination in step ST7-3 is that the circuit is stable, step ST, which will be described later,
If it is determined that the circuit is not stable, the process proceeds to step ST7-4. Step ST7-
In 4, the predetermined data is set in the LSI by applying the predetermined data to the LSI and also applying the clock signal. Then, after applying the data of a certain pattern a predetermined number of times, the above-described step S
The process proceeds to T7-3 again, and it is determined whether the circuit is stable.

In step ST7-5, the stationary current consumption Idds and the like are measured. This is done as part of functional testing.

As described above, in the conventional semiconductor integrated circuit device, the potential on the 3-state bus is not stable when the power is turned on, which may cause deterioration of the element or latch-up in the case of CMOS. was there.

The present invention has been made in view of the above problems, and an object thereof is to provide a reset signal when a reset signal is applied.
To obtain a bus floating prevention circuit capable of forcibly setting the state bus to a predetermined potential and preventing the 3-state bus from becoming in an unstable state, that is, a so-called floating state.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the first invention is to hold a voltage on a 3-state bus, and not all 3-state buffers drive the 3-state bus. Also, the held voltage is
A circuit for preventing a 3-state bus from entering a floating state, the circuit comprising a state-holding latch to be supplied to the state bus, wherein the state-holding latch holds a first or second voltage on the 3-state bus. A feedback loop, and a voltage setting means for forcibly setting the voltage of the signal in the feedback loop to one of the first voltage or the second voltage determined in advance by inputting a reset signal from the outside. And a first or second voltage forcedly set in the feedback loop is supplied to the three-state bus by externally inputting a reset signal to the voltage setting means. It is a floating prevention circuit.

In order to solve the above-mentioned problems, the second aspect of the present invention, when all the 3-state buffers connected to the 3-state bus are not driving the 3-state bus, a predetermined voltage is applied to the 3-state bus. A circuit for preventing a 3-state bus from being in a floating state, which is provided with a dummy driver for supplying a reset signal to the 3-state bus, or for connecting all 3-state buses to the 3-state bus. Floating determination means for generating a floating signal when the buffer does not drive the three-state bus; and a dummy three-state buffer for supplying the first or second voltage to the three-state bus when the floating signal is received. , And a reset signal from the outside can be input to the floating determination means. Accordingly, the dummy three-state driver is a bus floating prevention circuit and supplying a predetermined voltage of one of the first or second voltage to said three-state bus.

[0016]

The voltage setting means in the first aspect of the present invention forcibly sets the output of the state holding latch to a predetermined voltage by a reset signal from the outside. Therefore, when the reset signal is applied, the 3-state bus is always forcibly set to a predetermined voltage.

The floating judgment means in the second aspect of the present invention generates the floating signal not only when all the 3-state buffers connected to the 3-state bus are in the non-driving state but also when the reset signal is input. . Therefore, the dummy driver in the second invention is
Even when a reset signal is input, a predetermined voltage is forcibly set on the 3-state bus.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows a circuit diagram of an embodiment of a bus floating prevention circuit of the present invention. As shown in FIG. 1, the bus floating prevention circuit of the present embodiment forms a signal loop by connecting an output terminal of an inverter 40 and a NOR gate 42 to the input terminal of the other terminal. There is. The output terminal of the inverter 40 is also connected to the 3-state bus, which constitutes a state holding latch. A feature of this embodiment is that the NOR gate 42 is included in the signal loop forming the state holding latch, and the "H" significant reset signal RSTH is applied to one of its input terminals. NOR
The other input terminal of the gate 42 is the inverter 40 described above.
Output signal is applied.

As described above, in this embodiment, a part of the signal loop of the state holding latch is the NOR gate 42, and
A reset signal was applied to one input terminal of the NOR gate 42. Therefore, when the "H" significant reset signal is applied, the output signal of the NOR gate 42 is forcibly set to the "L" level and the potential on the 3-state bus connected to the output terminal of the inverter 40 is forced. The "H" level.

A 3-state buffer 50, an input buffer 52, etc. are connected to the 3-state bus.

As described above, according to this embodiment, the potential on the 3-state bus is forcibly set to the "H" level by the reset signal RSTH. Therefore, it is possible to eliminate the instability of the potential of the three-state bus immediately after the reset and set the predetermined potential (in this embodiment, for example, it is the “H” level). As a result, according to this embodiment, the potential on the 3-state bus immediately after reset is
A constant value can be expected, and it is not necessary to set the potential on the 3-state bus by inputting a data pattern even when performing a functional test.

Embodiment 2 FIG. 2 is a circuit diagram of Embodiment 2 of the bus floating prevention circuit of the present invention. The bus floating prevention circuit shown in FIG.
And a D-gate 62. And the inverter 6
The output terminal of 0 is connected to one input terminal of the NAND gate 62, and the output terminal of the NAND gate 62 is connected to the input terminal of the inverter 60. The output terminal of the inverter 60 is also connected to the 3-state bus.
The characteristic feature of this embodiment is that the "L" significant reset signal RSTL is applied to the input terminal of the NAND gate. By applying the reset signal RSTL to the NAND gate 62, the “L” level signal is forcibly supplied to the 3-state bus.

As described above, in this embodiment, the above first embodiment is used.
Is forcibly set to the "H" level when the "H" significant reset signal RSTH is applied, whereas the "L" significant reset signal RSTL is forcibly set to the "H" level.
Is applied, the potential on the 3-state bus is forcibly set to the “L” level. Therefore, when it is desired to set the potential on the 3-state bus immediately after reset to the "L" level, the second embodiment is suitable. Other functions and effects are exactly the same as those in the first embodiment. The bus floating prevention circuit in the second embodiment can be provided inside the same LSI circuit as in the first embodiment, and the potential of the signal immediately after the reset is set to the “H” level with respect to the separate 3-state bus. And the "L" level can be set to desired levels.

Embodiment 3 FIG. 3 is a circuit diagram of Embodiment 3 of the bus contention prevention circuit of the present invention. As shown in FIG. 3, the bus floating prevention circuit according to the third embodiment includes a dummy 3-state buffer 70 whose input terminal is connected to the power supply terminal VDD.
And a floating judgment circuit section for supplying a control signal to the dummy 3-state buffer 70. As shown in FIG. 3, the floating judgment circuit section includes a NOR gate 72 for inputting control signals EN1 and EN2 to another 3-state buffer 50, and a NOR gate 72.
It also includes an OR gate 74 to which the output signal of the gate 72 is input. The "H" significant reset signal RSTH is applied to the other input terminal of the OR gate 74. The output terminal of the dummy 3-state buffer 70 is connected to the 3-state bus. Further, the above-mentioned control signals EN1 and 2 are "L" significant signals, and each 3-state buffer 50 is in a drive state when the control signal EN (1,2) is a signal of "L" level, and "H". When it is a signal of the “” level, it is in a non-driving state.

What is characteristic of this embodiment is not only that each control signal EN (1, 2) is at the "L" level and none of the 3-state buffers 50 drives the 3-state bus. Even when the reset signal RSTH is applied to the OR gate 74, the dummy three-state buffer 70 is driven, and the power supply voltage, that is, the signal of "H" level is supplied to the three-state bus. In the third embodiment, when the reset signal RSTH is applied, each control signal EN (1, 2) of the 3-state buffer 50 is suppressed by the control circuit (not shown), and the 3-state buffer 50 is It becomes a non-driving state.

As described above, according to the third embodiment, the 3-state bus is forcibly set to "H" when the reset signal RSTH is applied, so that the instability of the potential on the 3-state bus is eliminated. It is possible to As a result, it is expected that the dummy 3-state buffer 70 will be used to achieve the same effects as those of the first embodiment.

In the third embodiment, it is possible to forcibly set the potential on the 3-state bus to the "H" level at the time of reset, but the input terminal of the dummy 3-state buffer 70 is set to the power supply terminal. By installing instead of connecting, it is possible to set the potential on the 3-state bus to the "L" level at the time of reset. In this case, the potential on the 3-state bus can be forcibly set to the “L” level when the reset signal is applied.

As described above, according to the first, second, and third embodiments, the potential on the 3-state bus can be set to a desired potential when the reset signal is applied. It is not necessary to input a data pattern after inputting and set a predetermined potential to each 3-state bus inside the semiconductor integrated circuit device. Furthermore, since the potential on the 3-state bus immediately after resetting is stable, it is possible to prevent the power consumption current from becoming excessive immediately after power-on. As a result, it is possible to effectively prevent element deterioration, latch-up, element destruction, and the like.

[0030]

As described above, according to the first aspect of the present invention, it is possible to apply a signal of a desired level to the 3-state bus by inputting the reset signal. Therefore,
It is possible to stabilize the potential on the 3-state bus immediately after reset, and suppress excessive power consumption current.
It is possible to obtain a bus floating circuit that can effectively prevent element breakdown and the like.

According to the second aspect of the present invention, the potential of a desired level is supplied to the 3-state bus not only when the 3-state buffer is in the non-driving state but also when the reset signal is input. be able to. Therefore, similar to the first aspect of the present invention, it is possible to obtain a bus floating prevention circuit that can effectively prevent element breakdown and the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bus floating prevention circuit that is a first preferred embodiment of the present invention.

FIG. 2 is a circuit diagram of a bus floating prevention circuit according to a second preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of a bus floating prevention circuit which is a preferred embodiment 3 of the present invention.

FIG. 4 is a circuit diagram showing a state in which a 3-state buffer is connected to a conventional 3-state bus.

FIG. 5 is a circuit diagram showing a latch circuit connected in order to stabilize the potential of a conventional 3-state bus.

FIG. 6 is a conventional circuit diagram configured by using a multiplexer when an equivalent function is to be realized without using a 3-state bus.

FIG. 7 is a flowchart showing an operation of stabilizing a potential on a 3-state bus by applying a predetermined data pattern immediately after power-on when performing a functional test in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 40 inverter 42 NOR gate 50 3-state buffer 52 input buffer

Claims (2)

[Claims] 1. A state-holding latch that holds a voltage on a 3-state bus and supplies the held voltage to the 3-state bus even when all the 3-state buffers do not drive the 3-state bus, A circuit for preventing the 3-state bus from entering a floating state, wherein the state-holding latch receives a feedback loop for holding the first or second voltage on the 3-state bus, and inputs a reset signal from the outside. A voltage setting means for forcibly setting the voltage of the signal in the feedback loop to one of the first voltage and the second voltage, which is predetermined, By inputting to the setting means, the first or second voltage forcedly set in the feedback loop is supplied to the three-state bus. Bus floating preventing circuit according to claim. 2. A dummy driver for supplying a predetermined voltage to the 3-state bus when all the 3-state buffers connected to the 3-state bus are not driving the 3-state bus, and the 3-state bus is floating. The dummy driver is a circuit that prevents a state from being brought into a floating state when a reset signal is input, or when all 3-state buffers connected to the 3-state bus do not drive the 3-state bus. A floating judging means for generating a signal; and a dummy three-state buffer for supplying the first or second voltage to the three-state bus when the floating signal is received. Input to the dummy 3-state dry A bus floating preventing circuit and supplying one of the voltage a predetermined one of the first or second voltage to said three-state bus.