JPH0673358B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0673358B2 JPH0673358B2 JP61212090A JP21209086A JPH0673358B2 JP H0673358 B2 JPH0673358 B2 JP H0673358B2 JP 61212090 A JP61212090 A JP 61212090A JP 21209086 A JP21209086 A JP 21209086A JP H0673358 B2 JPH0673358 B2 JP H0673358B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- mounting portion
- element mounting
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に、半導体素子と半導体
素子載置部との接合構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a joint structure between a semiconductor element and a semiconductor element mounting portion.
第７図，第９図は従来の半導体装置の半導体素子載置部
付近を示す平面図であり、第８図は第７図のVIII−VIII
線断面、第10図は第９図のＸ−Ｘ線断面図である。第７
図〜第10図において、１は半導体素子、２は半導体素子
載置部、３は半導体素子１と半導体素子載置部２とを接
合する接合材、４は配線材、５は外部端子である。7 and 9 are plan views showing the vicinity of a semiconductor element mounting portion of a conventional semiconductor device, and FIG. 8 is VIII-VIII of FIG.
FIG. 10 is a sectional view taken along line XX in FIG. 7th
In FIG. 10 to FIG. 10, 1 is a semiconductor element, 2 is a semiconductor element mounting portion, 3 is a bonding material for joining the semiconductor element 1 and the semiconductor element mounting portion 2, 4 is a wiring material, and 5 is an external terminal. .
従来の半導体装置は以上のように構成されているので、
半導体素子１が大型化して熱放散性改善のために銅系の
半導体素子載置部を用いた場合、半導体素子と熱膨張係
数が大きく異なるため、第８図に示すように半導体素子
１の全面を接合材３で接合すると、接合後、温度変化に
伴い熱応力が発生し、半導体素子１に割れが生じるとい
う問題があった。Since the conventional semiconductor device is configured as described above,
When the semiconductor element 1 is upsized and a copper-based semiconductor element mounting portion is used to improve heat dissipation, the coefficient of thermal expansion is greatly different from that of the semiconductor element. However, there is a problem in that, when the materials are bonded with the bonding material 3, thermal stress is generated with the temperature change after the bonding, and the semiconductor element 1 is cracked.
この割れを防止するため、第９図および第10図に示すよ
うに半導体素子１を部分的に接合すると、応力は緩和さ
れるものの接合の面積が一定しないという問題に加え、
半導体素子１が半導体素子載置部２から浮いている部分
があり半導体素子１が傾いたりするため、配線材４の半
導体素子１への接合が安定してできないというような問
題があった。In order to prevent this crack, if the semiconductor element 1 is partially bonded as shown in FIGS. 9 and 10, in addition to the problem that the stress is relieved but the bonding area is not constant,
There is a problem that the semiconductor element 1 is inclined from the semiconductor element mounting portion 2 and the semiconductor element 1 is inclined, so that the wiring member 4 cannot be stably bonded to the semiconductor element 1.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、接合面積を一定にし、半導体素
子にかかる応力を緩和し、半導体素子が半導体素子載置
部に対して傾いたり浮いたりしない半導体装置を得るこ
とにある。The present invention has been made in view of such a point, and an object thereof is to make a bonding area constant, relieve stress applied to a semiconductor element, and the semiconductor element tilts with respect to a semiconductor element mounting portion. It is to obtain a semiconductor device that does not float or float.
このような目的を達成するために本発明は、半導体素子
と半導体素子載置部とを有する半導体装置において、前
記半導体素子載置部は、二つの向き合ったコ字状の貫通
穴により形成されるとともにくぼみ部を有しかつ接する
半導体素子の表面積より小さい表面積を有する接合部
と、この接合部と前記半導体素子載置部本体とを連結す
る連結部とを有し、前記接合部にのせた接合材により前
記半導体素子と前記半導体素子載置部とを接合したもの
である。In order to achieve such an object, the present invention provides a semiconductor device having a semiconductor element and a semiconductor element mounting portion, wherein the semiconductor element mounting portion is formed by two facing U-shaped through holes. And a joint portion having a recessed portion and having a surface area smaller than the surface area of the contacting semiconductor element, and a joint portion connecting the joint portion and the semiconductor element mounting portion main body, and the joint placed on the joint portion The semiconductor element and the semiconductor element mounting portion are joined by a material.
本発明においては、半導体素子が半導体素子載置部に対
して傾いたり浮いたりすることはない。In the present invention, the semiconductor element does not tilt or float with respect to the semiconductor element mounting portion.
本発明に係わる半導体装置の一実施例を第１図に示す。
第２図は第１図のII−II線断面図、第３図は第１図のII
I−III線断面図である。第１図〜第３図において、６は
コ字状の貫通穴８により形成され接する半導体素子１の
表面積より小さい表面積を有する接合部、７は接合部６
と半導体素子載置部２本体と連結する連結部である。第
１図〜第３図において第８図および第９図と同一部分又
は相当部分には同一符号が付してある。接合部６は、二
つの向き合うコ字状の貫通穴により形成され、かつ、半
導体素子１を接合する側では、半導体素子載置部２の面
に対しくぼみ部を有しており、接合部の表面積は４×４
mm2以下で半導体素子の表面積より小さい。An embodiment of the semiconductor device according to the present invention is shown in FIG.
2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is II in FIG.
It is a sectional view taken along the line I-III. In FIGS. 1 to 3, 6 is a joint portion formed by a U-shaped through hole 8 and having a surface area smaller than the surface area of the semiconductor element 1 in contact, and 7 is a joint portion 6.
And a connecting portion for connecting to the main body of the semiconductor element mounting portion 2. 1 to 3, the same or corresponding parts as those in FIGS. 8 and 9 are designated by the same reference numerals. The joint portion 6 is formed by two U-shaped through holes facing each other, and has a recess on the surface of the semiconductor element mounting portion 2 on the side where the semiconductor element 1 is joined. Surface area is 4 × 4
It is smaller than the surface area of the semiconductor device at mm 2 or less.
第１図〜第３図に示す実施例においては、半導体素子１
と接合部６の接合面積が４×４mm2以下で半導体素子１
の表面積より小さい面積であるため、熱膨張係数の違い
により生じる応力を緩和できる。In the embodiment shown in FIGS. 1 to 3, the semiconductor device 1
The semiconductor element 1 has a junction area of 4 × 4 mm 2 or less between
Since the area is smaller than the surface area of, the stress caused by the difference in thermal expansion coefficient can be relaxed.
また、接合部６は連結部７により半導体素子載置部２と
介されているため、接合面積を一定にすることができ
る。Further, since the joining portion 6 is connected to the semiconductor element mounting portion 2 by the connecting portion 7, the joining area can be made constant.
さらに、接合部６は半導体素子載置部７に対してくぼみ
状になっており、接合部６にのせた接合材３で半導体素
子１を接合しているため、半導体素子１が半導体素子載
置部２に対して傾いたり浮いたりすることがない。Further, since the bonding portion 6 has a recessed shape with respect to the semiconductor element mounting portion 7 and the semiconductor element 1 is bonded by the bonding material 3 placed on the bonding portion 6, the semiconductor element 1 is mounted on the semiconductor element mounting portion 7. It does not tilt or float with respect to the part 2.
第４図は本発明の第２の実施例を示す平面図であり、第
５図は第４図のＶ−Ｖ線断面図、第６図は第４図のVI−
VI線断面図である。第４図〜第６図において第１図〜第
３図と同一部分又は相当部分には同一符号が付してあ
る。第１の実施例では接合部６が１つであったが、第２
の実施例は接合部６の個数を複数にしたものである。こ
の第２の実施例も、第１の実施例と同様の効果を奏する
ものである。FIG. 4 is a plan view showing a second embodiment of the present invention, FIG. 5 is a sectional view taken along line VV of FIG. 4, and FIG. 6 is VI- of FIG.
FIG. 6 is a sectional view taken along line VI. In FIGS. 4 to 6, the same or corresponding parts as those in FIGS. 1 to 3 are designated by the same reference numerals. In the first embodiment, the number of joints 6 was one, but in the second
In this embodiment, the number of joints 6 is plural. The second embodiment also has the same effect as the first embodiment.
以上説明したように本発明は、半導体素子載置部内に半
導体素子より小さい面積で半導体素子載置部に対して二
つの向き合うコ字状の貫通穴により形成され、かつ、く
ぼみ状の接合部を連結部を介して設け、この接合部にの
せた接合材で半導体素子と半導体素子載置部とを接合し
たことにより、接合部が連結部により半導体素子載置部
と介されたため接合面積を一定にでき、また、半導体素
子と接合部の接合面積を半導体素子の表面積より小さく
できるので、熱膨張係数の違いにより半導体素子に生じ
る応力を緩和でき、さらに、半導体素子を半導体素子載
置部本体でも支えるようにしたので、半導体素子が半導
体素子載置部に対して傾いたり浮いたりしないという効
果がある。INDUSTRIAL APPLICABILITY As described above, the present invention is formed in the semiconductor element mounting portion by two facing U-shaped through holes with respect to the semiconductor element mounting portion in an area smaller than the semiconductor element, and a recessed joint portion. By providing the semiconductor element and the semiconductor element mounting portion with the bonding material placed on the joint portion through the joint portion, the joint area is constant because the joint portion is interposed by the joint portion with the semiconductor element mounting portion. In addition, since the bonding area between the semiconductor element and the bonding portion can be made smaller than the surface area of the semiconductor element, the stress generated in the semiconductor element due to the difference in the thermal expansion coefficient can be relaxed. Since the semiconductor element is supported, there is an effect that the semiconductor element does not tilt or float with respect to the semiconductor element mounting portion.
第１図は本発明に係わる半導体装置の一実施例を示す平
面図、第２図は第１図のII−II線断面図、第３図は第１
図のIII−III線断面図、第４図は本発明の第２の実施例
を示す平面図、第５図は第４図のＶ−Ｖ線断面図、第６
図は第４図のVI−VI線断面図、第７図および第８図は従
来の半導体装置を示す平面図および断面図、第９図およ
び第10図はさらに別の従来の半導体装置を示す平面図お
よび断面図である。 １…半導体素子、２…半導体素子載置部、３…接合材、
４…配線材、５…外部端子、６…接合部、７…連結部、
８…貫通穴。FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional view taken along line II-II of FIG. 1, and FIG.
III-III sectional view of the drawing, FIG. 4 is a plan view showing a second embodiment of the present invention, FIG. 5 is a sectional view taken along the line VV of FIG. 4, and FIG.
FIG. 6 is a sectional view taken along line VI-VI in FIG. 4, FIGS. 7 and 8 are plan views and sectional views showing a conventional semiconductor device, and FIGS. 9 and 10 show yet another conventional semiconductor device. It is a top view and a sectional view. DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Semiconductor element mounting part, 3 ... Bonding material,
4 ... Wiring material, 5 ... External terminal, 6 ... Joining portion, 7 ... Connecting portion,
8 ... Through hole.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−171733（ＪＰ，Ａ) 特開 昭57−97659（ＪＰ，Ａ) 特開 昭53−14563（ＪＰ，Ａ) 特開 昭57−66655（ＪＰ，Ａ) 実開 昭58−27934（ＪＰ，Ｕ) ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-60-171733 (JP, A) JP-A-57-97659 (JP, A) JP-A-53-14563 (JP, A) JP-A-57- 66655 (JP, A) Actual development Sho 58-27934 (JP, U)
Claims (2)
半導体装置において、前記半導体素子載置部は、二つの
向き合ったコ字状の貫通穴により形成されるとともにく
ぼみ部を有しかつ接する半導体素子の表面積より小さい
表面積を有する接合部と、この接合部と前記半導体素子
載置部本体とを連結する連結部とを有し、前記接合部に
のせた接合材により前記半導体素子と前記半導体素子載
置部とを接合したことを特徴とする半導体装置。1. A semiconductor device having a semiconductor element and a semiconductor element mounting portion, wherein the semiconductor element mounting portion is formed by two facing U-shaped through holes and has a recessed portion and is in contact therewith. The semiconductor element and the semiconductor have a joint portion having a surface area smaller than the surface area of the semiconductor element, and a joint portion that couples the joint portion and the semiconductor element mounting portion main body, with the joint material placed on the joint portion. A semiconductor device characterized by being joined to an element mounting portion.
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the joint portion has a surface area of 4 × 4 mm 2 or less.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61212090A JPH0673358B2 (en) | 1986-09-08 | 1986-09-08 | Semiconductor device |
| US07/093,524 US4857989A (en) | 1986-09-04 | 1987-09-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61212090A JPH0673358B2 (en) | 1986-09-08 | 1986-09-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6366941A JPS6366941A (en) | 1988-03-25 |
| JPH0673358B2 true JPH0673358B2 (en) | 1994-09-14 |
Family
ID=16616707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61212090A Expired - Lifetime JPH0673358B2 (en) | 1986-09-04 | 1986-09-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0673358B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3892139B2 (en) * | 1998-03-27 | 2007-03-14 | 株式会社ルネサステクノロジ | Semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314563A (en) * | 1976-07-26 | 1978-02-09 | Hitachi Ltd | Fixing method of semiconductor pellet to lead frame |
| JPS5766655A (en) * | 1980-10-09 | 1982-04-22 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
| JPS5797659A (en) * | 1980-12-10 | 1982-06-17 | Matsushita Electronics Corp | Lead frame |
| JPS5827934U (en) * | 1981-08-13 | 1983-02-23 | 日本電気株式会社 | semiconductor equipment |
| JPS60171733A (en) * | 1984-02-17 | 1985-09-05 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
-
1986
- 1986-09-08 JP JP61212090A patent/JPH0673358B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6366941A (en) | 1988-03-25 |
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| JPS60242652A (en) | Semiconductor device |