JPS61104630A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61104630A JPS61104630A JP22610884A JP22610884A JPS61104630A JP S61104630 A JPS61104630 A JP S61104630A JP 22610884 A JP22610884 A JP 22610884A JP 22610884 A JP22610884 A JP 22610884A JP S61104630 A JPS61104630 A JP S61104630A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor chip
- bonded
- deformation
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体チップをバンプによシパッケージ内
に装着した半導体装置に関し、特にバンプの半導体チッ
プへの接合の改良にかかわる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor chip is mounted in a package using bumps, and particularly relates to an improvement in bonding the bumps to the semiconductor chip.
従来、この種の半導体装置として、第７図に断面図で示
すものがあった。（１）は能動素子を有する半導体チッ
プで、シリコン材などからなり、表面にバンプ（６）が
設けられている。（７）はアルミナなどを主成分にした
セラミックからなるパッケージ、（８）はこのパッケー
ジ（７）内部に埋込まれた内部配線で、半導体チップ（
１）の機能を複合するように結線してあシ、上端部はパ
ッケージ（７）の底面上に露出している。（９）は内部
配線（８）の下部に接続され、パッケージ（７）の下方
に出された外部リード、（１０はパッケージ（７）に取
付けられたふたで、半導体チップ（１）部を外部環境か
ら保護する。Conventionally, as this type of semiconductor device, there has been one shown in a cross-sectional view in FIG. (1) is a semiconductor chip having active elements, made of silicon material, etc., and has bumps (6) provided on its surface. (7) is a package made of ceramic whose main component is alumina, etc., and (8) is the internal wiring embedded inside this package (7), and the semiconductor chip (
The wires are connected to combine the functions of 1), and the upper end is exposed on the bottom surface of the package (7). (9) is an external lead connected to the lower part of the internal wiring (8) and extended below the package (7), (10 is a lid attached to the package (7), and the semiconductor chip (1) part is Protect from the environment.
上記半導体チップ（１）のバンプ（６）部を、第８図に
拡大断面図及び第９図に第８図のＩＸ −ＩＸ線におけ
る断面図で示す。半導体チップ（１）の表面には、能動
素子を相互接続しその機能を取出すだめのアルミ材など
からなる配線（２）と、半導体チップ（１）の表面保護
のシリコン窒化瞭などからなる絶縁嘆（３）とが形成さ
れている。絶縁ｌ１１！ （３）にはバンプ（６）に対
応する部分に開孔部（３ａ）をあけ配線（２）の一部を
露出させている。開孔ｇ（（（３ａ）にはクローム材か
らなる接合金属部（４）かた−積付着され、この表面に
は銅材からなる厚嘆の接合−金属部（５）がたい積付着
されている。これら接合金属部（４） 、 （５＞のた
い積は、スパッタ法や蒸着法などによる。この接合金属
部（５）に鉛−すずなど軟ろう材からなるバンプ（６）
が接合されている。接合金属部（４）は無機物、有機物
に強い接合力をもつクローム材からなり、配線（２）と
接合金属部（５）とに結合し固着と電気的接続をしてい
る。接合金属部（５）の材料には、金属以外の物質には
接合力がほとんどなく導電率が大きい鋼材を用い、バン
プ（６）への冶金的なじみをよくしている。The bump (6) portion of the semiconductor chip (1) is shown in FIG. 8 as an enlarged sectional view and FIG. 9 as a sectional view taken along the line IX--IX in FIG. 8. On the surface of the semiconductor chip (1), wiring (2) made of aluminum or the like is used to interconnect active elements and take out their functions, and insulation layers made of silicon nitride or the like are used to protect the surface of the semiconductor chip (1). (3) is formed. Insulation l11! In (3), an opening (3a) is formed in a portion corresponding to the bump (6) to expose a part of the wiring (2). A bonding metal part (4) made of chrome material is deposited on the opening g ((3a), and a thick bonding metal part (5) made of copper material is deposited on its surface. These joining metal parts (4) and (5> are deposited by sputtering, vapor deposition, etc.) Bumps (6) made of a soft filler material such as lead-tin are added to this joining metal part (5).
are joined. The joining metal part (4) is made of a chromium material that has a strong bonding force to inorganic and organic substances, and is bonded to the wiring (2) and the joining metal part (5) for fixation and electrical connection. As the material of the joining metal part (5), a steel material having almost no joining force with substances other than metals and having high electrical conductivity is used to improve metallurgical conformity to the bump (6).
バンプ（６）の鉛−すずはんだは、金、ニラケール。The lead-tin solder of the bump (6) is gold and Nirakale.
銅などへの冶金的なじみ性が優れている。Excellent metallurgical compatibility with copper etc.
上記パッケージ（７）の内部配線（８）の露出した上端
部面は、ニッケル、金などの被嘆を蒸着やめっきなどで
付着しており、バンプ（６）の鉛−すず材などと冶金的
に接合している。The exposed upper end surface of the internal wiring (8) of the package (7) is coated with nickel, gold, etc. by vapor deposition or plating, and is metallurgically similar to the lead-tin material of the bump (6). It is joined to.
一般に半導体装置は実装使用において、温度サイクルを
受ける。これは、使用環境の温度が変化したり、装置の
動作、休止による余熱、冷却の繰返しなどによって起こ
る。ところが、半導体チップ（１）とパッケージ（７）
とは熱膨張係数が異なるので、このような温度変化に伴
す熱ひずみが生じる。両者はバンプ（６）で接合してい
るが、バンプ（６）の方が軟質であり剛性が低いので、
このバンプ（６）の変形によってひずみが解放され、バ
ンプ（６）部にせん断し力が生じる。この応力は熱ひず
み量と変形する部分の長さくチップ（１）とパッケージ
（７）の間隔であるが実質上バンプ（６）の高さに等し
い）によって決する。熱ひずみ量は温度差が決まれば一
定であるので、バンプ（６）高さを大きくすればバンプ
（６）のせん断ひずみは小さくなる。したがって、接合
部の寿命を長くするには、バンプ（６）の高さを犬きく
する手段が採用される。この手段にはバンプ（６）の体
積を増せばよい。Semiconductor devices are generally subjected to temperature cycles during packaging and use. This occurs due to changes in the temperature of the usage environment, residual heat due to device operation or rest, repeated cooling, etc. However, the semiconductor chip (1) and package (7)
Since the coefficient of thermal expansion is different from that of the material, thermal strain occurs due to such temperature changes. Both are joined by a bump (6), but since the bump (6) is softer and has lower rigidity,
This deformation of the bump (6) releases the strain and generates a shearing force in the bump (6). This stress is determined by the amount of thermal strain, the length of the deformed portion, and the distance between the chip (1) and the package (7), which is substantially equal to the height of the bump (6). Since the amount of thermal strain is constant as long as the temperature difference is determined, increasing the height of the bump (6) will reduce the shear strain of the bump (6). Therefore, in order to extend the life of the joint, measures are taken to increase the height of the bump (6). This can be achieved by increasing the volume of the bump (6).
上記のような従来の半導体装置では、バンプ（６）の体
積を増していけば高さが増えるが、あまり高くはできず
限度がある。また、隣接するバンプ（６）闇のピッチが
小さい場合は、バンプ（６）の体積を増して込〈と接触
するおそれがある。これを防ぐには、バンプ（６）の配
置間隔を広げなければならず、半導体チップ（１）に配
置するバンプ（６）数、すなわち、電気的機能の敗出し
端子数を減らさなければならなかった。このように、従
来の半導体装置は、バンプ（６）による接合部の寿命を
長くするためには、半導体チップ（１）に収納する電気
的機能の規模を制限しなければならないという問題点が
あった。In the conventional semiconductor device as described above, the height can be increased by increasing the volume of the bump (6), but there is a limit to how high it can be. Furthermore, if the pitch of the adjacent bumps (6) is small, there is a risk that the volume of the bumps (6) will increase and come into contact with the bumps (6). To prevent this, the spacing between the bumps (6) must be increased, and the number of bumps (6) placed on the semiconductor chip (1), that is, the number of terminals for electrical functions, must be reduced. Ta. As described above, conventional semiconductor devices have a problem in that in order to extend the life of the joints formed by the bumps (6), it is necessary to limit the scale of the electrical functions housed in the semiconductor chip (1). Ta.
この発明は、このような問題点を解決するためになされ
たもので、バンプを大きくすることなく接合が長寿命に
維持され、電気的機能の取出しが機能の規模の減少を要
しない半導体装置を得ることを目的としている。This invention was made to solve these problems, and it is possible to create a semiconductor device in which the bonding can be maintained for a long time without increasing the size of the bumps, and in which the extraction of electrical functions does not require a reduction in the scale of the functions. The purpose is to obtain.
この発明にかかる半導体装置は、半導体チップの表面の
配線の表面側の絶縁嘆の開口部を埋めた接合金属部で上
記配線に接合し、この接合金属部会シ、コノバンブをパ
ッケージの内部配線上端部に接合したものである。The semiconductor device according to the present invention is bonded to the wiring by a bonding metal part that fills the opening of the insulation on the front side of the wiring on the surface of the semiconductor chip, and the bonding metal part and the convex are connected to the upper end of the internal wiring of the package. It is joined to.
この発明においては、半導体チップとパッケージとの温
度変化により生じた熱ひずみによって、バンプと接合金
属体とに応力が生じるが、バンプの高さと接合金属体の
延長さｒＬだ中間部長さとによる変形により応力が減少
され、接合部の寿命が長くなる。In this invention, stress is generated in the bumps and the bonded metal body due to thermal strain caused by temperature changes between the semiconductor chip and the package, but due to deformation due to the height of the bump, the length rL, and the intermediate length of the bonded metal body. Stresses are reduced and joint life is increased.
第１図はこの発明による半導体装置の一実施例を示すバ
ンブ部の拡大断面図であり、（１）〜（４） 、 （６
）〜（８） 、 （３ａ）は上記従来装置と同一のもの
である。FIG. 1 is an enlarged sectional view of a bump portion showing an embodiment of a semiconductor device according to the present invention, and shows (1) to (4), (6)
) to (8) and (3a) are the same as the above conventional device.
０１）は鋼材からなり接合金属部（４）に一端が接合さ
れ、延長された他端側か絶縁嘆（４）外面に接する接合
金属体である。この接合金属体（ＩＩ）Ｋ冶金的に接合
されたバンプ（６）は、パッケージ（７）の内部配線（
８）の上端部のニッケル、金などの被−が施された表面
に冶金的に接合し、十分な接合強度になっている。Reference numeral 01) is a joint metal body made of steel, one end of which is joined to the joint metal part (4), and the other extended end in contact with the outer surface of the insulation joint (4). The metallurgically bonded bumps (6) of the bonded metal body (II) K are connected to the internal wiring (
8) It is metallurgically bonded to the surface coated with nickel, gold, etc. at the upper end, and has sufficient bonding strength.
このバンプ（６）部を第２図に第１図のＩＴ −ＩＩ線
における断面図で示すっ
上記接合金属体０１）は鋼材を用いており、接合金属部
（４）と１−１′接合力が大きく、また、バンプ（６）
とは軟ろう材との接合であり、冶金的なじみがよく十分
な接合となっている。さらに、鋼材からなる接合金属体
（１１）は絶縁Ｉｔ＠ （３）に接してはいるが、接着
力はなく伸縮は拘束されない。This bump (6) portion is shown in FIG. 2 as a sectional view taken along the IT-II line in FIG. The force is large and the bump (6)
This is a bond with a soft filler metal, and the bond is metallurgically compatible and sufficient. Further, although the bonded metal body (11) made of steel is in contact with the insulation It@ (3), it has no adhesive force and its expansion and contraction are not restricted.
なお、接合金属体０１）の材料は、接合金属部（４）及
びバンプ（６）と冶金的になじんで接合され、絶縁摸（
３）にＩｄ接着が弱く、導電性のよい金属であれば、鋼
材の外の材料を用いてもよい。Note that the material of the bonded metal body 01) is metallurgically compatible with the bonded metal part (4) and the bump (6), and is bonded to the insulating model (
For 3), materials other than steel may be used as long as the metal has weak Id adhesion and good conductivity.
上記一実施例の半導体装置において、温度変化が生じる
と、半導体チップ（１）とパッケージ（７）との間に熱
ひずみが生じる。しかし、双方とも剛性が大きく、双方
間の接合部分に変形が生じ、ひずみが解放され、接合部
分ＶＣ応力が生じる。この応力の大きさは、熱ひずみ量
と変形が起こる部分の長さによって決まる。ところが、
接合金属体０］）の延長部は伸縮可能であり、この部分
が変形する。しだがって、変形が起こる部分の長さは、
パンダ（６）の高さと接合金属体０］）の伸縮自在な中
間部長さとの和となる。この長さは従来のもののバンプ
（６）の高さだけよりは十分大きくなっておシ、変形部
分に生じる応力は小さくなり、これによシ、接合部の寿
命が延長する。In the semiconductor device of the above embodiment, when a temperature change occurs, thermal strain occurs between the semiconductor chip (1) and the package (7). However, since both have high rigidity, deformation occurs at the joint between the two, the strain is released, and VC stress is generated at the joint. The magnitude of this stress is determined by the amount of thermal strain and the length of the portion where deformation occurs. However,
The extension part of the bonded metal body 0]) is expandable and contractible, and this part is deformed. Therefore, the length of the part where the deformation occurs is
This is the sum of the height of the panda (6) and the extendable middle length of the joining metal body 0]). This length is sufficiently larger than just the height of the conventional bump (6), and the stress generated in the deformed portion is reduced, thereby extending the life of the joint.
このように、接合金属体０］）の長さを大きくすること
により応力を低下でき、従来のもののように、バンプ（
６）の体積を大きくする必要はない。したがって、半導
体チップ（１）に配置するバンプ（６）数を減らす要は
なく、半導体チップ（１）内に収容する電気的機能の規
模も制限されることはない。逆にバンプ（６）の体積を
小さくすることもでき、これによりバンプ（６）数を増
すことができ、半導体チップ（１）内に従来のものより
電気的機能を多く収容することができる。In this way, the stress can be reduced by increasing the length of the bonded metal body 0]), and unlike the conventional one, the stress can be reduced by increasing the length of the bonded metal body 0]).
6) There is no need to increase the volume. Therefore, there is no need to reduce the number of bumps (6) arranged on the semiconductor chip (1), and the scale of the electrical functions accommodated within the semiconductor chip (1) is not limited. Conversely, the volume of the bumps (6) can be made smaller, thereby increasing the number of bumps (6) and allowing more electrical functions to be accommodated in the semiconductor chip (1) than in the conventional one.
第３図ないし第６図はこの発明の他のそれぞれ異なる実
施例を示す。第３図では、接合金属体（２）の延長した
他端側を、絶縁暎（３）から離して因る。3 to 6 show other different embodiments of the invention. In FIG. 3, the other extended end of the joining metal body (2) is separated from the insulating strip (3).
第４図では、接合金属体ａ［有］の他端側を渦巻き状に
延長し、狭い空所で長さを大き′〈シている。In FIG. 4, the other end of the bonded metal body a is extended in a spiral shape, and the length is increased in a narrow space.
また、第５図では、接合金属体０荀の他端側を蛇行状に
曲げて延長し、大幅に長くしている。Further, in FIG. 5, the other end of the joint metal body 0 is bent and extended in a meandering manner, making it significantly longer.
第６図では、接合金属体００の他端側を折り返し、バン
プ（６）位置が接合金属体００の一端の接合部の下方に
なるようにしている。In FIG. 6, the other end of the bonded metal body 00 is folded back so that the bump (6) position is below the joint at one end of the bonded metal body 00.
なお、半導体チップ（１）ｌ−１：シリコン材に限らず
、ガリウム・ひ素材などの場合にも適用できるものであ
る。Note that the semiconductor chip (1) l-1 is not limited to silicon material, but can also be applied to gallium, arsenic materials, and the like.
また、上記実施例ではパッケージ（７）はアルミナ材を
用いたが、シリコンカーバイト（ＳＩＣ）、ガラス、エ
ポキシ樹脂などを用いた場合にも適用できるものである
。Further, in the above embodiment, the package (7) is made of alumina material, but it is also applicable to cases where silicon carbide (SIC), glass, epoxy resin, etc. are used.
さらに、上記実施例では、接合金属体はバンプ（６）ノ
配列方向に延長したが、バンプ（６）間のピッチが小さ
い場合は、バンプ（６）の配列方向に対し直角方向に延
長するようにしてもよい。Further, in the above embodiment, the bonded metal body extends in the direction in which the bumps (6) are arranged, but if the pitch between the bumps (6) is small, it may extend in the direction perpendicular to the direction in which the bumps (6) are arranged. You can also do this.
以上のように、この発明によれば、半導体チップの表面
の配線に、表面側の絶縁嘆の開口部を埋めた接合金属部
を接合し、この接合金属部の表面部に接合金属体の一端
部を接合し、この接合金属体の延長した他端の外表面部
にバンプを接合し、このバンプをパッケージの内部配線
上端部に接合したので、半導体装置の温度変化による接
合部分の応力が、接合金属体の延長部の変形によシ低下
され、接合部分の寿命が長くなる。また、バンプの体積
を小さくしバンプ配＠数を増すことができ、半導体チッ
プの電気的機能の収容数を増すこともできる。As described above, according to the present invention, a bonding metal part that fills the opening of the insulation on the front side is bonded to the wiring on the surface of the semiconductor chip, and one end of the bonding metal body is attached to the surface of the bonding metal part. A bump is bonded to the outer surface of the other extended end of the bonded metal body, and this bump is bonded to the upper end of the internal wiring of the package, so that stress at the bonded portion due to temperature changes in the semiconductor device is reduced. The deformation of the extended portion of the joined metal body reduces the deformation, and the life of the joined part becomes longer. Furthermore, the volume of the bumps can be reduced and the number of bumps arranged can be increased, and the number of electrical functions that can be accommodated in the semiconductor chip can also be increased.
第１図はこの発明による半導体装置の一実施例を示す要
部の拡大断面図、第２図は第１図のｎ−■線における断
面図、第３図ないし第６図はこの発明の他のそれぞれ異
なる実施例を示し、第３図はバンプ部の断面図、第４図
及び第５図はそれぞれバンプ部の第２図に相当する断面
図、第６図はバンプ部の断面図、第７図は従来の半導体
装置の断面図、第８図は第７図の装置の要部断面図、第
９図は第８図の■−ＩＸ線における！ｆ面図である。
ｌ・・・半導体チップ、２・・・配線、３・・・絶縁嘆
、３ａ・・開孔部、４・・・接合金属孔、５・・・接合
金属体、６・・・バンプ、７・・・パッケージ、８・・
内部配線、１１〜１５ ・接合金属体
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is an enlarged sectional view of essential parts showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional view taken along the line n-■ in FIG. 1, and FIGS. FIG. 3 is a sectional view of the bump portion, FIGS. 4 and 5 are sectional views corresponding to FIG. 2 of the bump portion, and FIG. 6 is a sectional view of the bump portion. 7 is a sectional view of a conventional semiconductor device, FIG. 8 is a sectional view of a main part of the device shown in FIG. 7, and FIG. It is an f-plane view. l...Semiconductor chip, 2...Wiring, 3...Insulation gap, 3a...Opening part, 4...Joining metal hole, 5...Joining metal body, 6...Bump, 7 ...Package, 8...
Internal wiring, 11 to 15 - Joined metal body Note that the same reference numerals in the drawings indicate the same or equivalent parts.
Claims (3)
した半導体装置において、上記半導体チップの表面に形
成された配線、上記半導体チップと配線の表面を覆い、
配線の所定箇所上は接続用の開孔部があけられた絶縁膜
、この開孔部に埋め込まれたい積し上記配線を接合する
接合金属部、一端がこの接合金属部の表面に接合され他
端側が延長された接合金属体、及びこの接合金属体の他
端の外表面に上部が接合し、下部が上記パッケージ側の
内部配線の上端部に接合したバンプを備えたことを特徴
とする半導体装置。(1) In a semiconductor device in which a semiconductor chip is mounted in a package using bumps, wiring formed on the surface of the semiconductor chip, covering the surfaces of the semiconductor chip and the wiring,
An insulating film with an opening for connection formed on a predetermined location of the wiring, a joining metal part embedded in the opening to join the above-mentioned wiring, one end of which is joined to the surface of this joining metal part, and the other end A semiconductor device comprising a bonded metal body with an extended side, and a bump whose upper portion is bonded to the outer surface of the other end of the bonded metal body and whose lower portion is bonded to the upper end of the internal wiring on the package side. .
特徴とする特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the other end of the bonded metal body is extended linearly.
特徴とする特許請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the other end of the bonded metal body is bent and extended.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22610884A JPS61104630A (en) | 1984-10-27 | 1984-10-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22610884A JPS61104630A (en) | 1984-10-27 | 1984-10-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61104630A true JPS61104630A (en) | 1986-05-22 |
Family
ID=16839953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22610884A Pending JPS61104630A (en) | 1984-10-27 | 1984-10-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61104630A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6221749B1 (en) | 1998-09-02 | 2001-04-24 | Shinko Electric Industries Co., Ltd. | Semiconductor device and production thereof |
| US6429517B1 (en) | 1998-10-16 | 2002-08-06 | Shinko Electric Industries Co., Ltd | Semiconductor device and fabrication method thereof |
| JP2007329503A (en) * | 1997-01-23 | 2007-12-20 | Seiko Epson Corp | Film carrier tape, semiconductor assembly, semiconductor device and manufacturing method therefor, mounting board, and electronic apparatus |
-
1984
- 1984-10-27 JP JP22610884A patent/JPS61104630A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007329503A (en) * | 1997-01-23 | 2007-12-20 | Seiko Epson Corp | Film carrier tape, semiconductor assembly, semiconductor device and manufacturing method therefor, mounting board, and electronic apparatus |
| US6221749B1 (en) | 1998-09-02 | 2001-04-24 | Shinko Electric Industries Co., Ltd. | Semiconductor device and production thereof |
| US6429517B1 (en) | 1998-10-16 | 2002-08-06 | Shinko Electric Industries Co., Ltd | Semiconductor device and fabrication method thereof |
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