JPH0669219A - Upward structure-type bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE: To improve the integration of a logic circuit by constituting a bipolar device as an upward-structure type, including an isolation oxide film, filled in a trench formed in a semiconductor substrate. CONSTITUTION: An n<+> -embedded layer 2 is formed on a silicon substrate 1, on which layer an emitter is formed. A silicon layer 3 is formed on the n<+> - embedded layer 2 which a low-temperature growing method, on which layer a substantial base is formed. After completion of the formation of a field oxide film 9, there are formed on the semiconductor substrate 1 the sequence, an N<+> -polycrystalline silicon 10, a silicide 11, a low-temperature deposited oxide film 12, and a polycrystalline silicon layer 13. In succession, after an N<+> - polycrystalline silicon electrode and a collector region are defined with a fine pattern formation method the layers 10 to 13 are selectively removed with a dry etching method. Operating voltage and a switching speed of an IIL circuit are improved by making equal the upward operating characteristic and downward operating characteristic of the bipolar device. Hereby, in the case of an ECL circuit, integration is enhanced sharply while keeping speed performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more specifically, to an upward structure type polycrystalline silicon self-alignment (Polysilicon) applicable to a system requiring high-speed information processing and linearity of processing signals. Self Al
igned: hereinafter abbreviated as "PSA") Bipolar Transistor
The present invention relates to an element and a manufacturing method thereof.

[0002]

2. Description of the Related Art Bipolar device technology, which is in the limelight in the field of electronic industry that requires high-speed information processing and linearity of signals, has been developed by a method of developing a polycrystalline silicon self-alignment (PSA) method. (Standard
Compared with the Buried Collector) technology, the switching speed and the degree of chip integration are greatly improved.
However, bipolar elements are
T (Metal Oxide Silicon Fi)
Although it has relatively high speed performance as compared with an eld Effect Transistor) device, its application field is limited by its large power consumption and low chip integration.

Therefore, in order to expand the IC application range of the bipolar device, it is basically necessary to maintain the speed performance, which is an advantage of the bipolar device, while increasing the chip integration and reducing the power consumption. Must be achieved.

To date, ECL (Emitter C
coupled logic), IIL (Integra)
The impurity concentration distribution of the emitter (Emitter), the base (Base), and the collector (Collector) in the silicon active region of the vertical bipolar transistor applied to the bipolar circuit such as ted injection (logic) is generally shown in FIG. Thus, the impurity concentration distribution of the emitter 101, the base 102, and the collector 103 of the transistor is N + / P / N- / N + type.

[0005]

In the case of the conventional bipolar device having such a structure, the upward operating characteristic has serious problems in terms of collector-emitter breakdown voltage and speed characteristic.

[0006] In fact, the IIL bipolar circuit configured in the upward-moving bipolar device is excellent in terms of integration and power consumption, but has a large limitation in circuit application due to the low operating voltage and the low switching speed. There's a problem.

An object of the present invention is to provide an upward structure type bipolar transistor capable of increasing the integration degree of a logic circuit and a manufacturing method thereof.

Another object of the present invention is to provide a bipolar transistor and a method of manufacturing the same which can significantly improve the operating voltage and switching speed of a logic circuit.

Another object of the present invention is to provide a bipolar transistor having less parasitic capacitance and parasitic resistance, and a method of manufacturing the same.

[0010]

In order to achieve the above object, according to the present invention, a semiconductor substrate (1) having an n + buried layer (2) used in an emitter region, and the above n. + A silicon layer (3) formed on the buried layer located in the active region defined by the field oxide film (9) formed on the buried layer (2) and used for the base region; A collector (co) formed on the silicon (3) with a buffer oxide film (5) interposed therebetween.
n + epitaxial (E) used for the collector region
pitaxial) layer (4) and n + polycrystal silicon (10), sidewalls (14) formed on both sides of the collector region for electrical insulation, and the n ~ on the silicon layer (3). On the base contact (17) formed at the lower end of the epitaxial layer (4) and on the buried layer (2) located between the field oxide film (9) and the silicon layer (3) in the active region. An insulating film (16) formed to electrically insulate the base region and the emitter region.
And a p + polycrystalline silicon layer (18) formed for electrical contact with the silicon layer (3) through the base contact (17) and the semiconductor substrate (1). The semiconductor substrate (1) for electrical insulation between functional elements, etc.
There is provided a semiconductor device in which a bipolar transistor is formed in the upper direction of the semiconductor substrate (1) including an isolation oxide film (8) filled in a trench formed in the above.

According to another aspect of the present invention, in the method of manufacturing a semiconductor device in which a bipolar transistor is formed on the upper side of the semiconductor substrate (1), the semiconductor substrate (is formed in order to form the emitter of the bipolar transistor). 1) a step of forming an n + buried layer (2) on the n + buried layer (2)
A step of forming a silicon layer (3) on the buried layer (2), and n to be used as a collector on the silicon layer (3).
A step of forming an epitaxial layer (4), and a step of sequentially forming a buffer oxide film (5), a nitride film (6) and a low temperature deposited oxide film (7) on the epitaxial layer (4). After defining the trench using the trench mask, the layer formed on the semiconductor substrate (1) and the semiconductor substrate having a predetermined depth are removed to form a trench,
The step of filling the trench with an oxide film (8) for isolating the element, and defining the active region by using a mask, and then removing many layers of the non-active region to remove the surface of the buried layer (2). Are selectively exposed to expose the field oxide film (9) on the exposed surface, and after removing the remaining nitride film (6), the buffer oxide film ( 5) A step of sequentially forming an n + polycrystal silicon layer (10), a silicide layer (11), a low temperature deposited oxide film (12) and a polycrystal silicon layer (13) on the same, and using a mask. A step of defining a collector region and etching a layer other than the defined collector region and the epitaxial layer (4) having a predetermined depth; and the silicide layer (11) and the n + in the collector region. Polycrystalline silicon layer (1
0), a step of forming side walls (14) for electrical insulation between the base and the collector on both sides of the buffer oxide film (5) and the n to epitaxial layers (4), and the side walls (14 ) And a sidewall nitride film (15) on the side surface of the field oxide film (9), and between the collector region and the field oxide film (9) so that the upper surface of the buried layer (2) is exposed. Removing the epitaxial layer (4) and the silicon layer (3), and oxidizing the exposed surface of the buried layer (2) to electrically insulate the base and collector. After selectively forming the film (16) and removing the sidewall nitride film (15), a p + polycrystalline silicon layer (18) having a predetermined pattern is formed,
A step of allowing the p + polycrystalline silicon layer (18) to be self-aligned through the lower ends of both sides of the n to the epitaxial layer (4), and a step of forming metal wiring on the collector and base of the bipolar transistor. There is provided a method for manufacturing a semiconductor device, comprising:

[0012]

Embodiments of the present invention will be described below with reference to FIGS.

As shown in FIG. 2, the present invention is an upward structure type bipolar device having an emitter.
201, base 202 and collector (C
collector) 203.

3 to 8 show the emitter (Emitter) and the base (Base) of the upward structure type bipolar device.
A process of forming a collector layer and a collector layer is shown.

First, an n + buried layer (Buried Layer) 2 for forming an emitter is formed on a silicon substrate 1, and an essential base (Int) is formed on the n + buried layer 2.
A low temperature growth method is applied to the silicon layer 3 capable of forming a linear base.
h process).

Then, a breakdown voltage (Break down Vo) between the collector and the emitter is formed on the silicon layer 3.
n) epitaxial layer 4 in order to control the
And a buffer oxide film 5, a nitride film 6 and a low temperature deposited oxide film (low temperature deposition) for the next step and the like on the n to epitaxial layers 4.
Ited oxide film) 7 is sequentially formed.

FIG. 4 is a cross-sectional view illustrating a process of forming a trench isolation for providing electrical insulation between devices.

First, a trench is defined by a fine pattern forming method, and then the trench is formed. Therefore, the oxide film 7, the nitride film 6, the buffer oxide film 5, n to the epitaxial layer 4, the polycrystalline silicon layers 3 and n are formed. + The buried layer 2 and the silicon substrate 1 up to a predetermined depth are sequentially removed by a dry etching method.

Then, an oxide film is coated on the semiconductor substrate having the above-mentioned multi-layer structure by a low temperature deposition method and planarized to form a trench isolation oxide film 8 as shown in FIG.

FIG. 5 shows the field oxide film (Field).
An oxide layer) is formed.

After defining the active region by a fine pattern forming method, many layers located in the non-active region are removed so that the upper surface of the n + buried layer 2 can be exposed. A field oxide film 9 is formed by a selective oxidation process.

FIG. 6 is a sectional view showing a step of defining an N + polycrystalline silicon electrode and a collector region.

After the field oxide film forming step described above is completed, the N + polycrystalline silicon 1 is formed on the semiconductor substrate.
0, a silicide film 11, a low temperature deposited oxide film 12, and a polycrystalline silicon layer 13 are sequentially formed. Subsequently, the N + polycrystalline silicon electrode and the collector region are defined by a fine pattern forming method, and then the above-mentioned layers such as 10- are formed by a dry etching method.
13 is selectively removed. Here, the N + polysilicon 10 is the N + silicon collector region 2 shown in FIG.
It acts as a diffusion source for the formation of 02.

FIG. 7 is a cross-sectional view showing a process for defining a base contact.

After growing a sidewall oxide 14 that provides self-aligned self-insulation between the collector and the base, the N-silicon layer 4 is selectively dry etched until the n + buried layer 2 is exposed. .

Then, in order to provide self-aligned electrical insulation between the emitter and the base, a sidewall oxide film 15 is formed, and then a planar oxide film 16 is selectively grown to form the sidewall nitride film 15. The base contact region 17 is defined by selective wet etching.

FIG. 8 is a cross-sectional view for explaining the step of forming the base electrode and the metal wiring.

After forming the p + polycrystalline silicon layer 18 and the silicide layer 19, a base electrode is formed by a flattening step and a fine pattern forming step.

Subsequently, a contact opening is formed by a fine pattern forming method, and then an aluminum coating step, a fine pattern forming step and a heat treatment step are sequentially performed to complete the device structure of the present invention shown in FIG. Will be realized.

[0030]

As described above, according to the present invention, the upward operating characteristic and the downward operating characteristic of the bipolar element are made equal to each other, thereby improving the operating voltage and the switching speed of the IIL circuit. In the case of the ECL circuit, the integration degree can be greatly improved while maintaining the speed performance.

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional downward structure type bipolar device.

FIG. 2 is a cross-sectional view of an upward structure type bipolar device completed by the present invention.

FIG. 3 is a cross-sectional view of an upward structure type bipolar device according to the present invention for each manufacturing process.

FIG. 4 is a cross-sectional view of the upward structure bipolar device according to the present invention for each manufacturing process.

5A to 5C are cross-sectional views of manufacturing process steps of an upward structure type bipolar device according to the present invention.

6A to 6C are cross-sectional views of manufacturing processes of an upward structure type bipolar device according to the present invention.

FIG. 7 is a cross-sectional view of the upward-structure bipolar device according to the present invention for each manufacturing process.

FIG. 8 is a sectional view of an upward structure type bipolar device according to the present invention for each manufacturing process.

[Explanation of symbols]

1: Silicon substrate, 2: n + buried layer, 3: polycrystalline silicon, 4: n-epitaxial layer, 5, 7, 8, 9, 1
2, 14, 16: oxide film, 6, 11, 15, 19: nitride film, 10, 13, 18: polycrystalline silicon

Claims (3)

[Claims] 1. A semiconductor substrate (1) on which an n + buried layer (2) used in an emitter region is formed, and a field oxide film (9) formed on the n + buried layer (2). And a buffer layer (5) is sandwiched between the silicon layer (3) formed on the buried layer located in the active region defined by and used for the base region and the silicon (3). N + epitaxial layer (4) to be formed and used for the collector region
And n + polycrystalline silicon (10), sidewalls (14) formed on both sides of the collector region for electrical insulation, and n to the epitaxial layer (4) on the silicon layer (3). A base contact (17) formed at a lower end, and a base contact (17) formed on the buried layer (2) located between the field oxide film (9) and the silicon layer (3) in the active region. And an insulating film (16) for electrical insulation between the emitter layer and the emitter region, and the silicon layer (3) through the base contact (17).
Formed on the semiconductor substrate (1) for electrical insulation between the p + polycrystalline silicon layer (18) formed for electrical contact with the functional element and the like formed on the semiconductor substrate (1). A semiconductor device in which a bipolar transistor is formed in the upper direction of the semiconductor substrate (1), including an isolation oxide film (8) filled in the formed trench. 2. A method of manufacturing a semiconductor device, wherein a bipolar transistor is formed on an upper side of a semiconductor substrate (1), wherein an n + buried layer (2) is formed on the semiconductor substrate (1) to form an emitter of the bipolar transistor. ) To form the base of the bipolar transistor,
A step of forming a silicon layer (3) on the n + buried layer (2), a step of forming n to an epitaxial layer (4) used as a collector on the silicon layer (3), and the epitaxial layer A buffer oxide film (5), a nitride film (6) and a low temperature deposited oxide film (7) on (4)
And a step of sequentially forming the trench and defining the trench by using a trench mask, and then removing the layer and the like formed on the semiconductor substrate (1) and the semiconductor substrate having a predetermined depth to form the trench. , A step of filling the trench with an oxide film (8) for isolating the element, and after defining an active region by using a mask, many layers of the inactive region are removed to remove the buried layer (2). A step of selectively forming a field oxide film (9) on the exposed surface so that the surface is exposed, and the buffer oxide film after removing the remaining nitride film (6) A step of sequentially forming an n + polycrystalline silicon layer (10), a silicide layer (11), a low temperature deposited oxide film (12) and a polycrystalline silicon layer (13) on (5), and using a mask Other than the collector area defined above by defining the collector area with A step of etching a layer such as an epitaxial layer of the predetermined depth (4), in the collector region, the silicide layer (11),
On both sides of the n + polycrystalline silicon layer (10), the buffer oxide film (5) and the n to epitaxial layer (4),
The side wall (1 for electrical insulation between the base and the collector)
4) and after forming a sidewall nitride film (15) on the sidewalls (14) and side surfaces of the field oxide film (9), exposing the upper surface of the buried layer (2). The step of removing the epitaxial layer (4) and the silicon layer (3) between the collector region and the field oxide film (9), and the step of removing the exposed buried layer (2) on the surface. Oxide film (16) for electrical insulation of the base and the collector
And selectively removing the sidewall nitride film (15), a p + polycrystalline silicon layer (18) having a predetermined pattern is formed, and the p + polycrystalline silicon layer (18) is removed. n ~ Epitaxial layer (4)
A method of manufacturing a semiconductor device, comprising the steps of allowing self-alignment through the lower ends of both sides of the bipolar transistor and the step of forming metal wiring on the collector and base of the bipolar transistor. 3. The side wall (14) according to claim 1, wherein
A semiconductor device that is an oxide film.