JPH0669095B2 - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH0669095B2 JPH0669095B2 JP60233291A JP23329185A JPH0669095B2 JP H0669095 B2 JPH0669095 B2 JP H0669095B2 JP 60233291 A JP60233291 A JP 60233291A JP 23329185 A JP23329185 A JP 23329185A JP H0669095 B2 JPH0669095 B2 JP H0669095B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- gate electrode
- electrode
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 19
- 239000010408 film Substances 0.000 claims description 41
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 230000005684 electric field Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910017875 a-SiN Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、例えばフラツトデイスプレイにおいて各画素
を構成する表示駆動用電極と同一絶縁基板上に集積され
てスイツチング素子として用いられる薄膜トランジスタ
に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a switching element integrated on the same insulating substrate as a display driving electrode which constitutes each pixel in a flat display, for example. .
フラツトデイスプレイをアクテイブマトリツクス方式で
駆動する方法は、従来より知られており、けい光表示管
や液晶デイスプレイを利用した携帯用テレビ等が提案さ
れている（日経エレクトロニクス1984年９月10日号第21
1頁）。A method of driving a flat display by an active matrix system has been known in the past, and a portable television using a fluorescent display tube or a liquid crystal display has been proposed (Nikkei Electronics September 10, 1984 issue. 21st
1).
しかしながら、これらの表示装置が未だ十分に実用化さ
れるに至つていないのは、高密度の微細パターンを形成
する際の歩留りに問題があることの他、微細化したとき
のスイツチング用トランジスタの特性に問題があること
による。すなわち、スイツチング用トランジスタは周囲
光によつてオフ電流が増大し、オンオフ特性が劣化する
という問題がある。However, the reason why these display devices have not been fully put into practical use is that there is a problem in the yield when forming a high-density fine pattern, and in addition, there is a problem with switching transistors when miniaturized. Due to a problem with the characteristics. That is, the switching transistor has a problem that the off-current increases due to the ambient light and the on-off characteristics deteriorate.
このような問題を改善するものとしては、第45回応用物
理学会予稿集P343.14a−Ｑ−７に開示されているように
光入射を防止する遮光膜を設けたアモルフアスシリコン
薄膜トランジスタが提案されている。As a solution to such a problem, an amorphous silicon thin film transistor provided with a light shielding film for preventing light incidence is proposed as disclosed in Proceedings of the 45th Japan Society of Applied Physics P343.14a-Q-7. ing.
第２図および第３図はこの種の薄膜トランジスタを示す
断面図である。同図において、１は透光性ガラス板から
なる絶縁基板、２はCr,ITO等からなるゲート電極、３は
SiO2,SiNｘ等からなるゲート絶縁膜、４はアモルフアス
シリコン（以下ａ−Siと称する）などからなるａ−Si
膜、５はコンタクト領域、6,7はCr,ITO等からなるソー
ス電極およびドレイン電極、８はSiO2,SiNｘ等からなる
パツシベーシヨン膜、９は遮光膜である。2 and 3 are sectional views showing this type of thin film transistor. In the figure, 1 is an insulating substrate made of a transparent glass plate, 2 is a gate electrode made of Cr, ITO or the like, and 3 is
A gate insulating film made of SiO 2 , SiN x or the like, and 4 are a-Si made of amorphous silicon (hereinafter referred to as a-Si)
A film 5 is a contact region, 6 and 7 are source and drain electrodes made of Cr, ITO, etc., 8 is a passivation film made of SiO 2 , SiN x, etc., and 9 is a light-shielding film.
このように構成される薄膜トランジスタは、ゲート電極
２とソース電極６との間に加える電界の大きさを変化さ
せることによつてソース電極６とドレイン電極７との間
の電気抵抗を変化させることができる。すなわち、スイ
ツチ機能をもたせることができる。つまり、アクテイブ
マトリツクスデイスプレイにおいては、各画素に付設さ
れた薄膜トランジスタのスイツチ機能を利用し、スイツ
チオンのとき画素に画像情報を書き込み、スイツチオフ
のときその情報を保持させるようにしたものである。The thin film transistor thus configured can change the electric resistance between the source electrode 6 and the drain electrode 7 by changing the magnitude of the electric field applied between the gate electrode 2 and the source electrode 6. it can. That is, the switch function can be provided. That is, in the active matrix display, the switch function of the thin film transistor attached to each pixel is used, image information is written in the pixel when the switch is on, and the information is held when the switch is off.
しかしながら、このような構成によると、ａ−Si膜４へ
の光入射をゲート電極２と遮光膜９とで防止したとして
もゲート電極２よりもａ−Si膜４の幅寸法が大であれ
ば、ゲート電極２の幅寸法よりもはみ出したａ−Si膜４
に光が入射し、オフ抵抗が十分に大きくならないという
問題があつた。したがつて、ａ−Si膜４はゲート電極２
の幅寸法よりも小さくする必要があるが、第３図に示す
ようにソース電極6,ドレイン電極７とゲート電極２とを
ゲート絶縁膜３で絶縁する部分が生じる。この結果、ゲ
ート電極２のエツジ部分でゲート絶縁膜３の電界による
破壊が生じ易くなり、歩留りを低下させることになる。However, according to such a configuration, even if the light incident on the a-Si film 4 is prevented by the gate electrode 2 and the light shielding film 9, if the width dimension of the a-Si film 4 is larger than that of the gate electrode 2. , A-Si film 4 protruding beyond the width of the gate electrode 2
There was a problem that the off resistance did not become sufficiently large when light was incident on. Therefore, the a-Si film 4 is the gate electrode 2
However, as shown in FIG. 3, there is a portion where the gate electrode 2 insulates the source electrode 6, the drain electrode 7 and the gate electrode 2 from each other. As a result, the edge portion of the gate electrode 2 is apt to be destroyed by the electric field of the gate insulating film 3, and the yield is reduced.
本発明の目的は、周囲光の入射によつて生じるオフ特性
の劣化を防止することができるａ−Si薄膜トランジスタ
を提供することにある。It is an object of the present invention to provide an a-Si thin film transistor capable of preventing the deterioration of off characteristics caused by the incidence of ambient light.
本発明の他の目的は、ゲート電極のエツジでゲート絶縁
膜の電界による破壊を防止することができるａ−Si薄膜
トランジスタを提供することにある。Another object of the present invention is to provide an a-Si thin film transistor capable of preventing the gate insulating film from being destroyed by an electric field due to the edge of the gate electrode.
本発明の一実施例によれば、ａ−Si膜をゲート電極の寸
法よりも大とし、ゲート電極の寸法よりもはみ出したａ
−Si膜を薄膜トランジスタのチヤンネル領域から分離
し、ソース電極とドレイン電極との間に光電流を流さな
い構成とすることにより、オフ特性の劣化を防止させか
つゲート絶縁膜の電界による破壊を確実に防止した薄膜
トランジスタが提供される。According to one embodiment of the present invention, the a-Si film is made larger than the size of the gate electrode, and a is larger than the size of the gate electrode.
-By separating the Si film from the channel region of the thin film transistor and preventing photocurrent from flowing between the source electrode and the drain electrode, the off characteristics are prevented from being deteriorated and the breakdown of the gate insulating film due to the electric field is ensured. A protected thin film transistor is provided.
次に図面を用いて本発明の実施例を詳細に説明する。 Next, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明による薄膜トランジスタおよびその製造
方法の一実施例を説明するための断面図であり、前述の
図と同一部分には同一符号を付してある。同図におい
て、絶縁基板１上にCr,AlあるいはTa等の金属をスパツ
タリングし、通常のフオトリソグラフイ技術で加工して
ゲート電極２を形成する。次にゲート電極２が形成され
た絶縁基板１上に、ａ−SiN,SiO2あるいはAl2O3等の金
属およびａ−Siを同一真空雰囲気中でプラズマCVD法に
よりゲート絶縁膜３およびａ−Si膜４を順次連続形成
し、このａ−Si膜４をフオトリソグラフイ技術によりパ
ターニングを行なつてゲート絶縁膜３上にａ−Siからな
るチヤンネル領域4a,アイランド部4bおよびこれらの上
面にn+−aSi膜4cを形成する。次にａ−Si膜４が形成さ
れたゲート絶縁膜３上にMg,AlあるいはAu（As）等の金
属をスパツタリングし、フオトリソグラフイ技術で加工
してソース電極６およびドレイン電極７をそれぞれ形成
する。この場合、これらのソース電極６およびドレイン
電極７はａ−Siアイランド部4bの周囲を完全に囲んだ構
造で形成される。次にこれらのソース電極６およびドレ
イン電極７上にSiO2あるいはSiNｘ等のパツシベーシヨ
ン膜８を形成した後、このパツシベーシヨン膜８上にC
r,AlあるいはTa等の金属をスパツタリングし、フオトリ
ソグラフイ技術で加工し、遮光膜９を形成して完成す
る。FIG. 1 is a sectional view for explaining one embodiment of a thin film transistor and a method of manufacturing the same according to the present invention, and the same parts as those in the above-mentioned drawings are designated by the same reference numerals. In the figure, a metal such as Cr, Al or Ta is sputtered on an insulating substrate 1 and processed by a normal photolithography technique to form a gate electrode 2. Then, on the insulating substrate 1 on which the gate electrode 2 is formed, a metal such as a-SiN, SiO 2 or Al 2 O 3 and a-Si are formed by the plasma CVD method in the same vacuum atmosphere by the gate insulating film 3 and a- A Si film 4 is successively and successively formed, and the a-Si film 4 is patterned by photolithography technique to form a channel region 4a made of a-Si on the gate insulating film 3, an island portion 4b, and n on the upper surface thereof. A + -aSi film 4c is formed. Next, metal such as Mg, Al or Au (As) is sputtered on the gate insulating film 3 on which the a-Si film 4 is formed and processed by photolithography technique to form a source electrode 6 and a drain electrode 7, respectively. To do. In this case, the source electrode 6 and the drain electrode 7 are formed so as to completely surround the periphery of the a-Si island portion 4b. Next, after forming a passivation film 8 of SiO 2 or SiN x on the source electrode 6 and the drain electrode 7, C is formed on the passivation film 8.
A metal such as r, Al or Ta is sputtered and processed by photolithography technique to form a light shielding film 9 to complete the process.
このような構成によれば、ゲート絶縁膜３上に形成され
るａ−Si膜４が活性層としてａ−Siチヤンネル領域4aお
よびそのはみ出し部分がａ−Siアイランド部4bとしてソ
ース電極６とドレイン電極７とにより分離されるととも
に、ａ−Siアイランド部4bが完全に包囲されて形成され
るので、ａ−Siアイランド部4b内での電界勾配が零とな
る。したがつて、ゲート電極２よりも寸法が大きいａ−
Siアイランド部4bに周囲光が照射されてもａ−Siアイラ
ンド部4bで発生した光電流がチヤンネル領域4aに流れ込
むことはない。すなわち、オフ特性が光照射によつて劣
化することがなくなる。なお、コンタクト改善のために
n+−aSi膜4cをソース電極6,ドレイン電極７との間に形
成しているが、このn+−aSi膜4cがなくても本実施例の
効果が失なわれることはない。According to such a configuration, the a-Si film 4 formed on the gate insulating film 3 serves as an active layer, the a-Si channel region 4a and the protruding portion serve as the a-Si island portion 4b, which are the source electrode 6 and the drain electrode. 7 and the a-Si island portion 4b is completely surrounded and formed, the electric field gradient in the a-Si island portion 4b becomes zero. Therefore, a- which is larger than the gate electrode 2 in size
Even if the Si island portion 4b is irradiated with ambient light, the photocurrent generated in the a-Si island portion 4b does not flow into the channel region 4a. That is, the off characteristics are not deteriorated by the light irradiation. In order to improve contact
Although the n + -aSi film 4c is formed between the source electrode 6 and the drain electrode 7, the effect of the present embodiment is not lost even without the n + -aSi film 4c.
また、このような方法によれば、絶縁破壊防止用のａ−
Siアイランド部4bは、ａ−Siチヤンネル領域4aの形成お
よびソース電極6,ドレイン電極７の形成と同一工程内で
それぞれ分離して同時に形成できるので、工程数を増加
させることなく容易に形成され、歩留りを向上させるこ
とができる。Further, according to such a method, a-
Since the Si island portion 4b can be separately formed at the same time in the same process as the formation of the a-Si channel region 4a and the formation of the source electrode 6 and the drain electrode 7, they can be easily formed without increasing the number of processes. The yield can be improved.
以上説明したように本発明による薄膜トランジスタは、
ゲート電極の寸法よりもはみ出したａ−Si膜を薄膜トラ
ンジスタのチヤンネル領域から分離させたことにより、
ソース電極とドレイン電極との間に光電流が流れ込むこ
とがなくなるので、オフ特性の劣化を防止できるととも
に、ゲート絶縁膜の電界による破壊が防止でき、品質、
信頼性の高い薄膜トランジスタが得られるという極めて
優れた効果を有する。As described above, the thin film transistor according to the present invention,
By separating the a-Si film protruding beyond the dimension of the gate electrode from the channel region of the thin film transistor,
Since the photocurrent does not flow between the source electrode and the drain electrode, it is possible to prevent the deterioration of the off characteristics and prevent the gate insulating film from being destroyed by the electric field.
It has an extremely excellent effect that a highly reliable thin film transistor can be obtained.
【図面の簡単な説明】 第１図は本発明による薄膜トランジスタおよびその製造
方法の一実施例を説明するための断面図、第２図および
第３図は従来の薄膜トランジスタを示す断面図である。 １……絶縁基板、２……ゲート電極、３……ゲート絶縁
膜、４……ａ−Si膜、4a……ａ−Siチヤンネル領域、4b
……ａ−Siアイランド部、4c……n+−aSi膜、５……コ
ンタクト領域、６……ソース電極、７……ドレイン電
極、８……パツシベーシヨン膜、９……遮光膜、。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view for explaining one embodiment of a thin film transistor and a method for manufacturing the same according to the present invention, and FIGS. 2 and 3 are sectional views showing a conventional thin film transistor. 1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... a-Si film, 4a ... a-Si channel region, 4b
... a-Si island part, 4c ... n + -aSi film, 5 ... contact region, 6 ... source electrode, 7 ... drain electrode, 8 ... passivation film, 9 ... light-shielding film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 金子 好之 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 筒井 謙 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshiyuki Kaneko 1-280 Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (72) Ken Ken Tsutsui 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory
Claims (2)
と、アモルファスシリコン膜よりなり上記ゲート電極の
幅寸法よりも小さいチヤンネル部と、上記チヤンネル部
の一方に接続されるソース電極および他方に接続される
ドレイン電極とよりなる薄膜トランジスタにおいて、 上記チヤンネル部は遮光手段により遮光され、上記ソー
ス電極と上記ゲート電極の一方のエツジ部分の間およ
び、上記ドレイン電極と上記ゲート電極の他方のエツジ
部分の間に、それぞれ、上記アモルファスシリコン膜よ
りなり上記チヤンネル部から分離されたアイランド部を
設けたことを特徴とする薄膜トランジスタ。1. An insulating substrate, a gate electrode, a gate insulating film, a channel portion made of an amorphous silicon film and having a width smaller than the width of the gate electrode, and a source electrode connected to one of the channel portion and the other. In the thin film transistor including a drain electrode connected to the channel portion, the channel portion is shielded by a light shielding means, and the portion between the edge portion of one of the source electrode and the gate electrode and the other edge portion of the drain electrode and the gate electrode is formed. A thin film transistor characterized in that an island portion made of the amorphous silicon film and separated from the channel portion is provided therebetween.
と、上記アモルファスシリコン膜との間に不純物をドー
プしたアモルファスシリコン膜を設けたことを特徴とす
る特許請求の範囲第１項記載の薄膜トランジスタ。2. A thin film transistor according to claim 1, wherein an amorphous silicon film doped with impurities is provided between the source and drain electrodes and the amorphous silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60233291A JPH0669095B2 (en) | 1985-10-21 | 1985-10-21 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60233291A JPH0669095B2 (en) | 1985-10-21 | 1985-10-21 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6293978A JPS6293978A (en) | 1987-04-30 |
| JPH0669095B2 true JPH0669095B2 (en) | 1994-08-31 |
Family
ID=16952801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60233291A Expired - Lifetime JPH0669095B2 (en) | 1985-10-21 | 1985-10-21 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669095B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2620240B2 (en) * | 1987-06-10 | 1997-06-11 | 株式会社日立製作所 | Liquid crystal display |
| JPS6422066A (en) * | 1987-07-17 | 1989-01-25 | Toshiba Corp | Thin film transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60211982A (en) * | 1984-04-06 | 1985-10-24 | Hitachi Ltd | Thin film transistor |
| JPS61248564A (en) * | 1985-04-26 | 1986-11-05 | Nec Corp | Thin film transistor and manufacture thereof |
-
1985
- 1985-10-21 JP JP60233291A patent/JPH0669095B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60211982A (en) * | 1984-04-06 | 1985-10-24 | Hitachi Ltd | Thin film transistor |
| JPS61248564A (en) * | 1985-04-26 | 1986-11-05 | Nec Corp | Thin film transistor and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6293978A (en) | 1987-04-30 |
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