JPH0669003A - Laminated voltage dependent nonlinear resistor element and manufacture thereof - Google Patents
Laminated voltage dependent nonlinear resistor element and manufacture thereofInfo
- Publication number
- JPH0669003A JPH0669003A JP4216686A JP21668692A JPH0669003A JP H0669003 A JPH0669003 A JP H0669003A JP 4216686 A JP4216686 A JP 4216686A JP 21668692 A JP21668692 A JP 21668692A JP H0669003 A JPH0669003 A JP H0669003A
- Authority
- JP
- Japan
- Prior art keywords
- external electrode
- internal electrodes
- film
- external
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Thermistors And Varistors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、積層型電圧非直線抵抗
素子及びその製造方法に関し、特にチップ状部品本体の
上下両側に外部保護膜を形成した積層型非直線抵抗素子
及びその製造方法。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated voltage non-linear resistance element and a method for manufacturing the same, and more particularly to a laminated non-linear resistance element in which external protective films are formed on both upper and lower sides of a chip component body and a method for manufacturing the same.
【0002】[0002]
【従来の技術】積層型電圧非直線抵抗素子(以下チップ
バリスタと称する)は、図3に示すようにセラミックシ
ートを適当な大きさにパンチングし、その上に所定のパ
ターンの内部電極33,34をスクリーン印刷し、この
内部電極が印刷されたセラミックシート35,36を適
当な枚数を重ねて熱圧着し、焼成を行い、外部電極3
1,32を塗布し焼き付けることにより図示のような構
造を有するチップバリスタを得ることができる。図3の
(A)は、チップバリスタの斜視図であり、(B),
(C)は、(A)をC−C1 線,D−D1 線で切断した
時の断面図である。(例えば特公昭58−23921号
公報)。2. Description of the Related Art In a laminated type voltage non-linear resistance element (hereinafter referred to as a chip varistor), a ceramic sheet is punched into an appropriate size as shown in FIG. Are screen-printed, and an appropriate number of the ceramic sheets 35 and 36 on which the internal electrodes are printed are laminated by thermocompression and baked to form the external electrodes 3.
A chip varistor having the structure shown in the drawing can be obtained by applying and baking 1, 32. FIG. 3A is a perspective view of the chip varistor, and FIG.
(C) is a sectional view taken along the (A) C-C 1 line, with D-D 1 line. (For example, Japanese Patent Publication No. 58-23921).
【0003】[0003]
【発明が解決しようとする課題】この従来のチップバリ
スタは、図3のように上下両側面はチップバリスタの素
子が露出している状態と同じであり、高温高湿中でチッ
プバリスタに直流電圧を印加した場合、立ち上がり電圧
が変化し、またもれ電流が増加し、次第にバリスタとし
ての特性が劣化する現象が生じる。これは、高温高湿に
よる水分がチップバリスタ内部まで浸透し、素子の劣化
が加速されるという問題点があった。This conventional chip varistor has the same condition as the elements of the chip varistor are exposed on both the upper and lower sides as shown in FIG. 3, and the DC voltage is applied to the chip varistor in high temperature and high humidity. When the voltage is applied, the rising voltage changes, the leakage current increases, and the characteristics of the varistor gradually deteriorate. This causes a problem that moisture due to high temperature and high humidity permeates into the inside of the chip varistor, and the deterioration of the element is accelerated.
【0004】本発明の目的は、従来の欠点を除去し、高
温高湿においてバリスタ特性の向上した積層型電圧非直
線抵抗素子およびその製造方法を提供することにある。It is an object of the present invention to provide a laminated type voltage non-linear resistance element which eliminates the conventional defects and has improved varistor characteristics at high temperature and high humidity, and a manufacturing method thereof.
【0005】[0005]
【課題を解決するための手段】本発明のチップバリスタ
は、内部電極が引刷されたセラミックシートを積層し、
積層したユニットを絶縁性を持つガラス等で外部電極を
除く全面をセラミックシートで覆っている外部保護膜を
形成している。これにより高温高湿中の水分がチップバ
リスタ内部まで浸透するのを防ぎ、水分による素子の劣
化加速を阻止することができる。A chip varistor of the present invention comprises a stack of ceramic sheets having internal electrodes printed thereon,
An external protective film is formed by covering the entire surface of the stacked units with a glass sheet having an insulating property except the external electrodes with a ceramic sheet. As a result, it is possible to prevent the moisture in the high temperature and high humidity from penetrating into the inside of the chip varistor, and to prevent the deterioration of the element from being accelerated by the moisture.
【0006】[0006]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0007】図1は本発明の一実施例のチップバリスタ
の斜視図及びA−A1 並びにB−B1 断面図である。[0007] Figure 1 is a perspective view and A-A 1 and B-B 1 cross-sectional view of the chip varistor according to an embodiment of the present invention.
【0008】まず、従来方法と同じように、内部電極
5,6が印刷されたセラミックシート7,8を適当な枚
数を重ねて積層し、積層したユニットを第一熱圧着を行
い内部電極が互い違いに露出しない方向へ図2のような
スティック状のユニットに切断する。次にガラス等の絶
縁性を持つスリラー状の混合物をドクターブレード法等
により電極を形成したセラミックシートより厚い膜を形
成し、その厚い製膜でユニット全体を覆い保護膜で覆わ
れたユニットを得る。そして、最終第2熱圧着を行い、
次いで内部電極5,6が互い違いに露出するように切
断、焼成する。最後に、外部電極1,2が外部保護膜
3,4,9,10に重なるように塗付し、焼き付けを行
うことにより図1のようなチップバリスタを得ることが
できる。図1の(B),(C)は(A)を線分A−
A1 ,B−B1 で切断した時の断面図である。First, as in the conventional method, an appropriate number of ceramic sheets 7 and 8 on which the internal electrodes 5 and 6 are printed are stacked and stacked, and the stacked units are subjected to the first thermocompression bonding so that the internal electrodes are staggered. Cut it into a stick-shaped unit as shown in Fig. 2 in the direction not exposed. Next, a chiller-like mixture having an insulating property such as glass is formed into a film thicker than the ceramic sheet on which electrodes are formed by the doctor blade method etc., and the unit is covered with the thick film to obtain a unit covered with a protective film. . Then, the final second thermocompression bonding is performed,
Next, the internal electrodes 5 and 6 are cut and fired so that they are exposed alternately. Finally, the external electrodes 1 and 2 are applied so as to overlap the external protective films 3, 4, 9, and 10 and baked to obtain a chip varistor as shown in FIG. 1 (B) and 1 (C) show (A) as a line segment A-
Is a sectional view taken along with A 1, B-B 1.
【0009】次に、本実施例の効果を確認するために行
った試験を示す。温度80℃,湿度95%中で、立ち上
がり電圧を示すバリスタ電圧の80%の直流電圧を10
00時間連続印加した場合、表1のように、外部保護膜
無しの試料はバリスタ電圧の変化率が大きく、もれ電流
の増加も大きいが、外部保護膜有りの試料は、バリスタ
電圧の変化率が小さくもれ電流の増加も小さい。高温高
湿性に対する特性が改善されている。Next, a test conducted to confirm the effect of this embodiment will be shown. At a temperature of 80 ° C and a humidity of 95%, a DC voltage that is 80% of the varistor voltage indicating the rising voltage is 10
When continuously applied for 00 hours, as shown in Table 1, the sample without the external protective film has a large change rate of the varistor voltage and the leakage current also has a large increase. Is small and the increase in leakage current is small. The characteristics for high temperature and high humidity are improved.
【0010】 [0010]
【0011】[0011]
【発明の効果】以上説明したように本発明は、外部電極
を除く全面にガラス等の絶縁性を持つ外部保護膜のシー
トを形成したので高温高湿性に対するバリスタ特性が向
上するという結果を有する。As described above, the present invention has the result that the varistor characteristic with respect to high temperature and high humidity is improved because the sheet of the external protective film having an insulating property such as glass is formed on the entire surface excluding the external electrodes.
【図1】本発明の一実施例の斜視図及びA−A1 並びに
B−B1 線断面図である。FIG. 1 is a perspective view and an AA 1 and BB 1 line sectional view of an embodiment of the present invention.
【図2】本発明の一実施例の製造方法を説明するための
一部工程のスティック状部品の斜視図である。FIG. 2 is a perspective view of a stick-shaped component in a partial process for explaining the manufacturing method according to the embodiment of the present invention.
【図3】従来の積層型電圧非直線抵抗素子の一例の斜視
図及びA−A1 線並びにB−B1 線の断面図である。FIG. 3 is a perspective view of an example of a conventional laminated type voltage non-linear resistance element and a cross-sectional view taken along line AA 1 and line BB 1 .
1,2,31,32 外部電極 3,4,9,10 外部保護膜 5,6,21,33,34 内部電極 7,8,22,35,36 セラミックシート 1, 2, 31, 32 External electrode 3, 4, 9, 10 External protective film 5, 6, 21, 33, 34 Internal electrode 7, 8, 22, 35, 36 Ceramic sheet
Claims (2)
積層、焼結したセラミックシート積層体と、前記セラミ
ックシート積層体の外部電極形成面を除く上下側面を覆
うガラス等の絶縁性保護膜と、前記外部電極形成面に形
成された外部電極とを有することを特徴とする積層型電
圧非直線抵抗素子。1. A ceramic sheet laminate obtained by laminating and sintering ceramic sheets printed with internal electrodes, an insulating protective film such as glass covering the upper and lower side surfaces of the ceramic sheet laminate except the external electrode forming surface, A laminated voltage non-linear resistance element having an external electrode formed on an external electrode formation surface.
を適当枚数重ねて積層熱圧着し、内部電極が互い違いに
露出しない方向にスティック状のユニットに切断する工
程と、ガラス等の絶縁性を持つスラリー状の泥漿をドク
ターブレード法等により製膜し、前記セラミックシート
より厚い膜を形成する工程と、前記成膜でスティック状
ユニット全体を覆い熱圧着する工程と、電極が互い違い
に露出する位置で切断、焼成する工程と、前記内部電極
露出面に外部保護膜に重なるように電極材を塗布、焼成
して外部電極を形成する工程とを含むことを特徴とする
積層型電圧非直線抵抗素子の製造方法。2. A step of stacking a suitable number of ceramic sheets on which internal electrodes are printed, stacking them by thermocompression bonding, and cutting them into stick-shaped units in a direction in which the internal electrodes are not exposed alternately, and a slurry having an insulating property such as glass. Forming a thick film by a doctor blade method etc. to form a film thicker than the ceramic sheet, a step of thermocompression covering the entire stick-shaped unit with the film formation, and cutting at positions where the electrodes are alternately exposed And a step of applying an electrode material to the exposed surface of the internal electrode so as to overlap the external protective film and firing the electrode material to form an external electrode. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4216686A JPH0669003A (en) | 1992-08-14 | 1992-08-14 | Laminated voltage dependent nonlinear resistor element and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4216686A JPH0669003A (en) | 1992-08-14 | 1992-08-14 | Laminated voltage dependent nonlinear resistor element and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0669003A true JPH0669003A (en) | 1994-03-11 |
Family
ID=16692338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4216686A Pending JPH0669003A (en) | 1992-08-14 | 1992-08-14 | Laminated voltage dependent nonlinear resistor element and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0669003A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016085004A1 (en) * | 2014-11-28 | 2016-06-02 | 홍익대학교 산학협력단 | Laminated ceramic chip component including nano thin film layer, manufacturing method therefor, and atomic layer vapor deposition apparatus therefor |
CN112748186A (en) * | 2020-12-09 | 2021-05-04 | 深圳供电局有限公司 | Method and device for detecting water content of piezoresistor, control equipment and medium |
-
1992
- 1992-08-14 JP JP4216686A patent/JPH0669003A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016085004A1 (en) * | 2014-11-28 | 2016-06-02 | 홍익대학교 산학협력단 | Laminated ceramic chip component including nano thin film layer, manufacturing method therefor, and atomic layer vapor deposition apparatus therefor |
US10513433B2 (en) | 2014-11-28 | 2019-12-24 | Hongik University Industry-Academic Corporation Foundation | Laminated ceramic chip component including nano thin film layer, manufacturing method therefor, and atomic layer vapor deposition apparatus therefor |
CN112748186A (en) * | 2020-12-09 | 2021-05-04 | 深圳供电局有限公司 | Method and device for detecting water content of piezoresistor, control equipment and medium |
CN112748186B (en) * | 2020-12-09 | 2022-07-08 | 深圳供电局有限公司 | Method and device for detecting water content of piezoresistor, control equipment and medium |
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