JP2504226B2 - Stacked Varistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a laminated varistor functioning as a voltage non-linear resistance, and in particular, it prevents deterioration of internal electrodes to prevent deterioration of varistor characteristics, while improving resistance. The present invention relates to a structure capable of avoiding variation in values.

[Conventional technology]

Generally, a varistor is a resistor element whose resistance value changes non-linearly according to an applied voltage. As such a varistor, there is a conventional rectangular parallelepiped laminated varistor as shown in FIG. 8 (for example, See Japanese Patent Publication No. 58-23921). The laminated varistor 10 has ceramic layers 11 containing ZnO as a main component and internal electrodes 12 alternately laminated and integrally sintered, and the external electrodes 14 are formed on the left and right end faces 13a and 13b of the sintered body 13. Is formed. Further, one end surface 12a of each internal electrode 12 is alternately exposed to the left and right end surfaces 13a and 13b of the sintered body 13 and is connected to the external electrode 14.

[Problems to be solved by the invention]

However, the conventional laminated varistor 10 has a structure in which one end face 12a of the internal electrode 12 is exposed to the outside when viewed as a sintered body 13, and therefore, in an atmosphere of high humidity, the exposed portion of the internal electrode 12 is exposed. Therefore, there is a problem that the quality is easily changed, and as a result, the varistor characteristics are deteriorated and the reliability of the quality is poor. Further, in the above-mentioned conventional laminated varistor 10, when the external electrode 14 is formed by plating or when the surface of the external electrode 14 is subjected to plating for the purpose of improving the solderability of the external electrode 14. However, there is a problem that the plating solution easily enters from the exposed portion of the internal electrode 12, which also deteriorates the characteristics.

Here, the applicant of the present invention, due to the above-mentioned high humidity atmosphere,
Alternatively, in order to prevent the internal electrodes from deteriorating due to the penetration of the plating solution, a multilayer varistor as shown in FIG. 7 has been proposed (Japanese Patent Application No. 63-225849). This stacked varistor 2
In the case of 0, the internal electrode 22 is embedded in the sintered body 21 so that one end surface 22a thereof is not exposed, and the left and right end surfaces 21a, 21
In the b portion, a lead layer 23 having a low resistance value formed by solid-solving a metal such as Al is formed, and one end face 22a of the internal electrode 22 is alternately connected to the outer electrode 24 via the lead layer 23. It will be. According to this laminated varistor 20, since the internal electrode 22 is enclosed in the sintered body 21 to completely eliminate the exposed portion, even when used in a high-humidity atmosphere, when forming an external electrode. Even when immersed in a plating solution, the internal electrodes can be prevented from deteriorating, and as a result, the deterioration of characteristics can be avoided.

By the way, as in the laminated varistor 20, the internal electrode 22
In the structure in which the sintered body 21 is embedded in the sintered body 21, in order to connect the internal electrode 22 to the external electrode 24, the left and right end faces 21a,
It is necessary to form the lead layer 23 having a low resistance value in the portion 21b.
In this case, Al ₂ O ₃ , Fe ₂ O _{3 on} both end faces 21a, 21b of the sintered body 21
Etc. and applying a semiconducting agent, etc., and baking this at 1100 ° C. to semiconduct the both end surfaces 21a, 21b.
I am trying to establish continuity with 2. However, the sintered body 2
When forming the lead-out layer 23 by dissolving Al or the like in 1 as a solid solution, it is difficult to control the thickness t of the lead-out layer 23, and the lead-out layer 23 may reach the other end surface 22b of the internal electrode 22 to cause a short circuit in some cases. It was found that the resistance value of the lead-out layer 23 is likely to vary.

An object of the present invention is to provide a laminated varistor capable of avoiding variations in resistance value when the internal electrode is embedded in a sintered body to prevent the internal electrode from being deteriorated due to high humidity or penetration of a plating solution. It is in.

[Means for solving problems]

Therefore, the present invention provides a laminated varistor in which a varistor layer and internal electrodes are alternately laminated to form a laminated body,
The above-mentioned laminated body is characterized by being formed of an integral sintered body of a laminated portion of a varistor layer and an internal electrode, and semiconductor ceramic layers formed on both ends of this laminated portion and having no varistor characteristic.

Here, the semiconductor ceramic layer that does not exhibit varistor characteristics in the present invention contains, for example, ZnO as a main component, and Al _{2
O 3, Fe 2 O 3,} Y 2 O 3, Ln 2 O 3, Ga 2 O 3, In 2 O 3, Sc 2 O 3 were mixed at least one kind selected from, which was formed into a paste It can be realized by applying a material to the above-mentioned laminated body or by heat-treating it.

Further, the semiconductor ceramics layer may be applied to a fired sintered body, or may be applied to a laminated body before firing and thereafter sintered together at the same time.

[Action]

According to the laminated varistor of the present invention, since the semiconductor ceramics layer is provided on the end face of the laminated portion, one end face of the internal electrode, that is, the exposed portion of the internal electrode can be completely covered with the ceramics layer. In addition to preventing deterioration of internal electrodes even in high humidity atmosphere,
The plating solution can be prevented from entering when forming the external electrodes, and the reliability of quality can be improved.

Further, in the present invention, the thickness of the ceramics layer can be set in advance, because it has a structure in which a semiconductor ceramics layer is formed on the end surface of the laminated portion by coating or the like.
The thickness can be controlled more easily and surely as compared with the case where a metal such as Al is solid-dissolved in the above-mentioned laminated body, and as a result, it is possible to prevent a short circuit between the ceramic layer and other internal electrodes, and to prevent variations in resistance value. This can be avoided and the internal electrode can be stabilized when it is led out.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

1 to 4 are views for explaining a laminated varistor according to an embodiment of the present invention.

In the drawing, reference numeral 1 denotes a multilayer varistor of the present embodiment,
The varistor 1 has a rectangular parallelepiped shape, and its basic structure is that a varistor layer 2 containing ZnO as a main component and an internal electrode 3 made of Pt are alternately laminated and integrally fired to form a laminated portion 4 External electrodes 5 made of Ag / Pd on the left and right end faces 4a, 4b of the
Is formed by coating. Further, one end surface 3a of each internal electrode 3 is alternately exposed to the left and right end surfaces 4a, 4b of the laminated portion 4, and the other end surface 3b is left of the laminated portion 4.
It is located slightly away from the right end faces 4a and 4b.

Then, between the left and right end surfaces 4a, 4b of the laminated portion 4 and the external electrode 5, a semiconductor ceramic layer 6 having no varistor characteristic is provided. The ceramic layer 6 covers both end surfaces 4a and 4b of the laminated portion 4 and is connected to the exposed one end surface 3a of the internal electrode 3, whereby the internal electrode 3 is connected to the external electrode via the ceramic layer 6. 5
Is electrically connected to The above semiconductor ceramic layer 6
Is formed by applying an oxide semiconductor ceramic paste to both end surfaces 4a and 4b of the laminated portion 4 and heating and baking the same.

Next, a method of manufacturing the laminated varistor 1 of this embodiment will be described.

The main component is ZnO, and impurities such as Bi ₂ O ₃ and Pr ₆ O
A green sheet is formed from a ceramic composition made by mixing at least one of ₁₁ , ₁₁ , CoO, MnO, Sb ₂ O ₃ , Cr ₂ O ₃ , and SiO ₂ , and the green sheet is cut into a rectangular shape of a predetermined size. Then, the ceramics layer 2 which becomes many varistor layers is formed.

An internal electrode 3 is formed by printing a paste made by mixing Pt with a vehicle on the upper surface of each ceramic layer 2. In this case, the one end surface 3a of the internal electrode 3 has the above-mentioned ceramic layer 2
Is exposed on one end surface of the ceramics and the other end surface 3b is located inside the ceramics layer 2.

Next, as shown in FIG. 3, one end surface of the internal electrode 3 is formed so that the internal electrode 3 and the ceramics layer 2 are alternately superposed.
3a are sequentially laminated so that they are alternately located, and a ceramic layer 8 as a dummy is further laminated on the upper and lower surfaces of this laminated body,
This is pressed and pressed by a press to form a laminated portion 4 '. Then, as shown in FIG. 4, one end surface of each internal electrode 3
Only 3a is exposed on the left and right end faces of the laminated portion 4 '.

Next, a ZnO as a main component, to which _{Al 2 O 3, Fe 2 O} 3, Y 2 O 3, Ln
_At least one selected from ₂ O ₃ , Ga ₂ O ₃ , In ₂ O ₃ , and Sc ₂ O ₃ is mixed, and a heat treatment is performed to form a ceramics paste that becomes a semiconductor. This paste is applied to the left and right end faces of the laminated portion 4'to have a thickness of 5 to 10 .mu.m, and then this is heated and baked in air at 1000 to 1300.degree. To get Then, the semiconductor ceramics layer 6 having a reduced resistance value is formed by the heating and firing, and as a result, the ceramics layer 6 and the one end surface 3a of the internal electrode 3 are connected.

Here, as the semiconductor ceramics layer 6, a method in which a sintered body is prepared in advance in the above step, and then a ceramics paste is applied and baked is also applicable. Also,
It is also possible to form the semiconductor ceramic layer by adopting a ceramic paste that does not require baking and applying it. Further, the semiconductor ceramics layer 6 may be formed by pressing it into a sheet shape.

Finally, the outer surface of the laminated portion 4 excluding the left and right end surfaces 4a and 4b is covered with a mask, and in this state, electrolytic plating is performed to form the external electrode 5 on the outer surface of the semiconductor ceramic layer 6. In addition, the external electrode 5 is provided on the laminated portion 4.
It may be formed by applying a paste containing Ag as a main component and adding Pd and then baking it. Thus, the multilayer varistor 1 of the present embodiment is manufactured.

 Next, the function and effect of this embodiment will be described.

According to the laminated varistor 1 of the present embodiment, since the one end faces 3a of the internal electrodes 3 exposed on the left and right end faces 4a, 4b of the laminated portion 4 are completely covered with the semiconductor ceramics layer 6, it is possible to operate in a high humidity atmosphere. The internal electrode 3 does not change in quality even when it is used, and the plating solution does not enter even when the laminated portion 4 is dipped in the electrolytic plating solution. Therefore, deterioration of varistor characteristics can be prevented, and the quality can be improved. Can be improved.

In addition, in this embodiment, since the semiconductor ceramics layer 6 for connecting each internal electrode 3 to the external electrode 5 is applied to both end faces of the laminated portion 4'and baked, the thickness of the ceramics layer 6 is reduced. Control becomes easy, and short circuit defects can be significantly reduced as compared with the case where the above-mentioned metal is dissolved. Moreover, the semiconductor ceramics layer 6 can obtain a stable resistance value by adjusting the additive separately in advance, thereby lowering the resistance value and improving the nonlinear coefficient α.

Next, an experiment conducted to confirm the effect of this embodiment will be described.

Experiment 1 First, the laminated varistor used in this experiment will be described. The manufacturing method is substantially the same as the steps 1 to 3 in the above embodiment.

First, ZnO (98.0mol%), Bi ₂ O ₃ (0.5mol%), CoO
(0.5mol%), MnO (0.5mol%), Sb ₂ O ₃ (0.5mol%) mixed ceramic composition is formed on the green sheet, and the internal electrode made of Ag-Pd is printed and then pressure-bonded. Then, a laminated portion was formed.

Next, ZnO (99.45mol%), Al ₂ O ₃ (0.05mol%), B ₂ O
₃ (0.5 wt%) mixed semiconductor ceramics paste is applied to both end faces of the above-mentioned laminated portion so as to have a thickness of 5 to 10 μm, followed by firing at 1100 ° C. for 2 hours, and then this sintering An external electrode was formed on the outer surface of the semiconductor ceramics layer of the body, and thus a sample of this example was prepared.

Next, the laminated varistor created above was left for 1000 hours in an atmosphere of a temperature of 60 ° C. and a relative humidity of 90%, and the _V1mA , V
The rate of change of _{0.1 mA} was investigated. Moreover, the variation of the nonlinear coefficient α was also investigated. For comparison, a laminated varistor (structure of FIG. 7) made by diffusing Al metal on both end faces of the sintered body was adopted as a comparative sample, and the end face of the internal electrode was exposed on the surface of the sintered body. Multilayer varistor (8th
The structure shown in the figure) was adopted as a conventional sample, and the same test was performed for these samples.

FIG. 5 shows the relationship between the change rate of V _{1 mA} and the elapsed time, and FIG. 6 shows the relationship between the change rate of V _{0.1 mA} and the elapsed time. In the figure, curve A (dashed-dotted line) shows the sample of this example, curve B (dashed line) shows the comparative sample, and curve C (solid line) shows the conventional sample.

As is clear from the figure, in the case of the conventional sample (curve C), the rate of change of V _{1 mA} is -9%, and the rate of change of V _{0.1 mA} is -25%. On the other hand, in the case of the sample of the present example (curve A) and the comparative sample (curve B) in which the exposed portion of the internal electrode was completely removed, V _{1 mA} was -4% and V _{0.1 mA} was -9%. That is, it can be seen that the moisture resistance is improved.

Table 1 shows the variation of the nonlinear coefficient α. In the table, the first column shows the sample of this example, the second column shows the comparative sample, and the third column shows the conventional sample. As is clear from the table, each sample has α
_{At 0.1-1mA} , there is no big difference from 32 to 35, but α _1-10mA
And the variation of α _0.1-1A (3CV%) was 29.0 for the comparative sample.
(10.0%) and 13.1 (20.6%), and the characteristics deteriorate. On the other hand, in the sample of this example, α _{1-10 mA}
30.2 (5.2%) and α _0.1-1A significantly decreased to 17.6 (7.2%), which is almost the same level as the conventional sample. Further, the short circuit failure rate in the sample of this example is
It was significantly improved from 10% of the comparative sample to 0.1%.

Experiment 2 In this experiment, the same laminated portion as in Experiment 1 above was created.
On both end faces of the laminated part, various kinds (No. 1
11 to 11), the semiconductor ceramic paste was applied, and the respective V _1mA , α _1-10mA , α _0.1-1A , and moisture resistance were examined. The semiconductor ceramic paste has a thickness of 5-10.
μm, and the firing temperature was 1100-1150 ° C. and the firing was performed at the same time as the laminated portion, and thereafter the external electrodes were formed.

As is clear from Table 2, even when the No. 1 to No. 11 semiconductor ceramic pastes are used, V _1mA
11.6 to 14.5, α _{1-10mA to 28.1} to 33.7, α _0.1-1A to 11.6
It was improved to ~ 19.8, and satisfactory results were obtained for all samples in terms of moisture resistance.

〔The invention's effect〕

As described above, according to the multilayer varistor according to the present invention,
Since the semiconductor ceramics layer is applied so as to cover the one end surface of the internal electrode exposed on the end surface of the laminated portion, it has the effect of preventing the deterioration of the internal electrode due to high humidity or invasion of the plating solution. It is possible to reduce the short circuit failure when deriving the value, and to avoid the variation of the resistance value and improve the nonlinear coefficient.

[Brief description of drawings]

1 to 4 are views for explaining a laminated varistor according to an embodiment of the present invention. FIG. 1 is its sectional view, FIG. 2 is its perspective view, and FIG. 3 is its manufacturing process. 4 (a) to 4 (c) are perspective views thereof, FIGS. 5 and 6 are characteristic diagrams showing the effect of the present embodiment, and FIG. 7 is the present invention. FIG. 8 is a cross-sectional view of a laminated varistor which is the background of the establishment of the above, and FIG. 8 is a sectional view showing a conventional laminated varistor. In the figure, 1 is a multilayer varistor, 2 is a ceramics layer,
3 is an internal electrode, 3a is one end face, 4 is a laminated portion, 4a and 4b are left and right end faces, and 6 is a semiconductor ceramics layer.

Claims (1)

(57) [Claims] 1. A laminated varistor formed by alternately laminating a varistor layer and an internal electrode to form a laminated body, which functions as a voltage non-linear resistance, wherein the laminated body is a laminated body of a varistor layer and an internal electrode. A laminated varistor comprising a portion and a semiconductor ceramic layer formed on both ends of the laminated portion and having no varistor characteristic, which is an integral sintered body.