JPH0770373B2 - Method of manufacturing laminated chip varistor - Google Patents
Method of manufacturing laminated chip varistorInfo
- Publication number
- JPH0770373B2 JPH0770373B2 JP61107101A JP10710186A JPH0770373B2 JP H0770373 B2 JPH0770373 B2 JP H0770373B2 JP 61107101 A JP61107101 A JP 61107101A JP 10710186 A JP10710186 A JP 10710186A JP H0770373 B2 JPH0770373 B2 JP H0770373B2
- Authority
- JP
- Japan
- Prior art keywords
- chip varistor
- varistor
- laminated chip
- zinc oxide
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Thermistors And Varistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、酸化亜鉛を主成分とする積層型チップバリス
タの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated chip varistor containing zinc oxide as a main component.
従来の技術 酸化亜鉛系バリスタは、電圧非直線抵抗特性を有し、現
在の半導体素子を主軸とする電子機器において、その半
導体素子を保護するためのサージアブソーバとして重要
な役割を果たしている。2. Description of the Related Art A zinc oxide varistor has a voltage non-linear resistance characteristic and plays an important role as a surge absorber for protecting a semiconductor element in a current electronic device having a semiconductor element as a main axis.
しかし、最近の機器においては軽薄短小化および低電圧
化が進み、低バリスタ電圧，高サージ耐量の特性を有す
るサージアブソーバが必要とされている。これに対応す
るものとして、積層型の酸化亜鉛系チップバリスタが実
用化されてきた。However, in recent devices, lightening, thinning, shortening and miniaturization and lowering of voltage have progressed, and a surge absorber having characteristics of low varistor voltage and high surge withstand is required. In response to this, a laminated zinc oxide-based chip varistor has been put into practical use.
従来、この種のチップバリスタの製造方法は、酸化亜鉛
系粉末と有機溶剤とからなるスラリーをシート状に成形
し、グリーンシートをつくり、乾燥後、白金，パラジウ
ム，銀などの高温で安定な貴金属ペーストを、前記グリ
ーンシートに交互に印刷積層することによって内部電極
をつくり、これを焼成し、焼結体の両端に銀−パラジウ
ムの合金からなる外部電極を形成するものであった。Conventionally, this type of chip varistor has been manufactured by forming a slurry of a zinc oxide-based powder and an organic solvent into a sheet, forming a green sheet, and drying it. An internal electrode was formed by alternately printing and laminating the paste on the green sheet, and was fired to form an external electrode made of a silver-palladium alloy on both ends of the sintered body.
発明が解決しようとする問題点 このような従来の方法では、外部電極に銀−パラジウム
の合金を使用しているが、これは銀だけではマイブレー
ションの発生や、ハンダ付け性が悪くなるためで、これ
を防ぐため、20％前後のパラジウムを含有したパラジウ
ムと銀との合金を使用している。しかし、パラジウムは
高価であり、素子のコストを上げてしまう欠点がある。
そこで、銀電極にニッケルメッキを施し、さらに半田メ
ッキを施すことにより、半田付け性を向上させ銀の半田
への拡散を防ぐことができる。しかし、酸化亜鉛系バリ
スタはセラミックス表面や内部に気孔が多く、メッキ処
理時にメッキ液がセラミックス内部に浸透し、バリスタ
電圧，サージ耐量等の電気的諸特性の劣化を生じさせる
という問題があった。Problems to be Solved by the Invention In such a conventional method, an alloy of silver-palladium is used for the external electrode, but this is because silver alone causes the occurrence of migration and deteriorates the solderability. To prevent this, an alloy of palladium and silver containing about 20% palladium is used. However, palladium is expensive and has the drawback of increasing the cost of the device.
Therefore, by plating the silver electrode with nickel and then with solder, the solderability can be improved and the diffusion of silver into the solder can be prevented. However, the zinc oxide varistor has many pores on the surface and inside of the ceramic, and there is a problem that the plating solution penetrates into the ceramic during the plating process and causes deterioration of various electrical characteristics such as varistor voltage and surge resistance.
本発明はこのような問題点を解決するもので、メッキ液
が素子内に浸透することがなく、電気特性の低下を防ぐ
ことを目的とするものである。The present invention solves such a problem, and an object of the present invention is to prevent the plating liquid from penetrating into the element and prevent the deterioration of the electrical characteristics.
問題点を解決するための手段 この問題点を解決するために本発明は、積層型のチップ
バリスタの焼結体にシリコンオイルをディップさせ、こ
れを高温で処理することにより、ガラス成分を拡散させ
るとともに、セラミックス表面にガラス成分層を形成さ
せるものである。Means for Solving the Problem In order to solve this problem, the present invention makes a sintered body of a laminated chip varistor dipped with silicone oil and treats it at a high temperature to diffuse a glass component. At the same time, a glass component layer is formed on the ceramic surface.
作用 この方法により、ガラス成分が素子内に浸透して、表面
および表面近傍の気孔をふさぎ、メッキ液の侵入を防
ぎ、電気特性の劣化を防ぐ。そして、メッキが可能なた
め、半田付け性も向上し、外部電極にパラジウムを使う
必要性がなくなり、素子のコストダウンが図れることと
なる。Action By this method, the glass component permeates into the element to block the surface and pores near the surface, prevent the invasion of the plating solution, and prevent the deterioration of the electrical characteristics. Further, since plating is possible, solderability is improved, there is no need to use palladium for the external electrode, and the cost of the element can be reduced.
実施例 以下、本発明の一実施例について図面を参照しながら説
明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.
まず、酸化亜鉛を主成分とするバリスタ粉末に対し、バ
インダー，可塑剤，分散剤，有機溶媒を加え、スラリー
化し、ドクターブレード法により、任意の厚みのグリー
ン・シートを作成する。これを所定の大きさに切断し、
これに白金ペーストを印刷したものを積層し、圧着後、
規定の大きさに切断する。こうして得られた素子は脱脂
後、1100〜1300℃で焼成し、素子の面取りを行う。この
面取り後、素子を十分乾燥させた。次に、メチルフェニ
ルシリコンオイル（信越化学（株）製のKF−45品番）等
のシリコンオイルをトリクロルエタンで希釈し、40％,6
0％,80％,100％の濃度のシリコンオイルを上記積層型焼
結体にディップさせ、30分間の真空脱泡を行った。その
後150〜200℃で３時間乾燥させ、800〜1000℃で熱処量
を行い、このようにして得られた積層型チップバリスタ
の両端に銀の外部電極を塗布，焼付けし、さらに銀の外
部電極の上に、ニッケルメッキ，ハンダメッキと重ねて
形成した。First, a binder, a plasticizer, a dispersant, and an organic solvent are added to a varistor powder containing zinc oxide as a main component to form a slurry, and a doctor blade method is used to prepare a green sheet having an arbitrary thickness. Cut this into a predetermined size,
After laminating what printed platinum paste on this, after pressure bonding,
Cut to the specified size. The element thus obtained is degreased and then baked at 1100-1300 ° C. to chamfer the element. After this chamfering, the element was sufficiently dried. Next, dilute silicon oil such as methylphenyl silicone oil (KF-45 product number manufactured by Shin-Etsu Chemical Co., Ltd.) with trichloroethane to give 40%, 6%.
Silicone oil having concentrations of 0%, 80%, and 100% was dipped in the above-mentioned laminated sintered body, and vacuum degassing was performed for 30 minutes. After that, it is dried at 150 to 200 ° C for 3 hours, heat treated at 800 to 1000 ° C, and silver external electrodes are applied and baked on both ends of the multilayer chip varistor thus obtained. It was formed by overlaying nickel plating and solder plating on the electrode.
第１図はこの本発明を用いた製造方法によって得られた
積層型チップバリスタの断面図である。図において、１
は酸化亜鉛系のセラミックス、２は白金電極、３は銀電
極、４はニッケルメッキ、５はハンダメッキである。FIG. 1 is a sectional view of a multilayer chip varistor obtained by the manufacturing method according to the present invention. In the figure, 1
Is zinc oxide ceramics, 2 is a platinum electrode, 3 is a silver electrode, 4 is nickel plating, and 5 is solder plating.
下記の表にシリコンオイル濃度と熱処理温度を検討した
結果を示す。The table below shows the results of examining the silicone oil concentration and heat treatment temperature.
なお、湿中負荷の条件は、60℃,90〜95％R.H,課電率90
％PC,1000Hrである。ここで、シリコンオイルは上述し
たようにトリクロルエタンである程度希釈した方が浸透
性が良くなるが、希釈しすぎるとシリコンオイルの塗着
量が少なくなり、内部までガラス成分が浸透しなくな
る。また、熱処理温度についても900℃付近が良好であ
る。 In addition, the condition of the load in the humidity is 60 ℃, 90 ~ 95% RH, the charge rate 90
% PC, 1000Hr. Here, as described above, the silicone oil has better permeability when it is diluted with trichloroethane to some extent, but if it is diluted too much, the coating amount of the silicone oil becomes small and the glass component does not penetrate to the inside. Also, the heat treatment temperature is preferably around 900 ° C.
発明の効果 以上のように本発明によれば、シリコンオイルを高温で
熱処理することにより、メッキ液が素子内に浸透するこ
とを防ぎ、電気特性の低下を防ぐことになる。以上のこ
とより、本発明は産業上で非常に利用価値のあるもので
ある。EFFECTS OF THE INVENTION As described above, according to the present invention, heat treatment of silicon oil at a high temperature prevents the plating solution from penetrating into the element and prevents deterioration of electrical characteristics. From the above, the present invention is very useful in industry.
図は本発明の積層型チップバリスタの製造方法により得
られた積層型チップバリスタの断面図である。 １……酸化亜鉛系のセラミックス、２……白金電極、３
……銀電極、４……ニッケルメッキ、５……半田メッ
キ。The figure is a cross-sectional view of a multilayer chip varistor obtained by the method for manufacturing a multilayer chip varistor of the present invention. 1 ... Zinc oxide ceramics, 2 ... Platinum electrode, 3
…… Silver electrode, 4 …… Nickel plating, 5 …… Solder plating.
Claims (1)
コンオイルをディップし、高温で熱処理することにより
焼結体内部にガラス成分を拡散させた積層型チップバリ
スタの製造方法。1. A method of manufacturing a laminated chip varistor in which a glass component is diffused inside a sintered body by dipping silicon oil into a laminated body of a zinc oxide varistor and heat-treating at high temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61107101A JPH0770373B2 (en) | 1986-05-09 | 1986-05-09 | Method of manufacturing laminated chip varistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61107101A JPH0770373B2 (en) | 1986-05-09 | 1986-05-09 | Method of manufacturing laminated chip varistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62263609A JPS62263609A (en) | 1987-11-16 |
| JPH0770373B2 true JPH0770373B2 (en) | 1995-07-31 |
Family
ID=14450483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61107101A Expired - Fee Related JPH0770373B2 (en) | 1986-05-09 | 1986-05-09 | Method of manufacturing laminated chip varistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770373B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02220403A (en) * | 1989-02-21 | 1990-09-03 | Ube Ind Ltd | Manufacture of laminated ceramic varistor |
| JP2682259B2 (en) * | 1991-04-03 | 1997-11-26 | 株式会社村田製作所 | Manufacturing method of multilayer varistor |
| JPH06231906A (en) * | 1993-01-28 | 1994-08-19 | Mitsubishi Materials Corp | Thermistor |
| JP5188390B2 (en) * | 2006-03-15 | 2013-04-24 | 株式会社村田製作所 | Multilayer electronic component and manufacturing method thereof |
-
1986
- 1986-05-09 JP JP61107101A patent/JPH0770373B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62263609A (en) | 1987-11-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |