JPS62122103A - Manufacture of laminated chip varistor - Google Patents
Manufacture of laminated chip varistorInfo
- Publication number
- JPS62122103A JPS62122103A JP60262162A JP26216285A JPS62122103A JP S62122103 A JPS62122103 A JP S62122103A JP 60262162 A JP60262162 A JP 60262162A JP 26216285 A JP26216285 A JP 26216285A JP S62122103 A JPS62122103 A JP S62122103A
- Authority
- JP
- Japan
- Prior art keywords
- chip varistor
- multilayer chip
- powder
- silver
- varistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Thermistors And Varistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は酸化亜鉛(ZnO)を主成分とする積層型チッ
プバリスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a multilayer chip varistor whose main component is zinc oxide (ZnO).
従来の技術
従来より、酸化亜鉛(ZnO)を主成分とする積層型チ
ップバリスタは印加電圧によって著しく抵装置が変わ9
.電圧−電流特性が顕著な非直線性を示す。このため、
エレクトロニクス機器の電圧の安定化や、サージ電流に
対する回路保護用素子として、幅広く使用されてきた。Conventional technology Conventionally, the resistance of multilayer chip varistors whose main component is zinc oxide (ZnO) changes significantly depending on the applied voltage9.
.. The voltage-current characteristics show significant nonlinearity. For this reason,
It has been widely used to stabilize voltages in electronic equipment and as a circuit protection element against surge currents.
最近では機器の小型化及び低電圧化が進み、これに対応
してセラミックシートの積層技術を応用して、小型で低
バ、リスク電圧・高サージ耐量を特徴とする酸化亜鉛系
の積層型チップバリスタが注目されている。Recently, equipment has become smaller and lower voltage, and in response to this trend, we have applied ceramic sheet lamination technology to create a zinc oxide-based laminated chip that is small, low-impact, has high risk voltage, and high surge resistance. Baristas are attracting attention.
積層型チップバリヌタの製造方法は、酸化亜鉛を主成分
とするセラミック粉末と有機物とからなるセラミックグ
リーンシート上に、白金、パラジウム、銀などの高温で
安定な貴金属ペーストをセラミックシート層と交互にく
し型構造になるように印刷し、その後、所定の形状に切
断し、グリーンチップをつくる。これを、大気中で焼成
し焼結体を得、この焼結体の両端に銀−パラジウムの合
金を焼付けて外部電極を形成させ、積層型のチップバリ
スタを製造しているものであった。The manufacturing method for laminated chip Balinuta is to comb a ceramic green sheet made of ceramic powder mainly composed of zinc oxide and an organic material with a noble metal paste such as platinum, palladium, silver, etc. that is stable at high temperatures, alternating with ceramic sheet layers. Print the structure and then cut it into a predetermined shape to create a green chip. This was fired in the atmosphere to obtain a sintered body, and a silver-palladium alloy was baked on both ends of this sintered body to form external electrodes, thereby manufacturing a multilayer chip varistor.
発明が解決しようとする問題点
このような従来の構成では、積層型のセラミック体の端
子電極を銀だけで形成すると、銀によるマイグレーショ
ンが発生したりハンダ付性が悪ぐなシ、これを改善する
ために20%前後のパラジウムを添加した銀−パラジウ
ム合金が用いられている。しかしながら、パラジウムは
1gあたシの市価700〜900円と高価であり、これ
を添加することによシミ極のコストが3〜5倍になる。Problems to be Solved by the Invention In such a conventional configuration, if the terminal electrodes of the laminated ceramic body are formed only of silver, migration due to silver will occur and solderability will be poor. In order to achieve this, a silver-palladium alloy to which around 20% palladium is added is used. However, palladium is expensive, with a market price of 700 to 900 yen per gram, and adding palladium increases the cost of the stain electrode by three to five times.
さらにパラジウムの添加に代えて、例えばNati o
nal、Technical、 Rep’i1M、 V
o 131、A3の第145頁に記載された「積層セラ
ミックコンデンサ用高誘電率誘電体材料」のように銀電
極上にメッキするという方法も行われているが、ZnO
系積層型チップバリスタはセラミックスの内部気孔が多
くさらに端子電極とチップバリスタとの密着性が悪い。Furthermore, instead of adding palladium, for example Nati o
nal, Technical, Rep'i1M, V
o 131, A3, p. 145, "High permittivity dielectric material for multilayer ceramic capacitors" is a method of plating on silver electrodes, but ZnO
The multilayer chip varistor has many internal pores in the ceramic, and the adhesion between the terminal electrode and the chip varistor is poor.
このため酸性のメッキ液が内部に浸透し、バリスタ電圧
。As a result, the acidic plating solution penetrates into the interior, reducing the varistor voltage.
耐量などの電気的特性が劣化し、良好な特性のものが得
られないという問題があった。There was a problem in that electrical properties such as withstand capacity deteriorated, making it impossible to obtain products with good properties.
問題点を解決するための手段
本発明は上記問題点を解決するために、ジルコニア粉末
とガラス粉末の混合粉末中に、積層研チップバリスタの
焼結体を埋込んで熱処理を行い、ガラス成分を拡散させ
、素体の表面にガラス成分層を形成し、しかる後銀電憧
及び金属メッキ層を形成するものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention embeds a sintered body of a multilayer chip varistor in a mixed powder of zirconia powder and glass powder and heat-treats it to remove the glass component. Diffusion is performed to form a glass component layer on the surface of the element body, and then a silver electroplating layer and a metal plating layer are formed.
作 用
このような方法を用いることによシ、ガラス成分が積層
型チップバリスタの内部気孔・や、欠陥部を補い、素体
を緻密化させ、さらK、素体と端子電極との密着性を向
上させ接着強度を大きぐすることによシ、酸性メッキ液
の積層体内部への浸透を防ぎ、メッキ後の電気的特性の
劣化を防ぐものである。Effect By using such a method, the glass component compensates for the internal pores and defects in the multilayer chip varistor, densifies the element, and further improves the adhesion between the element and the terminal electrodes. By improving the adhesive strength and preventing the acidic plating solution from penetrating into the laminate, this prevents the electrical properties from deteriorating after plating.
実 施 例 本発明を以下、実施例に基づいて説明する。Example The present invention will be explained below based on examples.
酸化亜鉛を主成分とするセラミック粉末に有機結合剤、
有機溶剤を加えてスラリー化し、ドクターブレードで厚
さ50層程度のグリーンシートを造る。これを所定の大
きさに切断し白金ペーストを印刷し1層シートと交互の
くし形構造をなすようにグリーンシートの積層と、ペー
ストの印刷を行い10層の構造とした。その後、所望の
形状に切断しグリーンチップを作成する。Ceramic powder mainly composed of zinc oxide, organic binder,
Add an organic solvent to make a slurry, and use a doctor blade to create a green sheet approximately 50 layers thick. This was cut into a predetermined size, platinum paste was printed on it, green sheets were laminated to form a comb-shaped structure alternating with single-layer sheets, and the paste was printed to obtain a 10-layer structure. Thereafter, it is cut into a desired shape to create green chips.
このグリーンチップの有機物を脱脂して、1200〜1
300℃で焼結させ、積層型チップバリスタを製造した
。この焼結体チップの大きさは1,5 x 3 x O
,55Cmm)であった。After degreasing the organic matter from this green chip, it becomes 1200 to 1
A multilayer chip varistor was manufactured by sintering at 300°C. The size of this sintered chip is 1.5 x 3 x O
, 55 Cmm).
この積層チップバリスタの焼結体を、酸化ジルコニア粉
末1001景部に対して第1表のようにガラス粉末を混
合して得られた混合粉末中に埋込み、この状態において
800°Cで熱処理した。このようにして得られたチッ
プバリスタの両端に銀電極ペーストを塗布し焼付を行な
った。銀電極の上にはNiメッキを1〜2μ、さらに、
ハンダメッキを4〜6μ形成することによシ、端子電憧
を形成した。第1図は本発明の製造方法によって得られ
た積層チップバリスタを示し1図において(1)は酸化
亜鉛系のセラミック体、(2)は白金電瞳、(3)はガ
ラス粉末拡散層、(4)は銀被覆、(5)はNiメッキ
、(6)はハンダメッキである。The sintered body of this multilayer chip varistor was embedded in a mixed powder obtained by mixing zirconia oxide powder 1001 with glass powder as shown in Table 1, and heat-treated at 800°C in this state. Silver electrode paste was applied to both ends of the thus obtained chip varistor and baked. On top of the silver electrode, apply 1~2μ of Ni plating, and
Terminals were formed by forming 4 to 6 μm of solder plating. FIG. 1 shows a multilayer chip varistor obtained by the manufacturing method of the present invention. In FIG. 1, (1) is a zinc oxide ceramic body, (2) is a platinum electrode pupil, (3) is a glass powder diffusion layer, 4) is silver coated, (5) is Ni plated, and (6) is solder plated.
第1表は従来の製造方法の一つとして端子電極に銀−パ
ラジウムを用いた方法と、別の従来方法として銀電極を
形成し、チップへのガラス粉末の拡散なしに前記銀電極
にメッキした方法と1本発明の製造方法に基づく場合の
積層チップバリスタの、V、mAのバリスタ電圧サージ
耐量の電気的特性素体の抗折強度、引張シ強度の物理的
特性を示す。Table 1 shows one conventional manufacturing method in which silver-palladium was used for the terminal electrode, and another conventional method in which a silver electrode was formed and the silver electrode was plated without diffusion of glass powder into the chip. 1 shows the electrical properties of the varistor voltage surge withstand capacity of V and mA of the multilayer chip varistor based on the manufacturing method of the present invention; and the physical properties of the bending strength and tensile strength of the element body.
上記第1表からも明らかなように、本発明の積層型チッ
プバリスタは、従来方法に比較してメッキ後の電気的特
性(特にサージ耐量)の劣化がなく、従来方法のいずれ
に対しても抗折強度、引張強度が著しく向上しているこ
とが認められ、良好な結果が得られた。なお、Brzo
3゜B203−5i02系のガラス粉末の良好な添加量
の範囲は5〜20%であった。すなわち、5係以下では
ガラス成分の拡散の効果が十分に表われず、逆に20チ
を越えると、ガラス成分が多すぎて、組成ずれが発生し
、バリスタ電圧、サージ耐量がずれてくるからである。As is clear from Table 1 above, the multilayer chip varistor of the present invention shows no deterioration in electrical characteristics (especially surge resistance) after plating compared to conventional methods, and It was observed that the bending strength and tensile strength were significantly improved, and good results were obtained. In addition, Brzo
A good range of addition amount of 3°B203-5i02 type glass powder was 5 to 20%. In other words, if the coefficient is less than 5, the effect of diffusion of the glass component will not be sufficiently exhibited, and if it exceeds 20, on the other hand, the glass component will be too large, causing a compositional deviation, which will cause a deviation in the varistor voltage and surge resistance. It is.
なお、上記実施例では、 Bib、 Br203.5i
02系のガラス粉末を用いたが積層型チップバリスタの
電気的、物理的特性を劣化させないものであれば、いか
なるガラス入粉末にも適用できるものである。In addition, in the above example, Bib, Br203.5i
Although 02 series glass powder is used, any glass-containing powder can be used as long as it does not deteriorate the electrical and physical characteristics of the multilayer chip varistor.
発明の効果
以上、述べたように1本発明の積層型チップバリスタは
、Ni、ハンダメッキ後の電気的特性がきわめて浸れて
いるため、これをプリント基板だ直に半田付けする場合
にクランクを防止することができるとともに、電極コス
トを大きく下げることに貢献し、本発明の効果は大なる
ものである。As mentioned above, the multilayer chip varistor of the present invention has very strong electrical characteristics after being plated with Ni and solder, which prevents cranking when soldering directly to a printed circuit board. In addition, the present invention contributes to greatly reducing electrode costs, and the effects of the present invention are significant.
積層型チップパリヌタの断面図である。FIG. 3 is a cross-sectional view of a laminated chip parinuta.
(1) −−−−一酸化亜鉛系士ラミック体(2) −
−−−一白金電極
(31−−−−−ガラス粉末の拡散層
(4) −−−−一銀
(51−−−−−Niメッキ
[61−−−−−ハンダメッキ(1) -----Zinc monoxide-based lamic body (2) --
--- One platinum electrode (31 --- Glass powder diffusion layer (4) --- One silver (51 --- Ni plating [61 --- Solder plating
Claims (1)
層が交互に積層されてなる積層焼結体を、ジルコニア粉
末及びガラス粉末の混合粉末中に埋込んだ後、熱処理す
ることにより上記焼結体内部に上記ガラス成分を拡散さ
せてなる積層型チップバリスタの素体を形成し、この素
体の両端に銀電極を被覆形成するとともに、金属メッキ
処理を施すことを特徴とする積層型チップバリスタの製
造方法。A laminated sintered body in which ceramic body layers and metal electrode layers containing zinc oxide as a main component are alternately laminated is embedded in a mixed powder of zirconia powder and glass powder, and then heat treated to produce the above-mentioned sintered body. A multilayer chip varistor is characterized in that a multilayer chip varistor element body is formed by diffusing the above-mentioned glass component inside, and silver electrodes are coated on both ends of the element body, and a metal plating process is performed. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60262162A JPS62122103A (en) | 1985-11-20 | 1985-11-20 | Manufacture of laminated chip varistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60262162A JPS62122103A (en) | 1985-11-20 | 1985-11-20 | Manufacture of laminated chip varistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62122103A true JPS62122103A (en) | 1987-06-03 |
Family
ID=17371922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60262162A Pending JPS62122103A (en) | 1985-11-20 | 1985-11-20 | Manufacture of laminated chip varistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62122103A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01295403A (en) * | 1988-01-27 | 1989-11-29 | Murata Mfg Co Ltd | Chip varister |
JPH0468502A (en) * | 1990-07-09 | 1992-03-04 | Murata Mfg Co Ltd | Varistor and its manufacture |
JPH05283206A (en) * | 1992-03-30 | 1993-10-29 | Taiyo Yuden Co Ltd | Manufacture of chip-type thermistor |
WO1997047017A1 (en) * | 1996-06-03 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing varistor |
WO2008142793A1 (en) * | 2007-05-24 | 2008-11-27 | Panasonic Corporation | Laminated ceramic electronic part and process for producing the same |
JP2020119935A (en) * | 2019-01-21 | 2020-08-06 | パナソニックIpマネジメント株式会社 | Multilayer varistor and manufacturing method thereof |
-
1985
- 1985-11-20 JP JP60262162A patent/JPS62122103A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01295403A (en) * | 1988-01-27 | 1989-11-29 | Murata Mfg Co Ltd | Chip varister |
JPH0468502A (en) * | 1990-07-09 | 1992-03-04 | Murata Mfg Co Ltd | Varistor and its manufacture |
JPH05283206A (en) * | 1992-03-30 | 1993-10-29 | Taiyo Yuden Co Ltd | Manufacture of chip-type thermistor |
WO1997047017A1 (en) * | 1996-06-03 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing varistor |
US6260258B1 (en) | 1996-06-03 | 2001-07-17 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing varistor |
WO2008142793A1 (en) * | 2007-05-24 | 2008-11-27 | Panasonic Corporation | Laminated ceramic electronic part and process for producing the same |
JP2020119935A (en) * | 2019-01-21 | 2020-08-06 | パナソニックIpマネジメント株式会社 | Multilayer varistor and manufacturing method thereof |
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