JPH05205908A - Manufacture of lamination type non-linear voltage resistor - Google Patents

Manufacture of lamination type non-linear voltage resistor

Info

Publication number
JPH05205908A
JPH05205908A JP4034222A JP3422292A JPH05205908A JP H05205908 A JPH05205908 A JP H05205908A JP 4034222 A JP4034222 A JP 4034222A JP 3422292 A JP3422292 A JP 3422292A JP H05205908 A JPH05205908 A JP H05205908A
Authority
JP
Japan
Prior art keywords
ceramic green
laminated
internal electrode
margin part
margin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4034222A
Other languages
Japanese (ja)
Other versions
JP2886724B2 (en
Inventor
Akihito Kondo
昭仁 近藤
Takamichi Momoki
孝道 桃木
Takeshi Suzuki
武志 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marcon Electronics Co Ltd
Original Assignee
Marcon Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Marcon Electronics Co Ltd filed Critical Marcon Electronics Co Ltd
Priority to JP4034222A priority Critical patent/JP2886724B2/en
Publication of JPH05205908A publication Critical patent/JPH05205908A/en
Application granted granted Critical
Publication of JP2886724B2 publication Critical patent/JP2886724B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Thermistors And Varistors (AREA)

Abstract

PURPOSE:To provide a lamination type non-linear voltage resistor in which the main cause for generation of delamination is eliminated and dampproof characteristics can be improved. CONSTITUTION:A margin part 2 is provided on three sides of the surface, and a slurry 4, having the composition same as a sheet 1, is printed in the thickness same as the inner electrode 3 on the margin part 2 of the ceramic green sheet 1 on which an inner electrode 3 is formed extending to the outer circumference of the side where the margin part 2 is not provided. Then, a plurality of ceramic green sheets 1 are press-bonded by lamination, integrally formed by sintering, and a laminated body, having no stepped part on the inner-electrode-3-formed part and the margin part 2, can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層体構成を改良した
積層型の非直線抵抗器(以下バリスタと称す)の製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a laminated non-linear resistor (hereinafter referred to as a varistor) having an improved laminated structure.

【0002】[0002]

【従来の技術】従来一般化している積層型のバリスタ
は、図5に示すように表面に一辺を外周辺まで延ばして
内部電極20を設け、他の三辺にマージン部21を設け
たバリスタ組成物からなるセラミックグリーンシート2
2を用い、図6に示すように前記内部電極20の外周辺
まで延びた一辺が交互に反対側になるよう前記セラミッ
クグリーンシート22を複数枚積層圧着し、しかる後焼
結一体化して積層体23を構成し、内部電極20の外周
辺まで延びた一辺、すなわち、内部電極の外部取り出し
電極部24以外を前記積層体23で囲まれた構造からな
るものである。
2. Description of the Related Art A conventional laminated varistor has a varistor composition in which one side is extended to the outer periphery and an internal electrode 20 is provided on the surface and a margin portion 21 is provided on the other three sides as shown in FIG. Ceramic green sheet 2
6, a plurality of the ceramic green sheets 22 are laminated and pressure-bonded so that one side extending to the outer periphery of the internal electrode 20 is alternately on the opposite side as shown in FIG. 23, and has a structure in which one side extending to the outer periphery of the internal electrode 20, that is, a portion other than the external extraction electrode portion 24 of the internal electrode is surrounded by the laminated body 23.

【0003】このような積層型のバリスタは、耐サージ
性に優れ、各種回路基板に表面実装ができることから実
用的価値が高く、今後その需要もますます高まるものと
考えられるし、品質の安定化が望まれる。
Such a laminated varistor has a high surge resistance and can be surface-mounted on various circuit boards, so that it has a high practical value, and it is considered that the demand thereof will further increase in the future, and the quality is stabilized. Is desired.

【0004】しかして、このような構成になる積層型の
バリスタにおいて、耐サージ性の向上を図るためには積
層枚数を増やさなければならないが、積層体23として
みた場合、内部電極20形成部分とマージン部21部分
に内部電極20厚み分だけ厚みの差があるため、図7に
示すように段差25が生じ、この段差25は、セラミッ
クグリーンシート22の積層枚数に比例して増大しす
る。その結果、セラミックグリーンシートの積層圧着時
の被圧力が内部電極20形成部分とマージン部分で相違
し、また焼結時の収縮歪みの相違により、バリスタ組成
物と内部電極20との間で層間剥離(デラミネーショ
ン)が発生し、耐湿特性劣化を引き起こす要因を抱える
結果となっていた。
Therefore, in the laminated varistor having such a structure, the number of laminated layers must be increased in order to improve the surge resistance, but in the case of the laminated body 23, the internal electrodes 20 are to be formed. Since the margin portion 21 has a thickness difference corresponding to the thickness of the internal electrode 20, a step 25 is formed as shown in FIG. 7, and the step 25 increases in proportion to the number of laminated ceramic green sheets 22. As a result, the pressure applied during lamination and compression of the ceramic green sheets differs between the internal electrode 20 forming portion and the margin portion, and due to the difference in shrinkage strain during sintering, delamination occurs between the varistor composition and the internal electrode 20. (Delamination) occurs, which results in having a factor that causes deterioration of moisture resistance characteristics.

【0005】[0005]

【発明が解決しようとする課題】以上述べたように、上
記構成になる積層型のバリスタは、内部電極を形成した
セラミックグリーンシートの積層によって生じる内部電
極形成部分とマージン部分の厚みの差に起因してデラミ
ネーションを引き起こす欠点をもっていた。
As described above, the laminated varistor having the above-described structure is caused by the difference in thickness between the internal electrode forming portion and the margin portion caused by the lamination of the ceramic green sheets having the internal electrodes formed thereon. And had the drawback of causing delamination.

【0006】本発明の目的は、積層枚数増大したとして
もデラミネーションの発生はなく、安定した特性を発揮
できる積層型電圧非直線抵抗器の製造方法を提供するこ
とである。
An object of the present invention is to provide a method of manufacturing a laminated voltage non-linear resistor which does not cause delamination even if the number of laminated layers is increased and exhibits stable characteristics.

【0007】[0007]

【課題を解決するための手段】本発明になる積層型電圧
非直線抵抗器の製造方法は、一表面の三辺にマージン部
を設け、このマージン部を設けない一辺の外周辺まで延
長し内部電極を形成したセラミックグリーンシートの前
記マージン部に前記シートと同成分のスラリーを前記内
部電極と同一厚さに印刷した後、前記内部電極の外周辺
まで延長した一辺が交互に反対側になるように前記セラ
ミックグリーンシートを複数枚積層し焼結一体化して得
た積層体の前記内部電極が露出した両側面に外部電極を
形成するものである。
According to the method of manufacturing a laminated voltage non-linear resistor according to the present invention, margins are provided on three sides of one surface, and the margins are not provided to extend to the outer periphery of one side and After printing a slurry having the same composition as the sheet with the same thickness as the internal electrode on the margin portion of the ceramic green sheet on which the electrode is formed, one side extending to the outer periphery of the internal electrode is alternately opposite sides. The external electrodes are formed on both side surfaces of the laminated body obtained by laminating a plurality of the ceramic green sheets and sintering and integrating them.

【0008】また、両面の三辺にマージン部を設けこの
マージン部を設けない両面間で反対側となる一辺の外周
辺まで延長し内部電極を形成したセラミックグリーンシ
ートの前記マージン部に前記シートと同成分のスラリー
を前記内部電極と同一厚さに印刷した後、前記セラミッ
クグリーンシートと内部電極を形成しないセラミックグ
リーンシートを交互に複数枚積層し焼結一体化して積層
体を得るものも含むものである。
Further, a margin is provided on three sides of both sides, and the margin is not provided on the opposite sides of the two sides. It also includes one in which a slurry of the same component is printed to the same thickness as the internal electrodes, and then a plurality of the ceramic green sheets and the ceramic green sheets without forming the internal electrodes are alternately laminated and sintered to obtain a laminated body. .

【0009】[0009]

【作用】セラミックグリーンシート表面の内部電極を形
成しないマージン部に、内部電極と同一厚さにセラミッ
クグリーンシートと同成分のスラリーを印刷しているた
め、このセラミックグリーンシートの積層数を多くして
も、内部電極形成部分とマージン部分に段差が生じるこ
となく、デラミネーションの発生要因を解消でき、高信
頼化に大きく貢献する作用を有する。
[Function] The margin of the surface of the ceramic green sheet where the internal electrode is not formed is printed with the slurry of the same component as the ceramic green sheet with the same thickness as the internal electrode. In addition, there is no step between the internal electrode formation portion and the margin portion, the delamination generation factor can be eliminated, and it has an effect of greatly contributing to high reliability.

【0010】[0010]

【実施例】以下、本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.

【0011】図2に示すように、焼結後にバリスタ機能
を有する原料として酸化亜鉛を主成分として、添加剤と
して酸化ビスマスとその他に酸化コバルト,酸化マンガ
ン,酸化ニッケル,酸化クロム,酸化マグネシウム,酸
化鉛,酸化アルミニウム,酸化チタン,酸化アンモニウ
ム,酸化バリウム,酸化硅素,酸化硼素などの中から2
種類又は3種類以上を加えボールミルで混合し、乾燥後
600〜950℃で仮焼し、しかる後、粉砕し有機バイ
ンダーとともに溶媒中に分散させスラリー状とする。
As shown in FIG. 2, zinc oxide is used as a main component having a varistor function after sintering, bismuth oxide as an additive, and cobalt oxide, manganese oxide, nickel oxide, chromium oxide, magnesium oxide, and oxides. 2 out of lead, aluminum oxide, titanium oxide, ammonium oxide, barium oxide, silicon oxide, boron oxide, etc.
One kind or three or more kinds are added, mixed in a ball mill, dried and calcined at 600 to 950 ° C., then pulverized and dispersed in a solvent together with an organic binder to form a slurry.

【0012】次にこれをドクターブレード法によって2
0μm〜100μm程度の均一なセラミックグリーンシ
ート1を形成する。しかして、次にこのセラミックグリ
ーンシート1の一表面の三辺にマージン部2を設け、こ
のマージン部2を設けない一辺の外周辺まで延長させ
金,白金,パラジウム,銀,銅,ニッケル又はこれらの
内の2つ以上の合金からなる金属ペーストをスクリーン
印刷して内部電極3を形成し、前記マージン部2に前記
シート1と同成分のスラリー4を前記内部電極3と同一
厚さに印刷した後、図3に示すように前記内部電極3の
外周辺まで延長した一辺が交互に反対側になるように前
記セラミックグリーンシート1を複数枚積層圧着し、し
かる後図1に示すように900〜1250℃で0.5〜
8時間焼結一体化して得た積層体5の前記内部電極3が
露出した両側面に銀ペーストを塗布し450〜850℃
で焼付けて外部電極6を形成してなるものである。
Next, this is 2 by the doctor blade method.
A uniform ceramic green sheet 1 having a thickness of 0 μm to 100 μm is formed. Then, next, a margin portion 2 is provided on three sides of one surface of the ceramic green sheet 1 and is extended to the outer periphery of one side where the margin portion 2 is not provided, gold, platinum, palladium, silver, copper, nickel, or these. Of the two or more of the above-mentioned alloys are screen-printed to form an internal electrode 3, and a slurry 4 having the same composition as that of the sheet 1 is printed on the margin 2 to the same thickness as the internal electrode 3. After that, as shown in FIG. 3, a plurality of the ceramic green sheets 1 are laminated and pressure-bonded so that one side extending to the outer periphery of the internal electrode 3 is alternately on the other side, and thereafter, as shown in FIG. 0.5 ~ 1250 ℃
A silver paste is applied to both side surfaces of the laminated body 5 obtained by sintering and integration for 8 hours where the internal electrodes 3 are exposed, and the temperature is 450 to 850 ° C.
The external electrode 6 is formed by baking.

【0013】以上のような構成になる積層型電圧非直線
抵抗器の製造方法によれば、セラミックグリーンシート
1表面の内部電極3を形成しないマージン部2に、内部
電極3と同一厚さにセラミックグリーンシート1と同成
分のスラリー4を印刷しているため、サージ耐量の向上
を目的として積層枚数を増したとしても、内部電極3と
マージン部2の厚さに段差が生じることなく、デラミネ
ーションの発生要因を解消でき、耐湿特性の優れた信頼
性に富む積層型電圧非直線抵抗器が得られる。
According to the method of manufacturing the laminated voltage non-linear resistor having the above-described structure, the ceramic green sheet 1 has the same thickness as the internal electrode 3 in the margin portion 2 where the internal electrode 3 is not formed. Since the slurry 4 having the same composition as that of the green sheet 1 is printed, even if the number of laminated layers is increased for the purpose of improving the surge resistance, there is no step in the thickness of the internal electrode 3 and the margin portion 2, and the delamination does not occur. It is possible to obtain a laminated type voltage non-linear resistor having excellent moisture resistance and excellent reliability, which can eliminate the cause of occurrence of the above.

【0014】次に本発明と従来例によって得られた積層
型電圧非直線抵抗器の特性比較について述べる。 (本発明A)セラミックグリーンシート及びマージン部
に印刷するスラリーは、ZnO(95.5モル%),C
oO(1モル%),MnO(1モル%),Cr2
3 (1モル%),Sb2 3 (1モル%),Bi2 3
(0.5モル%)の組成比からなり、内部電極として銀
パラジウム合金を用い、前記実施例にて述べた手段によ
ってセラミックグリーンシートを積層して製作した。
Next, a characteristic comparison between the laminated voltage non-linear resistors obtained by the present invention and the conventional example will be described. (Invention A) The slurry to be printed on the ceramic green sheet and the margin is made of ZnO (95.5 mol%), C
oO (1 mol%), MnO (1 mol%), Cr 2 O
3 (1 mol%), Sb 2 O 3 (1 mol%), Bi 2 O 3
The composition was (0.5 mol%), and the silver-palladium alloy was used as the internal electrode, and the ceramic green sheets were laminated by the means described in the above example.

【0015】(従来例B)マージン部にスラリーを印刷
する点を除き、セラミックグリーンシートの組成比、内
部電極材料及びセラミックグリーンシートの積層数など
は本発明Aと同一手段によって製作した。
(Prior Art Example B) The composition ratio of the ceramic green sheets, the internal electrode material and the number of laminated ceramic green sheets, etc. were manufactured by the same means as in the invention A except that the slurry was printed in the margin.

【0016】上記本発明Aと従来例Bの耐湿試験(DC
16V印加し、90〜98%RH下で、30℃から65
℃まで3時間かけて昇温し、65℃で6時間キープした
後、65℃から30℃まで3時間かけて降温する過程を
サイクルとし、このサイクルを1000時間の間繰返し
行う。)後における△Vの10%以上劣化の発生率を調
べた結果、表1に示すように本発明Aのものが従来例B
と比較して耐湿特性が著しく優れていた。
Moisture resistance test of the invention A and the conventional example B (DC
Apply 16V, 90 ~ 98% RH, from 30 ℃ to 65
The process of raising the temperature to 65 ° C over 3 hours, keeping at 65 ° C for 6 hours, and then lowering the temperature from 65 ° C to 30 ° C over 3 hours is a cycle, and this cycle is repeated for 1000 hours. As a result of investigating the occurrence rate of deterioration of ΔV by 10% or more after that, as shown in Table 1, the invention A is the conventional example B.
The moisture resistance was significantly better than that of

【0017】なお、試料は本発明A及び従来例Bとも1
0,000個である。
The sample of the present invention A and the conventional example B were both 1
It is 10,000.

【0018】[0018]

【表1】 [Table 1]

【0019】なお、上記実施例では、内部電極を一表面
に形成したセラミックグリーンシートを複数枚積層する
ものを例示して説明したが、図4に示すように両面の三
辺にマージン部7を設けこのマージン部7を設けない両
面間で反対側となる一辺の外周辺まで延長し内部電極8
を両面に形成したセラミックグリーンシート9を用い、
両面に形成したマージン部7に前記シート9と同成分の
スラリー10を前記内部電極8と同一厚さに印刷した
後、前記セラミックグリーンシート9と内部電極を形成
しないセラミックグリーンシート11を交互に複数枚積
層し、しかる後圧着し前記実施例にて述べたと同様の手
段で焼結一体化して積層体を得るようにしても同効であ
る。
In the above embodiment, the case where a plurality of ceramic green sheets having the internal electrodes formed on one surface thereof are laminated has been described as an example. However, as shown in FIG. 4, margin portions 7 are provided on three sides of both surfaces. Provided This margin portion 7 is not provided and extends to the outer periphery of one side opposite between both surfaces and the internal electrode 8 is provided.
Using the ceramic green sheet 9 formed on both sides,
After printing the slurry 10 having the same composition as the sheet 9 in the same thickness as the internal electrodes 8 on the margins 7 formed on both sides, a plurality of the ceramic green sheets 9 and the ceramic green sheets 11 without the internal electrodes are alternately formed. The same effect can be obtained by laminating the sheets, then pressing and then sintering and integrating them by the same means as described in the above embodiment to obtain a laminated body.

【0020】[0020]

【発明の効果】本発明によれば、積層体を構成する内部
電極形成部分とマージン部形成位置に段差が形成される
ことなく、デラミネーションの発生を防止できるため、
耐湿特性に優れた高信頼性の積層型電圧非直線抵抗器を
得られる積層型電圧非直線抵抗器の製造方法を提供でき
る。
According to the present invention, the occurrence of delamination can be prevented without forming a step between the internal electrode forming portion and the margin portion forming position forming the laminate.
It is possible to provide a method for manufacturing a laminated voltage non-linear resistor that can obtain a highly reliable laminated voltage non-linear resistor having excellent moisture resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例によって得られた積層型電圧
非直線抵抗器を示す断面図である。
FIG. 1 is a cross-sectional view showing a laminated voltage nonlinear resistor obtained according to an embodiment of the present invention.

【図2】本発明の一実施例による製造途中の内部電極を
形成したセラミックグリーンシートを示す斜視図であ
る。
FIG. 2 is a perspective view showing a ceramic green sheet on which an internal electrode is being manufactured according to an embodiment of the present invention.

【図3】本発明の一実施例による製造途中の焼結前積層
体を示す断面図である。
FIG. 3 is a cross-sectional view showing a pre-sintering laminate in the process of being manufactured according to an example of the present invention.

【図4】本発明の他の実施例による製造途中のセラミッ
クグリーンシートの積層状態を示す斜視図である。
FIG. 4 is a perspective view showing a laminated state of ceramic green sheets in the process of being manufactured according to another embodiment of the present invention.

【図5】従来例による製造途中の内部電極を形成したセ
ラミックグリーンシートを示す断面図である。
FIG. 5 is a cross-sectional view showing a ceramic green sheet on which internal electrodes are being manufactured according to a conventional example.

【図6】従来例による製造途中の積層体を示す断面図で
ある。
FIG. 6 is a cross-sectional view showing a laminate in the process of being manufactured according to a conventional example.

【図7】図6イ部拡大断面図である。FIG. 7 is an enlarged cross-sectional view of the portion a in FIG.

【符号の説明】[Explanation of symbols]

1 セラミックグリーンシート 2 マージン部 3 内部電極 4 スラリー 5 積層体 6 外部電極 7 マージン部 8 内部電極 9 セラミックグリーンシート 10 スラリー 11 セラミックグリーンシート 1 Ceramic Green Sheet 2 Margin Part 3 Internal Electrode 4 Slurry 5 Laminated Body 6 External Electrode 7 Margin Part 8 Internal Electrode 9 Ceramic Green Sheet 10 Slurry 11 Ceramic Green Sheet

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミックグリーンシート一表面の三辺
にマージン部を設けこのマージン部を設けない一辺の外
周辺まで延長し内部電極を形成する工程と、前記マージ
ン部に前記シートと同成分のスラリーを前記内部電極と
同一厚さに印刷する工程と、前記内部電極の外周辺まで
延長した一辺が交互に反対側に位置し、かつ前記内部電
極同士が接することなく前記セラミックグリーンシート
を複数枚積層し焼結一体化した積層体を得る工程と、こ
の積層体の前記内部電極が露出した両側面に外部電極を
形成する工程とを順次経ることを特徴とする積層型電圧
非直線抵抗器の製造方法。
1. A step of forming a margin part on three sides of one surface of a ceramic green sheet and extending to the outer periphery of one side without the margin part to form an internal electrode, and a slurry of the same component as the sheet in the margin part. A step of printing the same thickness as the internal electrode, and one side extending to the outer periphery of the internal electrode is alternately located on the opposite side, and a plurality of the ceramic green sheets are laminated without the internal electrodes contacting each other. Then, a laminated voltage non-linear resistor is manufactured by sequentially performing a step of obtaining a laminated body integrally sintered and a step of forming external electrodes on both side surfaces of the laminated body where the internal electrodes are exposed. Method.
【請求項2】 セラミックグリーンシート両面の三辺に
マージン部を設けこのマージン部を設けない両面間で反
対側となる一辺の外周辺まで延長し内部電極を形成する
工程と、前記マージン部に前記シートと同成分のスラリ
ーを前記内部電極と同一厚さに印刷する工程と、前記セ
ラミックグリーンシートと内部電極を形成しないセラミ
ックグリーンシートを交互に複数枚積層し焼結一体化し
た積層体を得る工程と、この積層体の前記内部電極が露
出した両側面に外部電極を形成する工程とを順次経るこ
とを特徴とする積層型電圧非直線抵抗器の製造方法。
2. A step of forming an internal electrode by extending a margin part on both sides of a ceramic green sheet and extending to the outer periphery of one side opposite to each other without the margin part, and forming the internal electrode on the margin part. A step of printing a slurry having the same composition as the sheet to the same thickness as the internal electrodes, and a step of alternately laminating a plurality of the ceramic green sheets and ceramic green sheets not forming the internal electrodes to obtain a laminated body which is sintered and integrated. And a step of sequentially forming external electrodes on both side surfaces of the laminated body where the internal electrodes are exposed, the method of manufacturing a laminated voltage non-linear resistor.
JP4034222A 1992-01-23 1992-01-23 Manufacturing method of laminated voltage non-linear resistor Expired - Lifetime JP2886724B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4034222A JP2886724B2 (en) 1992-01-23 1992-01-23 Manufacturing method of laminated voltage non-linear resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4034222A JP2886724B2 (en) 1992-01-23 1992-01-23 Manufacturing method of laminated voltage non-linear resistor

Publications (2)

Publication Number Publication Date
JPH05205908A true JPH05205908A (en) 1993-08-13
JP2886724B2 JP2886724B2 (en) 1999-04-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP4034222A Expired - Lifetime JP2886724B2 (en) 1992-01-23 1992-01-23 Manufacturing method of laminated voltage non-linear resistor

Country Status (1)

Country Link
JP (1) JP2886724B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210813A (en) * 2005-01-31 2006-08-10 Tdk Corp Process for manufacturing multilayer electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210813A (en) * 2005-01-31 2006-08-10 Tdk Corp Process for manufacturing multilayer electronic component

Also Published As

Publication number Publication date
JP2886724B2 (en) 1999-04-26

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