JPH0661223A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which the inclination of the irregular part can be reduced. CONSTITUTION:A wiring film 9 is formed at intervals on an insulating film 2 formed on a semiconductor substrate 1. The wiring film 9 is covered with an insulating film 8. A conductive film 3a is formed on an irregular part which is formed of the insulating film 8 and the insulating film 2. Source/drain regions 6, 7 are formed at intervals. A gate insulating film 4 is formed on the conductive film 3a and a gate electrode 5 is formed on the gate insulating film 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a step portion.

[0002]

2. Description of the Related Art A semiconductor device is an integrated circuit formed by laminating insulating films and conductive films of various shapes on a semiconductor substrate. FIG. 14 is a sectional view of a conventional semiconductor device. An insulating film 42 is formed on the semiconductor substrate 41. A wiring film 43 is formed on the insulating film 42 with a space therebetween, and the wiring film 43 is covered with an insulating film 44. Since the wiring film 43 is formed with a space provided between the wiring films 43, a step portion 45 is formed when a film is further formed thereon.

FIG. 15 shows a DRAM (Dynamic Random Acces) which is a kind of semiconductor memory device.
FIG. 6 is a cross-sectional view of the s Memory). The DRAM includes a memory cell area portion 52 and a peripheral circuit portion 53 on a semiconductor substrate 51.
It has and. 54 is a bit line, 55 is a storage node, 56 is a cell plate, and 57 is a gate electrode.
An interlayer insulating film 58 is formed between the cell plate 56 and the bit line 54. The bit line 54 is covered with an insulating film 59.

Since the memory cell area portion 52 has a multi-layered structure as compared with the peripheral circuit portion 53, the memory cell area portion 5
A step portion 45 is formed between the peripheral circuit portion 53 and the peripheral circuit portion 53.

[0005]

As described with reference to FIGS. 14 and 15, the step portion is inevitably generated in the semiconductor device. The step portion has various adverse effects on the manufacturing of the semiconductor device. For example, when a conductive film is formed and patterned into a predetermined shape using a photolithography technique and an etching technique, the conductive film may not be completely removed at the step portion and may remain as a residue. This residue causes a short circuit.

Further, when the resist is exposed by using the photoengraving technique, the margin of the depth of focus becomes small at the step portion, and the resist may not be sufficiently exposed at the step portion.

The present invention has been made to solve the above conventional problems. An object of the present invention is to provide a semiconductor device capable of reducing the inclination of the step portion.

[0008]

A semiconductor device according to the present invention includes a first portion and a second portion which is higher than the first portion.
An insulating film having a portion, a step portion connecting the first portion and the second portion, a conductive film formed on the step portion, and first and second sources formed on the conductive film with a space therebetween. / Drain region, a gate insulating film formed on a region between the first source / drain region and the second source / drain region, and a gate electrode formed on the gate insulating film.

[0009]

In the semiconductor device according to the present invention, the conductive film is formed on the step portion of the insulating film, and the first and second source / drain regions of the field effect transistor are formed on the conductive film. Since the conductive film is formed on the step portion of the insulating film, the step difference between the first portion and the second portion of the insulating film can be reduced.

Further, since the field effect transistor is formed in the step portion, the step portion can be effectively used.

[0011]

(First Embodiment) FIG. 1A is a sectional view of a semiconductor device according to a first embodiment of the present invention. Figure 1 (b)
FIG. 2 is a cross-sectional view of FIG. 1 (a) taken in the direction of arrow A. An insulating film 2 is formed on the semiconductor substrate 1.
A wiring film 9 is formed on the insulating film 2 with a space therebetween.
The wiring film 9 is covered with the insulating film 8.

A conductive film 3a is formed in the step portion formed by the insulating film 8 and the insulating film 2 to reduce the step. A gate insulating film 4 is formed on the conductive film 3a, and a gate electrode 5 is formed on the gate insulating film 4. Conductive film 3a
Source / drain regions 6 and 7 are formed with a space therebetween.

A method of manufacturing the first embodiment of the semiconductor device according to the present invention shown in FIG. 1 will be described below. FIG. 2 shows a state in which the wiring film 9 is formed on the insulating film 2 formed on the semiconductor substrate 1 with a space therebetween and the wiring film 9 is covered with the insulating film 8. Referring to FIG. 3, conductive film 3 made of polycrystalline silicon or the like is formed on the entire surface of semiconductor substrate 1 by the CVD method.

Referring to FIG. 4, conductive film 3 was removed by etching using reactive ion etching, leaving only the step portion. The conductive film 3 remaining on the step portion is called a conductive film 3a. Then, as shown in FIG. 1A, a gate insulating film 4 was formed on the entire surface of the semiconductor substrate 1, and then a gate electrode 5 was formed on the gate insulating film 4. Then, referring to FIG. 1B, ions are implanted into the conductive film 3a by using the gate electrode 5 as a mask, and
Drain regions 6 and 7 were formed. As described above, the manufacturing method of the first embodiment of the semiconductor device according to the present invention is completed. (Second Embodiment) FIG. 5 is a sectional view of a second embodiment of a semiconductor device according to the present invention. In the first embodiment shown in FIG. 1, the present invention is applied when the wiring film has a single layer structure, but in the second embodiment, the present invention is applied when the wiring film has a two-layer structure of the wiring films 9 and 10. is doing. The same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. (Third Embodiment) FIG. 6 is a sectional view of a semiconductor device according to a third embodiment of the present invention. In the first embodiment shown in FIG. 1A, the MOS field effect transistor is formed on both sides of the insulating film 8, but in the third embodiment, it is formed only on one side. The same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. (Fourth Embodiment) FIG. 7 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. The fourth embodiment applies the present invention to a DRAM. The semiconductor substrate 21 has a memory cell area portion 28 and a peripheral circuit portion 29. A field oxide film 22 separates the memory cell region 28 and the peripheral circuit 29.

The semiconductor substrate 21 is provided in the memory cell area 28.
Low concentration source / drain regions 25a, 2
5b is formed, and high-concentration source / drain regions 26a and 26b are further formed around it. A gate electrode 24a is formed on the region between the low concentration source / drain regions 25a and 25b via a gate insulating film. The gate electrode 24a is covered with an insulating film 28.

A storage node 30 is electrically connected to the high concentration source / drain regions 26b, a dielectric film 31 is formed on the storage node 30, and the dielectric film 31 is formed.
A cell plate 32 is formed on the top. On the other hand, the bit line 33 is electrically connected to the high concentration source / drain region 26a. Bit line 33 and cell plate 32
An inter-layer insulating film 23 is formed between and. The bit line 33 is covered with an interlayer insulating film 34. 24b is a word line.

In the peripheral circuit portion 29, the lightly doped source / drain regions 25 are formed in the semiconductor substrate 21 with a space therebetween.
a and 25b are formed, and high concentration source / drain regions 26a and 26b are further formed around them. A gate electrode 24c is formed on the region between the low concentration source / drain regions 25a and 25b via a gate insulating film.

Since the memory cell region portion 28 has a multilayered film stack as compared with the peripheral circuit portion 29, a step portion 38 is formed at the boundary between the memory cell region portion 28 and the peripheral circuit portion 29. A conductive film 35 having source / drain regions (not shown) formed at intervals is formed on the step portion 38. A gate insulating film 36 is formed on the conductive film 35,
A gate electrode 37 is formed on the gate insulating film 36. (Fifth Embodiment) FIG. 8 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. In the fifth embodiment, the step portion is intentionally formed in the insulating film, and the field effect transistor is formed in the step portion. Referring to FIG. 8, insulating film 17 is formed on semiconductor substrate 16. A step is intentionally formed in the insulating film 17 by etching. A conductive film 18a having source / drain regions separated from each other is formed in the step portion. A gate insulating film 19 is formed on the conductive film 18a, and a gate electrode 20 is formed on the gate insulating film 19. A method of manufacturing the semiconductor device according to the fifth embodiment of the present invention will be described below.

As shown in FIG. 9, a resist 15 was formed on the insulating film 17 formed on the semiconductor substrate 16, and the resist 15 was subjected to predetermined patterning. Then, using the resist 15 as a mask, a part of the insulating film 17 was partially removed by etching. As shown in FIG. 10, a conductive film 18 made of polycrystalline silicon or the like was formed by using the CVD method. Figure 11
Conductive film 1 using reactive ion etching as shown in
8 is removed, and the conductive film 18 is left only on the step portion. This conductive film is called a conductive film 18a.

Then, as shown in FIG. 8, a gate insulating film 19 was formed on the conductive film 18a, and a gate electrode 20 was formed on the gate insulating film 19. (Sixth Embodiment) FIG. 12 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention. In the fifth embodiment shown in FIG. 8, only one step portion is formed, but in the sixth embodiment many step portions are formed and the field effect transistor is formed therein. FIG. 13 is a plan view of FIG. Figure 8
The same parts as those indicated by the reference numerals are given the same reference numerals and the description thereof will be omitted.

[0021]

In the semiconductor device according to the present invention, since the conductive film is formed on the step portion of the insulating film, the step difference between the first portion and the second portion of the insulating film can be reduced. Therefore, it is possible to reduce the problems such as the generation of residues and the reduction in the depth of focus margin in lithography.

Further, in the semiconductor device according to the present invention, since the conductive film formed on the step portion is used as the source / drain region of the field effect transistor, the step portion can be effectively utilized, and the degree of integration of the semiconductor device can be increased. It becomes possible to improve.

[Brief description of drawings]

FIG. 1A is a sectional view of a first embodiment of a semiconductor device according to the present invention. (B) is sectional drawing of the state which cut | disconnected (a) from the arrow A direction.

FIG. 2 is a sectional view of a first step of a manufacturing method of the first example of the semiconductor device according to the present invention.

FIG. 3 is a sectional view of a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a third step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a second embodiment of a semiconductor device according to the present invention.

FIG. 6 is a sectional view of a third embodiment of a semiconductor device according to the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view of a first step of a method for manufacturing a semiconductor device according to a fifth exemplary embodiment of the present invention.

FIG. 10 is a sectional view of a second step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 11 is a sectional view of a third step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 12 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 13 is a plan view of a sixth embodiment of a semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view of an example of a conventional semiconductor device.

FIG. 15 is a cross-sectional view of another example of a conventional semiconductor device.

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film 3a conductive film 4 gate insulating film 5 gate electrode 6, 7 source / drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8728-4M H01L 27/10 325 R

Claims (1)

[Claims] 1. An insulating film having a first portion, a second portion higher than the first portion, and a step portion connecting the first portion and the second portion; A conductive film formed on the conductive film, first and second source / drain regions formed on the conductive film with a space, and a region between the first source / drain region and the second source / drain region. A semiconductor device comprising: a gate insulating film formed on the gate insulating film; and a gate electrode formed on the gate insulating film.