JP3259477B2 - Method of manufacturing dynamic RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-transistor, one-capacitor type memory cell, that is, a memory cell comprising a charge storage capacitor and an insulated gate field effect transistor for controlling charge input / output. Dynamic RAM (Dynamic Random Access Memory).
DRAM).

[0002]

2. Description of the Related Art FIG. 31 shows a circuit configuration of a one-transistor one-capacitor type memory cell provided in a DRAM.

In FIG. 31 , 1 is a word line for selecting a memory cell, 2 is a bit line forming a data transmission path, 3 is a capacitor for storing electric charge, and 4 is a counter electrode forming a capacitor 3 for storing electric charge. A plate voltage of a predetermined voltage, for example, a power supply voltage, a ground voltage, or a half of the power supply voltage is applied to the counter electrode 4.

Reference numeral 5 denotes an n-channel type MO for charge input / output control, the conduction and non-conduction of which is controlled via the word line 1.
An SFET (hereinafter, referred to as an nMOS transistor), and 5S and 5D indicate a source electrode and a drain electrode which are controlled electrodes of the nMOS transistor 5, respectively.

FIGS. 32 to 37 are schematic cross-sectional views for explaining an example of a conventional DRAM manufacturing method, showing the process of forming the memory cell shown in FIG. Shows a stage in which a polysilicon layer (polycrystalline silicon layer) for forming the counter electrode 4 constituting the capacitor 3 is formed.

In FIG . 32, reference numeral 6 denotes a P-type silicon substrate (P-Su).
b), 7 to 9 are N-type diffusion layers, 10 and 11 are gate insulating films made of SiO ₂ , 12 is a word line adjacent to the word line 1, 13 and 14 are SiO ₂ layers forming an interlayer insulating film, Reference numeral 15 denotes a polysilicon layer for forming the counter electrode 4.

Here, the N-type diffusion layers 7 and 8, the gate insulating film 10, and the word line 1, the N-type diffusion layer 7 is a drain electrode 5 D, the N-type diffusion layer 8 is a source electrode 5 S, N for controlling charge input / output with the gate electrode serving as a control electrode
The MOS transistor 5 is configured.

The N-type diffusion layers 8 and 9, the gate insulating film 11, and the word line 12 are connected to the N-type diffusion layer 8 as a source electrode, the N-type diffusion layer 9 as a drain electrode, and the word line 12 as a gate electrode. An nMOS transistor for charge input / output control adjacent to the nMOS transistor 5 for charge input / output control is configured.

In the conventional method of manufacturing a DRAM, next, as shown in FIG. 33, an N-type impurity, for example, phosphorus P is ion-implanted over the entire surface of the polysilicon layer 15 to lower the resistance of the polysilicon layer 15. To form a counter electrode 4,
The counter electrode 4, the SiO ₂ layer 14, and the N-type diffusion layer 7 constitute the charge storage capacitor 3.

Next, as shown in FIG.
A portion of each of the SiO ₂ layers 14 and 13 is removed by etching, a contact hole 16 is formed, and a portion of the N-type diffusion layer 8 is exposed.

Next, as shown in FIG. 35, a SiO ₂ layer 17 is formed as an insulating film on the entire surface, and thereafter, as shown in FIG. 36, a part of the SiO ₂ layer 17 is removed by etching to form a contact hole. 18 is formed, again exposing a part of the N-type diffusion layer 8.

Next, as shown in FIG. 37, a bit line 2 made of an aluminum layer is formed, and connection between the bit line 2 and the N-type diffusion layer 8 (source electrode 5S of the nMOS transistor 5) is achieved. The memory cell shown at 31 is formed.

[0013]

After forming the counter electrode 4 as shown in FIG . 33 , the counter electrode 4 is formed as shown in FIG.
When the contact hole 16 penetrating through the SiO ₂ layers 14 and 13 is formed, the contact hole 16 may not be formed due to an etching mistake.

[0014] In this case, SiO ₂ as shown in FIG. 35 Tier 1
When the contact hole 18 is formed as shown in FIG. 36 after the formation of the gate electrode 7, a part 4A of the upper surface of the counter electrode 4 is exposed as shown in FIG.
Is formed, as shown in FIG. 39, the bit line 2 and the counter electrode 4 are short-circuited (short-circuited), and the voltage of the counter electrode 4 becomes unstable.

Since the common electrode 4 is formed in common for a plurality of memory cells, for example,
And the nMOS transistor 5 for controlling charge input / output, even if the memory cell is rescued by a redundant cell, the memory data may be destroyed in other memory cells, which improves the yield. It was a factor that hindered.

Accordingly, the present invention solves the above problem and improves the yield.
An object of the present invention is to provide a method for manufacturing an AM.

[0017]

According to the present invention, there is provided a charge storage capacitor and a charge input / output control insulated gate field effect transistor.
The insulated gate field effect transistor for charge input / output control is configured to include a counter electrode formed above the first controlled electrode of the insulated gate field effect transistor for charge input / output. An object of the present invention is to improve a method of manufacturing a DRAM provided with a memory cell in which a control electrode is used and a second controlled electrode is connected to a bit line . Each of the inventions described above can be achieved.

According to a first aspect of the present invention, there is provided a step of forming a conductive layer serving as a counter electrode over the entire surface of an insulated gate field effect transistor for controlling charge input / output, and forming a bit line and a charge input / output forming an insulating layer which is not removed in the etching step performed when forming a contact hole to achieve a connection with the second controlled electrode of the insulated gate field effect transistor for controlling the contact holes
Removing the insulating layer and the conductive layer in a region where the hole is opened
And forming the contact hole
Process .

According to a second aspect of the invention , after a conductive layer serving as a counter electrode is formed above an insulated gate field effect transistor for controlling charge input / output, a bit line and a charge input / output control are formed on the upper surface of the conductive layer. Forming an insulating layer that is not removed by an etching step performed when forming a contact hole for connecting to a second controlled electrode of the insulated gate field effect transistor, and then forming the insulating layer and the conductive layer Is etched into a desired shape to form a counter electrode, and a contact hole for connecting the bit line to the second controlled electrode of the insulated gate field effect transistor for controlling charge input / output is formed on a side surface of the counter electrode. Forming an insulating layer which is not removed by an etching step performed when forming the second gate electrode and the second gate insulating field-effect transistor for controlling charge input / output; Include the step of forming a contact hole in order to connect the electrodes, is that.

[0020]

In the first aspect, a step of forming a conductive layer serving as a counter electrode over the entire surface above an insulated gate field effect transistor for controlling charge input / output, and
Including a step of forming an insulating layer that is not removed by an etching step performed when forming a contact hole for connecting a bit line and a second controlled electrode of an insulated gate field effect transistor for charge input / output control I have.

As a result, a part of the insulating layer formed on the upper surface of the opposing electrode, a part of the opposing electrode, and the like are thereafter removed by etching, so that the bit line and the second insulated gate field effect transistor for controlling charge input / output are removed. When forming a contact hole to connect to the controlled electrode,
When there is a mistake and a memory cell portion in which the contact hole cannot be formed occurs, the bit line and the second controlled electrode of the insulated gate field effect transistor for controlling the charge input / output are connected. Even if a contact hole for making a connection is formed and a bit line is formed, in the memory cell portion where an etching error has occurred, the bit line contacts the insulating layer formed on the upper surface of the counter electrode, There is no contact with the counter electrode.

Therefore, according to the first aspect, the stability of the voltage of the common electrode can be ensured, and the destruction of the stored data can be avoided, so that the yield can be improved.

According to the second aspect of the present invention , after a conductive layer serving as a counter electrode is formed above an insulated gate field effect transistor for controlling charge input / output, a bit line and a charge input are formed on the upper surface of the conductive layer. Forming an insulating layer which is not removed in an etching step performed when forming a contact hole for connecting to a second controlled electrode of an insulated gate field effect transistor for output control; subsequently, the insulating layer; The conductive layer is etched into a desired shape to form a counter electrode, and a bit line and a second insulated gate field effect transistor for controlling charge input / output are formed on side surfaces of the counter electrode.
Forming an insulating layer which is not removed in an etching step performed when forming a contact hole for connection with a controlled electrode of the second embodiment, and a second controlled layer of an insulated gate field effect transistor for controlling bit lines and charge input / output. It includes a step of forming a contact hole for connection with an electrode.

As a result, a part of the insulating layer formed on the upper surface of the opposing electrode, a part of the opposing electrode, and the like are thereafter removed by etching, so that the bit line and the second insulated gate field effect transistor for controlling charge input / output are removed. When forming a contact hole to connect to the controlled electrode,
If there is a mistake and a memory cell part in which the contact hole cannot be formed occurs, or if a memory cell part or a contact hole in which a sufficiently large contact hole is not formed is misaligned. In the case where the resulting memory cell portion occurs, a contact hole for connecting the bit line to the second controlled electrode of the insulated gate field effect transistor for controlling charge input / output is formed, Even if a line is formed, the bit line contacts the insulating layer formed on the upper surface of the counter electrode but does not contact the counter electrode in the memory cell portion where the etching error has occurred.

Therefore, according to the second invention ,
Since the stability of the voltage of the common electrode can be ensured and the destruction of the stored data can be avoided, the yield can be improved.

[0026]

EXAMPLES Hereinafter, with reference to FIGS. 1 to 30, Reference Examples arrangement
Next, a first embodiment and a second embodiment of the present invention will be described. 30. In FIGS. 1 to 30, the portions corresponding to FIGS. 31 to 39 are denoted by the same reference numerals, and the description thereof will not be repeated.

Reference Example FIGS. 1 to 8 FIGS. 1 to 6 are schematic cross-sectional views for explaining a reference example of a method of manufacturing a DRAM . During the entire process, the memory cell shown in FIG. The step of forming is shown, and conventionally known steps are executed for other portions.

FIG . 1 shows a stage in which a polysilicon layer 15 for forming the counter electrode 4 constituting the capacitor 3 is formed by performing a conventionally well-known process, which is the same as that shown in FIG. is there.

In the reference example , next, as shown in FIG. 2, a region where a contact hole 18 to be described later is to be formed, which is finally formed in order to connect the bit line 2 and the N-type diffusion layer 8. A resist 20 is formed on 19.

Then, using the resist 20 as a mask, an N-type impurity, for example,
Phosphorus P is ion-implanted, and a portion of the polysilicon layer 15 other than the portion 15A covered with the resist 20 is reduced in resistance to form the counter electrode 4, and the counter electrode 4 and the SiO ₂ layer 1 are formed.
4 and the N-type diffusion layer 7 constitute the capacitor 3 for charge storage.

Next, the polysilicon layer 15A, the counter electrode 4
, And a part of the SiO ₂ layers 13 and 14 are removed by etching to form a contact hole 16 and expose a part of the N-type diffusion layer 8 as shown in FIG.

Next, as shown in FIG. 4, a SiO ₂ layer 17 is formed as an insulating film on the entire surface, and then, as shown in FIG. 5, a part of the SiO ₂ layer 17 is removed by etching to form a contact hole. 18 is formed, and a part of the N-type diffusion layer 8 is exposed again.

Next, as shown in FIG. 6, a bit line 2 made of an aluminum layer is formed, and connection between the bit line 2 and the N-type diffusion layer 8 (source electrode 5S of the nMOS transistor 5) is made. Is formed.

As described above, in the reference example , among the polysilicon layers 15 shown in FIG. 1, as shown in FIG. 2, the polysilicon layers 15 are finally formed in order to connect the bit lines 2 and the N-type diffusion layers 8. The portion 15A to be the contact hole 18 to be formed is not reduced in resistance but remains as a high-resistance layer.

As a result, after forming the counter electrode 4 as shown in FIG. 2, the polysilicon layer 15A, as shown in FIG.
When a part of the counter electrode 4 and a part of the SiO ₂ layers 14 and 13 are removed by etching to form a contact hole 16,
Even if the contact hole 16 cannot be formed due to an etching mistake, if the contact hole 18 is formed as shown in FIG. 5 after forming the SiO ₂ layer 17 as shown in FIG. As shown in FIG. 7, the upper surface of the counter electrode 4 is not exposed, and only the upper surface 15B of the high-resistance polysilicon layer 15A is exposed. Even if the bit line 2 is formed as it is, as shown in FIG. In addition, a short circuit between the bit line 2 and the counter electrode 4 can be avoided.

Therefore, according to this reference example , in the step of forming the contact hole 16,
Even when the contact hole 16 cannot be formed due to a mistake, the stability of the voltage of the counter electrode 4 can be ensured, and the destruction of the stored data can be avoided, so that the yield can be improved.

In this embodiment , as shown in FIG. 2, a contact hole 18 finally formed in the polysilicon layer 15 for connecting the bit line 2 and the N-type diffusion layer 8 is formed. The portion 15A to be formed remains as a high-resistance layer. However, when a portion wider than this portion 15A is left as a high-resistance layer, when the contact hole 18 is formed, the position of the contact hole 18 is shifted. In this case, the short circuit between the bit line 2 and the counter electrode 4 can be avoided.

[0038] (First Embodiment ... FIGS. 9 17) 9 to 15 the first method of manufacturing a DRAM according to the present invention
FIG. 32 is a schematic cross-sectional view for explaining the embodiment , showing a process of forming the memory cell shown in FIG. 31 in all processes, and a conventionally well-known process is executed for other portions.

FIG . 9 shows a stage in which a polysilicon layer 15 for forming the counter electrode 4 constituting the capacitor 3 is formed by performing a conventionally well-known process, which is the same as that shown in FIG. is there.

In the first embodiment , next, as shown in FIG. 10, an N-type impurity, for example, phosphorus P is ion-implanted into the entire surface of the polysilicon layer 15 to lower the resistance of the polysilicon layer 15 to oppose it. An electrode 4 is formed, and a counter electrode 4 and SiO ₂
The capacitor 3 for storing electric charge is composed of the layer 14 and the N-type diffusion layer 7.
Is configured.

Next, as shown in FIG. 11, after forming a Si ₃ N ₄ layer 21 as an insulating film on the upper surface of the counter electrode 4, FIG.
As shown in FIG. 2, the Si ₃ N ₄ layer 21, the counter electrode 4 and the SiO 2
A part of the _two layers 14 and 13 is removed by etching, a contact hole 16 is formed, and a part of the N-type diffusion layer 8 is exposed.

Next, as shown in FIG. 13, an SiO ₂ layer 17 is formed as an insulating film on the entire surface, and then, as shown in FIG. 14, a part of the SiO ₂ layer 17 is removed by etching.
A contact hole 18 is formed, and a part of the N-type diffusion layer 8 is exposed again.

Next, as shown in FIG. 15, a bit line 2 made of an aluminum layer is formed, and connection between the bit line 2 and the N-type diffusion layer 8 (source electrode 5S of the nMOS transistor 5) is made. Is formed.

As described above, in the first embodiment , FIG.
After forming the counter electrode 4 as shown in FIG. 0, a Si ₃ N ₄ layer 21 is formed on the upper surface of the counter electrode 4 as shown in FIG.

As a result, as shown in FIG. 12, when the Si ₃ N ₄ layer 21, the counter electrode 4 and the SiO ₂ layers 14 and 13 are partially removed by etching to form the contact holes 16, an etching mistake may occur. Even if the contact hole 16 cannot be formed in some cases, when the SiO ₂ layer 17 is formed as shown in FIG. 13 and then the contact hole 18 is formed as shown in FIG. As described above, the upper surface of the counter electrode 4 is not exposed, and only the portion 21A of the upper surface of the Si ₃ N ₄ layer 21 is exposed. Even if the bit line 2 is formed as it is,
As shown in FIG. 17, a short circuit between the bit line 2 and the counter electrode 4 can be avoided.

Therefore, according to the first embodiment , in the step of forming the contact hole 16,
Even when the contact hole 16 cannot be formed due to a mistake, the stability of the voltage of the counter electrode 4 can be ensured, and the destruction of the stored data can be avoided, so that the yield can be improved.

[0047] (Second Embodiment ... view 18 to 30) FIGS. 18 25 the method of manufacturing a DRAM according to the invention first
FIG. 32 is a schematic cross-sectional view for explaining the second embodiment , showing a process of forming the memory cell shown in FIG. 31 in all processes, and a conventionally well-known process is executed for other portions.

FIG . 18 shows a stage in which a polysilicon layer 15 for forming the counter electrode 4 forming the capacitor 3 is formed by performing a conventionally well-known process, which is the same as that shown in FIG. is there.

In the second embodiment , next, as shown in FIG. 19, an N-type impurity, for example, phosphorus P is ion-implanted into the entire surface of the polysilicon layer 15 to lower the resistance of the polysilicon layer 15 so as to oppose each other. An electrode 4 is formed, and a counter electrode 4 and SiO ₂
The capacitor 3 for storing electric charge is composed of the layer 14 and the N-type diffusion layer 7.
To form

Next, as shown in FIG. 20, after forming a Si ₃ N ₄ layer 21 as an insulating film on the upper surface of the counter electrode 4, FIG.
As shown in FIG. 1, the Si ₃ N ₄ layer 21, the counter electrode 4 and the SiO 2
A part of the _two layers 14 and 13 is removed by etching, a contact hole 16 is formed, and a part of the N-type diffusion layer 8 is exposed.

Next, as shown in FIG. 22, after forming a Si ₃ N ₄ layer 22 on the contact hole surface of the counter electrode 4, as shown in FIG. 23, an SiO ₂ layer 17 is formed as an insulating film on the entire surface. Then, as shown in FIG. 24, a part of the SiO ₂ layer 17 is removed by etching, and the contact hole 18 is removed.
Is formed, and a part of the N-type diffusion layer 8 is exposed again.

Next, as shown in FIG. 25, a bit line 2 made of an aluminum layer is formed, and connection between the bit line 2 and the N-type diffusion layer 8 (source electrode 5S of the nMOS transistor 5) is made. The memory cell shown in FIG.

As described above, in the second embodiment , FIG.
After forming the counter electrode 4 as shown in FIG. 9, a Si ₃ N ₄ layer 21 is formed on the upper surface of the counter electrode 4 as shown in FIG.

As a result, as shown in FIG. 21, when each of the Si ₃ N ₄ layer 21, the counter electrode 4 and the SiO ₂ layers 14, 13 is partly removed by etching to form the contact hole 16, an etching mistake occurs. Even if the contact hole 16 cannot be formed in some cases, after forming the SiO ₂ layer 17 as shown in FIG. 23 and then forming the contact hole 18 as shown in FIG. As described above, the upper surface of the counter electrode 4 is not exposed, and only the portion 21A of the upper surface of the Si ₃ N ₄ layer 21 is exposed. Even if the bit line 2 is formed as it is,
As shown in FIG. 27, a short circuit between the bit line 2 and the counter electrode 4 can be avoided.

[0055] Therefore, also the second embodiment, in the step of forming the contact hole 16 by etching miss, when it was not possible to form a contact hole 16 is also the stability of the voltage of the counter electrode 4 As a result, the storage data can be prevented from being destroyed, so that the yield can be improved.

Further, in the second embodiment , FIG.
When forming the contact hole 16 as shown in FIG.
As shown in FIG. 28, a sufficiently large contact hole 1
29, the Si ₃ N ₄ layer 22 is formed on the contact hole surface of the counter electrode 4 as shown in FIG.
As shown in FIG. 30, bit line 2 and N-type diffusion layer 8 (source electrode 5 of nMOS transistor 5) are formed as shown in FIG.
When the connection with S) is intended, short-circuit between the bit line 2 and the counter electrode 4 can be avoided. Contact hole 1
The same applies to the case where a positional shift has occurred in No. 6.

As described above, according to the second embodiment , in the step of forming the contact hole 18, if the contact hole 16 having a sufficient size is not formed, or the contact hole 16 is displaced. Also in this case, the stability of the voltage of the counter electrode 4 can be ensured and the destruction of the stored data can be avoided, so that the yield can be improved from this point as well.

[0058]

According to the first aspect of the present invention , above the insulated gate field effect transistor for controlling charge input / output.
A step of forming a conductive layer serving as a counter electrode on the entire surface, and a contact hole for connecting a bit line and a second controlled electrode of an insulated gate field effect transistor for controlling charge input / output on the upper surface of the conductive layer By forming a step of forming an insulating layer that is not removed in the etching step performed when forming, a portion of the insulating layer formed on the upper surface of the counter electrode, a portion of the counter electrode and the like are then removed by etching, When forming a contact hole for connecting a bit line and a second controlled electrode of an insulated gate field effect transistor for controlling charge input / output, etching and etching are performed.
Even if there is a mistake and there is a memory cell part in which the contact hole cannot be formed, in this memory cell part, the bit line is in contact with the insulating layer formed on the upper surface of the counter electrode. No contact is made with the counter electrode. As a result, the stability of the voltage of the counter electrode can be ensured, and the destruction of the stored data can be avoided, so that the yield can be improved.

According to the second aspect of the present invention , after a conductive layer serving as a counter electrode is formed above an insulated gate field effect transistor for controlling charge input / output, an upper surface of the conductive layer is formed on the conductive layer.
Forming an insulating layer that is not removed by an etching step performed when forming a contact hole for connecting a bit line and a second controlled electrode of an insulated gate field effect transistor for controlling charge input / output; The insulating layer and the conductive layer are etched into a desired shape to form a counter electrode, and a bit line and a second controlled electrode of an insulated gate field effect transistor for controlling charge input / output are formed on side surfaces of the counter electrode. Forming an insulating layer that is not removed in an etching step performed when forming a contact hole for connection with a bit line, and connecting the bit line to a second controlled electrode of an insulated gate field effect transistor for controlling charge input / output; Then, a part of the insulating layer formed on the upper surface of the opposing electrode, Such as the etching removal of part,
When forming a contact hole for connecting the bit line and the second controlled electrode of the insulated gate field effect transistor for charge input / output control, there is an etching mistake,
Even if a memory cell portion in which the contact hole cannot be formed occurs, a displacement occurs in the memory cell portion or the contact hole in which a sufficiently large contact hole is not formed. Even if the memory cell part
A memory in which a contact hole formation error has occurred even if a contact hole is formed to connect a bit line and a second controlled electrode of an insulated gate field effect transistor for controlling charge input / output, and a bit line is formed. In the cell portion, the bit line contacts the insulating layer formed on the upper surface of the counter electrode but does not contact the counter electrode, and as a result, the voltage stability of the counter electrode can be ensured. Since the destruction of the stored data can be avoided, the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for describing a reference example of a method for manufacturing a DRAM .

FIG. 2 is a schematic cross-sectional view for describing a reference example of a method for manufacturing a DRAM .

FIG. 3 is a schematic cross-sectional view for describing a reference example of a method for manufacturing a DRAM .

FIG. 4 is a schematic cross-sectional view for describing a reference example of a method for manufacturing a DRAM .

FIG. 5 is a schematic cross-sectional view for describing a reference example of a method for manufacturing a DRAM .

FIG. 6 is a schematic cross-sectional view for describing a reference example of a method for manufacturing a DRAM .

FIG. 7 is a schematic cross-sectional view for explaining the effect of the reference example of the DRAM manufacturing method .

FIG. 8 is a schematic cross-sectional view for explaining the effect of the reference example of the DRAM manufacturing method .

FIG. 9 is a schematic cross-sectional view for explaining a first embodiment of a method for manufacturing a DRAM according to the present invention.

FIG. 10 is a first embodiment of a DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 11 is a first embodiment of a method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 12 is a first embodiment of a method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 13 is a first embodiment of a method of manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 14 is a first embodiment of a method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 15 is a first embodiment of a method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 16 is a first embodiment of a method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 17 is a first embodiment of a DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 18 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 19 shows a second embodiment of a method for manufacturing a DRAM according to the present invention.
It is a schematic sectional drawing for explaining an example .

FIG. 20 is a second embodiment of the method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 21 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 22 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 23 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 24 is a second embodiment of the method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 25 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for explaining an example .

FIG. 26 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 27 is a second embodiment of the method for manufacturing a DRAM according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 28 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 29 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 30 is a second embodiment of the DRAM manufacturing method according to the present invention;
It is a schematic sectional drawing for demonstrating the effect of an example .

FIG. 31 is a circuit diagram showing a one-transistor one-capacitor type memory cell.

FIG. 32 is a schematic cross-sectional view for explaining an example of a conventional DRAM manufacturing method.

FIG. 33 is a schematic cross-sectional view for explaining an example of a conventional DRAM manufacturing method.

FIG. 34 is a schematic cross-sectional view for explaining an example of a conventional DRAM manufacturing method.

FIG. 35 is a schematic cross-sectional view for explaining an example of a conventional DRAM manufacturing method.

FIG. 36 is a schematic cross-sectional view for explaining an example of a conventional DRAM manufacturing method.

FIG. 37 is a schematic cross-sectional view for explaining an example of a conventional DRAM manufacturing method.

FIG. 38 is a schematic cross-sectional view for describing a problem of a conventional DRAM manufacturing method.

FIG. 39 is a schematic cross-sectional view for describing a problem of a conventional DRAM manufacturing method.

[Explanation of symbols]

 2 bit line 4 counter electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 27/108

Claims (5)

(57) [Claims] 1. An insulated gate field effect transistor for charge storage and charge input / output control, said capacitor being located above a first controlled electrode of said insulated gate field effect transistor. The insulated gate field effect transistor includes a formed counter electrode. The insulated gate field effect transistor includes a memory cell having a word line as a control electrode and a second controlled electrode connected to a bit line. Forming a conductive layer serving as a counter electrode over the entire upper surface of the insulated gate field effect transistor; and forming the bit line and the insulated gate field effect transistor on an upper surface of the conductive layer. forming an insulating layer which is not removed in the etching step performed when forming a contact hole to achieve a connection with the second controlled electrode, before The insulating layer in the area where the contact hole is opened,
A method for manufacturing a dynamic RAM , comprising a step of processing to remove the conductive layer and a step of forming the contact hole . 2. An insulated gate field effect transistor for charge storage and charge input / output control, said capacitor being located above a first controlled electrode of said insulated gate field effect transistor. The insulated gate field effect transistor includes a formed counter electrode. The insulated gate field effect transistor includes a memory cell having a word line as a control electrode and a second controlled electrode connected to a bit line. Forming a conductive layer serving as a counter electrode above the insulated gate field effect transistor, and then forming the bit line and a second of the insulated gate field effect transistor on an upper surface of the conductive layer. Forming an insulating layer which is not removed in an etching step performed when forming a contact hole for connection with a controlled electrode; And a contact hole for forming a counter electrode by etching the conductive layer into a desired shape, and connecting the bit line to the second controlled electrode of the insulated gate field effect transistor on a side surface of the counter electrode. Forming an insulating layer that is not removed in an etching step performed when forming a contact hole, and forming a contact hole for connecting the bit line to a second controlled electrode of the insulated gate field effect transistor. A method for manufacturing a dynamic RAM, comprising: 3. An insulating layer which is not removed in an etching step performed when forming a contact hole for connecting the bit line and a second controlled electrode of the insulated gate field effect transistor is a silicon nitride film. 3. The method for manufacturing a dynamic RAM according to claim 1, wherein: 4. A capacitor for charge storage and an insulated gate field effect transistor for charge input / output control, wherein said capacitor is located above a first controlled electrode of said insulated gate field effect transistor. The insulated gate field effect transistor includes a formed counter electrode. The insulated gate field effect transistor includes a memory cell having a word line as a control electrode and a second controlled electrode connected to a bit line. A first insulating film covering the capacitor, a contact window formed in the first insulating film and opened to the second controlled electrode, and the second insulating film is formed through the contact window. has a bit line connected to the control electrode, the upper surface of the counter electrode, the first insulating film being different from the second insulating film is formed etching characteristics, the first insulating film A silicon oxide film, the second
A dynamic RAM, wherein the insulating film is a silicon nitride film . 5. The dynamic RAM according to claim 4, wherein said second insulating film is further formed on a side surface of said counter electrode.