JPH0794599A - Semiconductor memory and fabrication thereof - Google Patents
Semiconductor memory and fabrication thereofInfo
- Publication number
- JPH0794599A JPH0794599A JP5259326A JP25932693A JPH0794599A JP H0794599 A JPH0794599 A JP H0794599A JP 5259326 A JP5259326 A JP 5259326A JP 25932693 A JP25932693 A JP 25932693A JP H0794599 A JPH0794599 A JP H0794599A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- capacitor
- electrode
- semiconductor memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000010354 integration Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体記憶装置及びその
製造方法に関し、特にスタック型容量を有する半導体記
憶装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having a stack type capacitor and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体記憶装置は、年々高集積化が進ん
でいる。高集積化を実現するためにキャパシタ構造は、
より小さな面積でより大きな容量値を得るために、平面
的な構造から立体的な構造が使われるようになり、その
中でスタック型容量と呼ばれるものがある。従来の半導
体記憶装置及びその製造方法は、例えばＩＥＥＥ Ｔｒ
ａｎｓａｃｔｉｏｎｓ ｏｎ Ｅｌｅｃｔｒｏｎ Ｄｅ
ｖｉｃｅｓ，ＶＯＬ，ＥＤ−２７，Ｎｏ．８，Ａｕｇ
１９８０，Ｐ．１５９６〜１６０１に示すようなものが
ある。2. Description of the Related Art Semiconductor memory devices have been highly integrated year by year. To achieve high integration, the capacitor structure is
In order to obtain a larger capacitance value in a smaller area, a three-dimensional structure has been used instead of a planar structure, and there is one called a stack type capacitor. A conventional semiconductor memory device and its manufacturing method are disclosed in, for example, IEEE Tr
transactions on Electron De
Vices, VOL, ED-27, No. 8, Aug
1980, p. 1596 to 1601.
【０００３】すなわち、図７及び図８に示すように、Ｐ
型シリコン基板１にフィールド酸化膜２を形成し、ゲー
ト酸化膜３、第一のポリシリコン膜を順次成長させ、リ
ソグラフィー技術を用いて、第一のポリシリコン膜から
なるワード線（ゲート電極）４をパターニングし、パタ
ーニングされたワード線４とフィールド酸化膜２をマス
クとしてＮ型不純物イオン（例えばＰなど）をイオン注
入してＮ＋ 型拡散層５を形成し、第一の層間絶縁膜６
を形成する。つづいてＮ＋ 型拡散層５と下部容量電極
８とを接続するための容量コンタクト７を開孔して、第
二のポリシリコン膜を膜厚４０００〜５０００Åで全面
に形成し、パターニングすることにより、下部容量電極
８を形成し、下部容量電極８を覆うように、容量絶縁膜
９を膜厚８０〜１００Åで形成し、さらに容量絶縁膜９
を覆うように上部容量電極１０を形成する。つづいて第
二の層間絶縁膜１１を形成して、ビット線コンタクト１
２を形成し、最後にビット線１３を形成する。That is, as shown in FIGS. 7 and 8, P
A field oxide film 2 is formed on a silicon substrate 1, a gate oxide film 3 and a first polysilicon film are sequentially grown, and a word line (gate electrode) 4 made of the first polysilicon film 4 is formed by using a lithography technique. Is patterned, N-type impurity ions (for example, P) are ion-implanted using the patterned word line 4 and field oxide film 2 as a mask to form an N + -type diffusion layer 5, and a first interlayer insulating film 6 is formed.
To form. Subsequently, a capacitor contact 7 for connecting the N + type diffusion layer 5 and the lower capacitor electrode 8 is opened, a second polysilicon film is formed on the entire surface with a film thickness of 4000 to 5000 Å, and patterned. , The lower capacitor electrode 8 is formed, and the capacitor insulating film 9 is formed to have a film thickness of 80 to 100 Å so as to cover the lower capacitor electrode 8.
The upper capacitance electrode 10 is formed so as to cover the. Subsequently, the second interlayer insulating film 11 is formed, and the bit line contact 1 is formed.
2 is formed, and finally the bit line 13 is formed.
【０００４】[0004]
【発明が解決しようとする課題】この従来の半導体記憶
装置及びその製造方法では、半導体記憶装置の高集積化
に伴う素子寸法の縮少に対して、容量電極の表面積が小
さくなるので十分な容量値が得られなくなるという問題
点があった。In the conventional semiconductor memory device and the manufacturing method thereof, the surface area of the capacitor electrode becomes small with respect to the reduction of the element size accompanying the high integration of the semiconductor memory device, so that a sufficient capacitance is obtained. There was a problem that the value could not be obtained.
【０００５】[0005]
【課題を解決するための手段】本発明は、半導体基板上
に設けられた、容量絶縁膜を下部容量電極と上部容量電
極とで挟んだスタック型キャパシタを有し、スイッチン
グトランジスタの片方の拡散層と前記下部容量電極とが
容量コンタクトで接続されていて、前記容量コンタクト
が前記下部容量電極からはみ出して設けられていること
を特徴とする半導体記憶装置であり、また、Ｐ型シリコ
ン基板にフィールド酸化膜を形成し、ゲート酸化膜を形
成し、ワード線を形成し、Ｎ＋ 型拡散層を形成し、第
一の層間絶縁膜を形成し、容量コンタクトを形成し、下
部容量電極を前記容量コンタクト内の途中でエッチング
を止めるように形成し、容量絶縁膜を形成し、上部容量
電極を形成し、第二の層間絶縁膜を形成し、ビット線コ
ンタクトを形成し、ビット線を形成することを特徴とす
る半導体記憶装置の製造方法である。According to the present invention, there is provided a stack type capacitor provided on a semiconductor substrate with a capacitive insulating film sandwiched between a lower capacitive electrode and an upper capacitive electrode, and one diffusion layer of a switching transistor. And the lower capacitance electrode are connected by a capacitance contact, and the capacitance contact is provided so as to extend from the lower capacitance electrode, and field oxidation is performed on a P-type silicon substrate. Forming a film, forming a gate oxide film, forming a word line, forming an N + -type diffusion layer, forming a first interlayer insulating film, forming a capacitance contact, and forming a lower capacitance electrode with the capacitance contact. Forming so as to stop etching in the middle, forming a capacitance insulating film, forming an upper capacitance electrode, forming a second interlayer insulating film, forming a bit line contact, A method of manufacturing a semiconductor memory device is characterized in that a bit line is formed.
【０００６】[0006]
【作用】本発明においては、下部容量電極からはみ出し
て容量コンタクトを設けることにより、容量コンタクト
内にも下部容量電極を形成し、容量コンタクト内の下部
容量電極の側壁をも容量電極として利用することにより
容量電極面積を増加させることができるものである。In the present invention, the lower capacitance electrode is formed in the capacitance contact by providing the capacitance contact so as to extend from the lower capacitance electrode, and the side wall of the lower capacitance electrode in the capacitance contact is also used as the capacitance electrode. The capacitance electrode area can be increased by.
【０００７】[0007]
【実施例】本発明の実施例について図面を参照して説明
する。 ［実施例１］図１〜図３は、本発明の第１の実施例に係
る半導体記憶装置及びその製造方法の断面図で、図４
は、その平面図である。図１〜図３および図４に示すよ
うに、本発明の第１の実施例の半導体記憶装置は、Ｐ型
シリコン基板１上に設けられた、下部容量電極８と上部
容量電極１０とで容量絶縁膜９を挟んだスタック型キャ
パシタを有し、Ｎ＋ 型拡散層５と下部容量電極８とを
接続する容量コンタクト７が下部容量電極８から、図３
及び図４のように、はみ出して設けられ（距離ｘ）、容
量コンタクト７内の下部容量電極８の側壁をもキャパシ
タ面積として利用する構造となっている。即ち、容量コ
ンタクトが前記下部容量電極からはみ出して設けられて
いる、とは前記下部容量電極が前記容量コンタクトの内
側に設けられていることである。また、Ｎ＋ 型拡散層
５と容量コンタクト７は、前記Ｎ＋ 型拡散層５上に容
量コンタクトを設けるように位置（関係）している。Embodiments of the present invention will be described with reference to the drawings. [Embodiment 1] FIGS. 1 to 3 are sectional views of a semiconductor memory device and a method of manufacturing the same according to a first embodiment of the present invention.
FIG. As shown in FIGS. 1 to 3 and 4, in the semiconductor memory device of the first embodiment of the present invention, the capacitance is formed by the lower capacitance electrode 8 and the upper capacitance electrode 10 provided on the P-type silicon substrate 1. A capacitor contact 7 having a stack type capacitor sandwiching an insulating film 9 and connecting the N + type diffusion layer 5 and the lower capacitor electrode 8 is formed from the lower capacitor electrode 8 to
Further, as shown in FIG. 4, the structure is provided so as to protrude (distance x), and the side wall of the lower capacitance electrode 8 in the capacitance contact 7 is also used as the capacitor area. That is, the capacitive contact is provided so as to extend from the lower capacitive electrode, which means that the lower capacitive electrode is provided inside the capacitive contact. Further, the N + type diffusion layer 5 and the capacitance contact 7 are positioned (related) so that the capacitance contact is provided on the N + type diffusion layer 5.
【０００８】また、本発明の第１の実施例の半導体記憶
装置の製造方法は、図１及び図４に示す様に、Ｐ型シリ
コン基板１にフィールド酸化膜２を膜厚５０００〜６０
００Åで形成し、ゲート酸化膜３を形成し、ワード線４
をパターニングし、ワード線４とフィールド酸化膜２を
マスクとしてＮ型不純物イオン（例えばＰなど）をイオ
ン注入してＮ＋ 型拡散層５を形成し、第一の層間絶縁
膜６を形成し、Ｎ＋ 型拡散層５と下部容量電極８とを
接続する容量コンタクト７を形成するためのレジストパ
ターン（フォトレジスト）１４を形成する。つづいて、
図２及び図４に示すように、レジストパターン１４をマ
スクとしてドライエッチングを行ない容量コンタクト７
を形成し、第二のポリシリコン膜１５を膜厚４０００〜
５０００Åで全面に形成し、下部容量電極８を形成する
ためのレジストパターン１６を形成する。In the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, as shown in FIGS. 1 and 4, the field oxide film 2 is formed on the P-type silicon substrate 1 to have a film thickness of 5000-60.
00Å, gate oxide film 3 is formed, word line 4
Is patterned, N type impurity ions (for example, P) are ion-implanted using the word line 4 and the field oxide film 2 as a mask to form an N + type diffusion layer 5, and a first interlayer insulating film 6 is formed. A resist pattern (photoresist) 14 for forming a capacitance contact 7 that connects the N + type diffusion layer 5 and the lower capacitance electrode 8 is formed. Continuing,
As shown in FIGS. 2 and 4, dry etching is performed using the resist pattern 14 as a mask to form the capacitor contact 7.
To form a second polysilicon film 15 with a film thickness of 4000 to
A resist pattern 16 for forming the lower capacitor electrode 8 is formed on the entire surface with 5000 Å.
【０００９】つづいて、図３及び図４に示すように、レ
ジストパターン１６をマスクとして第二のポリシリコン
膜１５にドライエッチングを施し、下部容量電極８を形
成する。この時、第二のポリシリコン膜１５へのドライ
エッチングは、容量コンタクト７内の途中までエッチン
グが進んだ時点で止める様にして、オーバーエッチング
によってＰ型シリコン基板１がエッチングされるのを防
ぐ。つづいて、下部容量電極８を覆うように容量絶縁膜
９を膜厚８０〜１００Åで形成し、さらに容量絶縁膜９
を覆うように上部容量電極１０を形成し、第二の層間絶
縁膜１１を形成して、ビット線コンタクト１２を形成
し、最後にビット線１３を形成する。このように、従
来、下部電極は拡散層と接続するためのコンタクトを覆
うように形成されるが、この実施例１では容量コンタク
トの一部を下部容量電極の外側まで広ろげ、下部容量電
極を容量コンタクト内まで掘り下げるように形成するも
のである。ただし、Ｎ＋ 型拡散層（基板）が掘れるの
を防ぐため、容量コンタクト内途中まで掘り下げるもの
である。Subsequently, as shown in FIGS. 3 and 4, the second polysilicon film 15 is dry-etched using the resist pattern 16 as a mask to form the lower capacitor electrode 8. At this time, the dry etching of the second polysilicon film 15 is stopped when the etching progresses to the middle of the capacitance contact 7 to prevent the P-type silicon substrate 1 from being etched by overetching. Subsequently, a capacitive insulating film 9 is formed with a film thickness of 80 to 100Å so as to cover the lower capacitive electrode 8.
Then, an upper capacitance electrode 10 is formed so as to cover the above, a second interlayer insulating film 11 is formed, a bit line contact 12 is formed, and finally a bit line 13 is formed. As described above, conventionally, the lower electrode is formed so as to cover the contact for connecting to the diffusion layer, but in the first embodiment, a part of the capacitive contact is spread to the outside of the lower capacitive electrode to form the lower capacitive electrode. Is formed so as to be dug down into the capacitor contact. However, in order to prevent the N + -type diffusion layer (substrate) from being dug, the N + -type diffusion layer is dug halfway in the capacitance contact.
【００１０】［実施例２］次に、本発明の第２の実施例
について図５、図６を参照して説明する。図５は、本発
明の第２の実施例に係る半導体記憶装置及びその製造方
法の断面図で、図６はその平面図である。本発明の第２
の実施例の半導体記憶装置は、容量コンタクト７が下部
容量電極８からはみ出して設けられ（距離ｘ）、かつ、
フィールド酸化膜２が下部容量電極８の内側に設けられ
て（距離ｙ）、下部容量電極８が、容量コンタクト７内
の底部までエッチングされている構造となっている。即
ち、下部容量電極の内側に設けられているとは、前記フ
ィールド酸化膜２の外側に前記下部容量電極８が設けら
れているということである。[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS. 5 is a sectional view of a semiconductor memory device and a method of manufacturing the same according to a second embodiment of the present invention, and FIG. 6 is a plan view thereof. Second of the present invention
In the semiconductor memory device of the above embodiment, the capacitor contact 7 is provided so as to protrude from the lower capacitor electrode 8 (distance x), and
The field oxide film 2 is provided inside the lower capacitance electrode 8 (distance y), and the lower capacitance electrode 8 is etched to the bottom of the capacitance contact 7. That is, being provided inside the lower capacitance electrode means that the lower capacitance electrode 8 is provided outside the field oxide film 2.
【００１１】また、本発明の第２の実施例の半導体記憶
装置の製造方法は、第１の実施例と同様に下部容量電極
８まで形成する。この時、下部容量電極８は、フィール
ド酸化膜２をエッチングストッパーとして、Ｐ型シリコ
ン基板１をエッチングすることなく、オーバーエッチン
グを施すことができ、容量コンタクト７内の底部までエ
ッチングされる。つづいて、第１の実施例と同様にビッ
ト線１３まで形成する。この実施例では、フィールド酸
化膜２を下部容量電極８の内側に設けることにより、下
部容量電極８を形成するときにオーバーエッチングを可
能とし、製造マージンを広げることができる。また、下
部容量電極８の側壁が容量コンタクト７内の底部まで形
成されるので、容量電極面積をさらに増加させることが
できる。この実施例２では、容量コンタクト部のフィー
ルドパターンをつめることにより下部容量電極を容量コ
ンタクト内まで掘り下げるときに、フィールド酸化膜が
ストッパーになりＮ＋ 型拡散層が掘れるのを防ぐこと
ができ、オーバーエッチングが可能となるため、エッチ
ング残りが生じにくくなるものである。In the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention, the lower capacitance electrode 8 is formed as in the first embodiment. At this time, the lower capacitance electrode 8 can be over-etched without etching the P-type silicon substrate 1 using the field oxide film 2 as an etching stopper, and the bottom of the capacitance contact 7 is etched. Subsequently, the bit line 13 is formed as in the first embodiment. In this embodiment, by providing the field oxide film 2 inside the lower capacitance electrode 8, overetching is possible when the lower capacitance electrode 8 is formed, and the manufacturing margin can be widened. Further, since the side wall of the lower capacitance electrode 8 is formed to the bottom of the capacitance contact 7, the capacitance electrode area can be further increased. In the second embodiment, when the lower capacitance electrode is dug down into the capacitance contact by filling the field pattern of the capacitance contact portion, it is possible to prevent the field oxide film from acting as a stopper and digging the N + -type diffusion layer. Since etching becomes possible, etching residue is less likely to occur.
【００１２】[0012]
【発明の効果】以上説明したように、本発明によれば、
下部容量電極からはみ出して容量コンタクトを設けるこ
とにより、容量コンタクト内にも下部容量電極を形成
し、容量コンタクト内の下部容量電極の側壁をも容量電
極として利用することにより容量電極面積を増加させる
ことができる。このことにより、半導体記憶装置の高集
積化に伴い素子寸法が小さくなっても十分に高い容量値
を確保することができ、また、これにより、セル面積を
増大させることなく、かつ製造工程を複雑にすることな
く、セル容量値を増加させることができるという効果を
奏するものである。As described above, according to the present invention,
By forming a capacitance contact outside the lower capacitance electrode, a lower capacitance electrode is also formed in the capacitance contact, and the side wall of the lower capacitance electrode in the capacitance contact is also used as the capacitance electrode to increase the capacitance electrode area. You can As a result, it is possible to secure a sufficiently high capacitance value even if the element size becomes smaller due to the higher integration of the semiconductor memory device, and the manufacturing process is complicated without increasing the cell area. It is possible to increase the cell capacitance value without increasing
【図１】本発明の実施例１に係る半導体記憶装置とその
製造方法を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor memory device and a method of manufacturing the same according to a first embodiment of the present invention.
【図２】本発明の実施例１に係る半導体記憶装置とその
製造方法を示す断面図で［図１］に続くものあるFIG. 2 is a cross-sectional view showing a semiconductor memory device and a method of manufacturing the same according to the first embodiment of the present invention, which is subsequent to FIG. 1;
【図３】本発明の実施例１に係る半導体記憶装置とその
製造方法を示す断面図で［図２］に続くものあるFIG. 3 is a cross-sectional view showing the semiconductor memory device and the method for manufacturing the same according to the first embodiment of the present invention, which is subsequent to FIG. 2;
【図４】本発明の実施例１に係る半導体記憶装置とその
製造方法を示す平面図である。FIG. 4 is a plan view showing the semiconductor memory device and the manufacturing method thereof according to the first embodiment of the present invention.
【図５】本発明の実施例２に係る半導体記憶装置とその
製造方法を示す断面図である。FIG. 5 is a cross-sectional view showing a semiconductor memory device and a method of manufacturing the same according to a second embodiment of the present invention.
【図６】本発明の実施例２に係る半導体記憶装置とその
製造方法を示す平面図である。FIG. 6 is a plan view showing a semiconductor memory device and a method of manufacturing the same according to a second embodiment of the present invention.
【図７】従来の半導体記憶装置とその製造方法を示す断
面図である。FIG. 7 is a cross-sectional view showing a conventional semiconductor memory device and a method for manufacturing the same.
【図８】従来の半導体記憶装置とその製造方法を示す平
面図である。FIG. 8 is a plan view showing a conventional semiconductor memory device and a method for manufacturing the same.
１．シリコン基板 ２．フィールド酸化膜 ３．ゲート酸化膜 ４．ワード線 ５．Ｎ＋ 型拡散層 ６．第一の層間絶縁膜 ７．容量コンタクト ８．下部容量電極 ９．容量絶縁膜 １０．上部容量電極 １１．第二の層間絶縁膜 １２．ビット線コンタクト １３．ビット線 １４、１６．フォトレジスト １５．第二のポリシリコン膜1. Silicon substrate 2. Field oxide film 3. Gate oxide film 4. Word line 5. N + type diffusion layer 6. First interlayer insulating film 7. Capacitance contact 8. Lower capacitance electrode 9. Capacitance insulating film 10. Upper capacitance electrode 11. Second interlayer insulating film 12. Bit line contact 13. Bit line 14, 16. Photoresist 15. Second polysilicon film
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成６年７月１５日[Submission date] July 15, 1994
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図２[Name of item to be corrected] Figure 2
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図２】 本発明の実施例１に係る半導体記憶装置とそ
の製造方法を示す断面図で［図１］に続くものである。FIG. 2 is a cross-sectional view showing the semiconductor memory device and the method of manufacturing the same according to the first embodiment of the present invention, which is subsequent to FIG. 1;
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図３[Name of item to be corrected] Figure 3
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図３】 本発明の実施例１に係る半導体記憶装置とそ
の製造方法を示す断面図で［図２］に続くものである。FIG. 3 is a cross-sectional view showing the semiconductor memory device and the method for manufacturing the same according to the first embodiment of the present invention, which is subsequent to FIG. 2;
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/822
Claims (4)
を下部容量電極と上部容量電極とで挟んだスタック型キ
ャパシタを有し、スイッチングトランジスタの片方の拡
散層と前記下部容量電極とが容量コンタクトで接続され
ていて、前記容量コンタクトが前記下部容量電極からは
み出して設けられていることを特徴とする半導体記憶装
置。1. A stack type capacitor provided on a semiconductor substrate, wherein a capacitive insulating film is sandwiched between a lower capacitance electrode and an upper capacitance electrode, and one diffusion layer of a switching transistor and the lower capacitance electrode are capacitive. A semiconductor memory device, wherein the semiconductor memory device is connected by a contact, and the capacitance contact is provided so as to protrude from the lower capacitance electrode.
の内側に設けられている請求項１記載の半導体記憶装
置。2. The semiconductor memory device according to claim 1, wherein a field oxide film is provided inside the lower capacitance electrode.
形成し、ゲート酸化膜を形成し、ワード線を形成し、Ｎ
＋ 型拡散層を形成し、第一の層間絶縁膜を形成し、容
量コンタクトを形成し、下部容量電極を前記容量コンタ
クト内の途中でエッチングを止めるように形成し、容量
絶縁膜を形成し、上部容量電極を形成し、第二の層間絶
縁膜を形成し、ビット線コンタクトを形成し、ビット線
を形成することを特徴とする請求項１記載の半導体記憶
装置の製造方法。3. A field oxide film is formed on a P-type silicon substrate, a gate oxide film is formed, word lines are formed, and N is formed.
A + type diffusion layer is formed, a first interlayer insulating film is formed, a capacitor contact is formed, a lower capacitor electrode is formed so as to stop etching in the middle of the capacitor contact, and a capacitor insulating film is formed. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein an upper capacitor electrode is formed, a second interlayer insulating film is formed, a bit line contact is formed, and a bit line is formed.
形成し、ゲート酸化膜を形成し、ワード線を形成し、Ｎ
＋ 型拡散層を形成し、第一の層間絶縁膜を形成し、容
量コンタクトを形成し、前記フィールド酸化膜をエッチ
ングストッパーとして、下部容量電極を前記容量コンタ
クト内の底部までエッチングし、容量絶縁膜を形成し、
上部容量電極を形成し、第二の層間絶縁膜を形成し、ビ
ット線コンタクトを形成し、ビット線を形成することを
特徴とする請求項２記載の半導体記憶装置の製造方法。4. A field oxide film is formed on a P-type silicon substrate, a gate oxide film is formed, word lines are formed, and N is formed.
A + type diffusion layer is formed, a first interlayer insulating film is formed, a capacitor contact is formed, and the lower capacitor electrode is etched to the bottom of the capacitor contact using the field oxide film as an etching stopper. To form
3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the upper capacitance electrode is formed, the second interlayer insulating film is formed, the bit line contact is formed, and the bit line is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5259326A JP2565111B2 (en) | 1993-09-22 | 1993-09-22 | Semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5259326A JP2565111B2 (en) | 1993-09-22 | 1993-09-22 | Semiconductor memory device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0794599A true JPH0794599A (en) | 1995-04-07 |
| JP2565111B2 JP2565111B2 (en) | 1996-12-18 |
Family
ID=17332540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5259326A Expired - Lifetime JP2565111B2 (en) | 1993-09-22 | 1993-09-22 | Semiconductor memory device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2565111B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585998A (en) * | 1995-12-22 | 1996-12-17 | International Business Machines Corporation | Isolated sidewall capacitor with dual dielectric |
| US5633781A (en) * | 1995-12-22 | 1997-05-27 | International Business Machines Corporation | Isolated sidewall capacitor having a compound plate electrode |
| US5712759A (en) * | 1995-12-22 | 1998-01-27 | International Business Machines Corporation | Sidewall capacitor with L-shaped dielectric |
| US5914851A (en) * | 1995-12-22 | 1999-06-22 | International Business Machines Corporation | Isolated sidewall capacitor |
-
1993
- 1993-09-22 JP JP5259326A patent/JP2565111B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585998A (en) * | 1995-12-22 | 1996-12-17 | International Business Machines Corporation | Isolated sidewall capacitor with dual dielectric |
| US5633781A (en) * | 1995-12-22 | 1997-05-27 | International Business Machines Corporation | Isolated sidewall capacitor having a compound plate electrode |
| US5701647A (en) * | 1995-12-22 | 1997-12-30 | International Business Machines Corporation | Method for making an isolated sidewall capacitor having a compound plate electrode |
| US5712759A (en) * | 1995-12-22 | 1998-01-27 | International Business Machines Corporation | Sidewall capacitor with L-shaped dielectric |
| US5914851A (en) * | 1995-12-22 | 1999-06-22 | International Business Machines Corporation | Isolated sidewall capacitor |
| US6027966A (en) * | 1995-12-22 | 2000-02-22 | International Business Machines Corporation | Isolated sidewall capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2565111B2 (en) | 1996-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0487951B1 (en) | Method of fabricating a stacked capacitator DRAM cell | |
| JPH08153858A (en) | Manufacture of semiconductor device | |
| JPH06177345A (en) | Semiconductor memory and its manufacture | |
| US5591670A (en) | Method of manufacturing a semiconductor device having self aligned contact hole | |
| JP2959412B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| JP2565111B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| KR0161438B1 (en) | Semiconductor memory device and manufacture thereof | |
| JP2002076300A (en) | Semiconductor device and its manufacturing method | |
| JPH02143456A (en) | Manufacture of lamination type memory cell | |
| JPH0294564A (en) | Manufacture of semiconductor device | |
| JP2765133B2 (en) | Method for manufacturing semiconductor device | |
| JPH11340436A (en) | Manufacture of semiconductor storage | |
| KR100209223B1 (en) | Semiconductor device manufacturing method for forming contact | |
| JPH08139314A (en) | Semiconductor device and its manufacture | |
| JP3361377B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR960000963B1 (en) | Semiconductor integrated circuit device fabrication process | |
| JPH05267324A (en) | Manufacture of mos semiconductor device | |
| JPS6240765A (en) | Read-only semiconductor memory and manufacture thereof | |
| JP3036117B2 (en) | Method for manufacturing semiconductor device | |
| KR100293715B1 (en) | Manufacturing method of highly integrated semiconductor memory device | |
| JPH1126462A (en) | Manufacture of semiconductor device | |
| JPH03157969A (en) | Semiconductor storage device | |
| JPH0462965A (en) | Memory cell of one transistor type dynamic ram | |
| JPH08204153A (en) | Manufacture of semiconductor storage device | |
| JPH06132495A (en) | Fabrication of semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081003 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101003 Year of fee payment: 14 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111003 Year of fee payment: 15 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121003 Year of fee payment: 16 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131003 Year of fee payment: 17 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |