JPH0658997A - Semiconductor logic device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor logic device in which the time required for a signal to pass through an interface, constituted of a logic circuit and latch circuits on the input and output sides thereof, can be grasped accurately. CONSTITUTION:The semiconductor logic device comprises first latch circuits 100, 101, 13 for latching the signals in synchronism with a first clock signal CLK 2 and inputting to a logic circuit, i.e., a memory 26, and a second latch circuit 19 for latching the signal outputted from the memory 26 in synchronism with a second clock signal CLK 4 and outputting the latched signal. The semiconductor logic device further comprises an OR gate 27 for receiving the first clock signal CLK 2 and a control signal TEST 1 and immediately inputting a signal into the memory 26 regardless of the first clock signal CLK 2 so long as the control signal TEST 1 is significant, and an OR gate 28 for receiving the second clock signal CLK 4 and the control signal TEST 1 and immediately outputting a signal from the memory 26 regardless of the second clock signal CLK 4 so long as the control signal TEST 1 is significant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic device incorporated in a microprocessor or the like, a logic circuit constituting the semiconductor logic device, a latch circuit for inputting a signal to the logic circuit, and an output from the logic circuit. The present invention relates to a semiconductor logic device in which a real time for processing a signal can be directly measured for each of a logic circuit for latching and outputting a signal and the performance of a built-in logic circuit can be easily evaluated.

[0002]

2. Description of the Related Art FIG. 7 is a functional block diagram of a microprocessor as an example of a semiconductor integrated circuit incorporating a semiconductor logic device.

In FIG. 7, reference numeral 1 is a clock generation circuit, and the clock generated by the clock generation circuit 1 is supplied to and used by the entire microprocessor. Reference numeral 2 is a control unit, which mainly controls the data path unit 3 that executes instructions such as logical operations.

Reference numeral 4 is a built-in memory unit, which stores instructions executed by the data path unit 3 and also stores data before and after execution of calculation. Reference numeral 5 is a functional block, for example, a counter that measures time with a clock generated by the clock generation circuit 1 or an I / O that inputs / outputs information to / from the outside of a chip in which this semiconductor integrated circuit is configured. Includes O circuit.

The blocks are connected to each other by an address bus 6, a data bus 7, a clock and control signal line 8 and the like. Specifically, the clock and control signal line 8 is connected to the data path unit 3, the built-in memory unit 4, and the functional block 5 from the clock generation circuit 1 and the control unit 2.

The address bus 6 is connected to the data path unit 3
To the built-in memory unit 4 and the function block 5. Further, the data bus 7 is connected to the built-in memory unit 4 and the functional block 5 as an input / output, and to the control unit 2 as an input with the data path unit 3 as a center.

FIG. 8 shows "CMOS DIGITAL C" by Shoji Masakazu.
8 is a block diagram showing a configuration of a portion corresponding to the internal memory unit 4 of FIG. 7, that is, a static RAM (hereinafter, referred to as SRAM) for temporarily storing data, based on “IRCUIT TECHNOLOGY” P.333 (PRENTICE HALL). Note that FIG. 8 shows an example in which the data to be processed is limited to 1 bit.

In FIG. 8, reference numeral 9 is a memory cell, and in the example shown in FIG. 8, 2 ^N × 2 ^N memory cells 9, 9 ... Are arranged. The physical arrangement position of each of these memory cells 9 is determined by the addresses A _{0 to} A _2N-1 input from the address bus 6 of FIG.

Of these, the addresses A _{0 to} A _N-1 are taken into the address latch 100 by the control signal CLK2 described later, and further decoded by the row decoder 11 to select any of the 2 ^N word lines 12. To be done. On the other hand, the addresses A _{N to} A _2N-1 are also taken into the address latch 101 by the same control signal CLK2, connected to the Y selector 16 through the column decoder 14, and selected from 2 ^N.

The Y selector 16 selects one column in response to the 2 ^N Y selector control signals from the column decoder 14, and the bit line 17a and the inverted bit line 17 from the memory cell 9 are selected.
The data information output to b is I / O line 15a, inverted I / O line 15
It is a gate to tell b.

Reference numeral 18 is a sense amplifier, which is an I / O line.
15a, Amplifies the minute signal read to the inverted I / O line 15b. The data signal amplified by the sense amplifier 18 is clocked by the data latch 19 by the control signal CLK4 and then output to the address bus 6 through the driver 20. Reference numeral 21 is a write driver, and the data bus 7
Data is written from the I / O line 15a, the inverted I / O line 15b, and the Y selector 16 to the memory cell 9.

The output conditions of the drivers 20 and 21 are taken in by the control signal latch 13 in synchronization with the control signal CLK2.
It is controlled by the CS signal 22 and the R / # W signal 24. In addition,
“#” Indicates low active.

That is, the #CS signal 22 is "L" (the internal memory unit 4 is selected) and the R / # W signal 24 is "H".
If it is (lead), the output signal of OR gate 25 is "
The output signal of the OR gate 23 becomes "H".
become. The "L" output signal of the OR gate 25 gives the driver 21 a non-active state, and the OR gate 23 "H" output signal gives the driver 20 an active state.

On the other hand, the #CS signal 22 is "L" (the internal memory section 4 is selected) and the R / # W signal 24 is "L".
When it is (write), the output signal of OR gate 25 is "
It becomes "H", which causes the output signal of the OR gate 23 to be "L".
become. The "H" output signal of the OR gate 25 gives the driver 21 an active state, and the "L" output signal of the OR gate 23 gives the driver 20 a non-active state.

FIG. 9 shows the built-in memory unit 4 shown in FIG.
2 is a circuit diagram showing an input / output interface portion composed of address latches 100, 101 and data latch 19 of FIG. The address latches 100 and 101 shown in FIG. 9 also show some of the functions of the control signal latch 13.

FIG. 10 is a timing chart showing only the operation state at the time of memory reading in the circuit shown in FIG.

In the timing chart of FIG. 10, the address A shown in FIG. 10 (b) is based on the basic clock φ generated by the clock generation circuit 1 as shown in FIG. 10 (a). _{0 to} A _2N-1 , the control signal CLK2 of the address latches 100 and 101 shown in FIG. 10 (c) generated from the control signal and the basic clock φ, and the data shown in FIG. 10 (d). The control signal CLK4 of the latch and the data D _{0 to DN} on the data bus 7 shown in FIG.
The sampling control signal F1 of the data path unit 3 shown in (f) is shown.

Next, the operation of the built-in memory unit 4 will be described with reference to FIGS. 7, 8, 9 and 10.

The basic operation of the data path unit 3 is clock φ.
.Phi.1 to .phi.4 are set as one bus cycle, and the built-in memory section 4 operates in synchronization with this. In this conventional microprocessor, the data path unit 3 is shown in FIG. 10 (b) from the rise time of φ1 of the bus cycle 1 shown in FIG. 10 (a).
The address is output to the address bus 6 as shown in FIG. 3, and data is transmitted from the data bus 7 by the control signal F1 shown in FIG. 10 (f) during the period φ1 of the next bus cycle 2. Latch to.

On the other hand, in the internal memory unit 4, φ2 is "L".
As shown in Fig. 10 (c), the control signal CL
The address output to the address bus 6 by K2 is taken into the address latches 100 and 101, and the #CS signal 22,
The R / # W signal 24 is captured in the control signal latch 13.

Since the address fetched in the address latches 100 and 101 designates the word line 12 and the Y selector 16 respectively by the row decoder 11 and the column decoder 14,
Data information is input from the memory cell 9 of a specific address corresponding to this to the data latch 19 through the sense amplifier 18, and is further sent from the driver 20 to the data path unit 3 through the data bus 7.

At this time, sampling of the data latch 19 is performed by the control signal CLK4 shown in FIG. 10 (d). Therefore, the data path unit 3 latches the data latched by the data latch 19 and output to the data bus 7 as shown in FIG.
Fetch with control signal F1 in synchronization with.

As shown in the timing chart of FIG. 10, the conventional microcomputer having such a memory has a control signal at φ 2 of each bus cycle.
If the #CS signal 22 and the R / # W signal 24 are input to the address / control signal latch 19 by the time the address is fetched by CLK2, memory reading is possible. However, since the above-described operation is synchronized with the clock, it is not possible to accurately evaluate the time actually required to read the data from the internal memory unit 4.

Further, as shown in FIG. 10, when the output of the address to the address bus 6 is delayed from the control signal CLK2 timing like φ2 of the bus cycle 3,
Alternatively, when the read speed of the built-in memory unit 4 is evaluated in a state that does not depend on the timing, there is a problem that the performance cannot be evaluated.

That is, in bus cycle 1, the address AA
Is the setup time T rather than the rise of the control signal CLK2
Input to the internal memory unit 4 at the time before _Ast.2 , and the data (AA) for this is delayed by the delay time T from the rise of the control signal CLK4.
Since it is output at the time after _Dd1.4 , the result is the address.
The delay time from the input of AA to the output of data (AA) is T _(AMD1) φ which is the total of both.

However, in bus cycle 2, the address BB
Is the setup time T rather than the fall of the control signal CLK2
_The data (BB) corresponding to this is input to the internal memory unit 4 at the time before _Ast.3, but is output at the time after the delay time T _Dd1.4 as in the case of the bus cycle 1. Therefore, the delay time from the input of the address BB to the output of the data (BB) is T _(AMD2) φ which is the sum of both. In the bus cycle 3, the built-in memory unit 4 cannot take in the address CC.

[0027]

As described above, the conventional semiconductor logic device having a built-in logic circuit has a latch circuit for latching a signal to be input in synchronization with a clock signal and an output signal in synchronization with the clock signal. Since the latch circuit for latching is provided on both sides of the input and output of the logic circuit, the time required from the signal input to the signal output by the logic circuit itself,
The time required from the time a signal is applied to the input side latch circuit to the time the signal is output from the output side latch circuit,
Furthermore, it is not possible to accurately grasp the time required from the time when a signal is applied to each latch circuit on both the input and output sides until the signal is output. However, accurately grasping such time is very important in the performance evaluation of the semiconductor integrated circuit chip.

The present invention has been made in view of the above circumstances, and it is necessary for a signal to pass through an interface portion composed of a built-in logic circuit and latch circuits attached to both sides of its input and output. An object of the present invention is to provide a semiconductor logic device capable of accurately grasping time.

[0029]

A first aspect of a semiconductor logic device according to the present invention is a first latch circuit for latching a signal in synchronization with a first clock signal and inputting the signal to a logic circuit, and a logic circuit. And a second latch circuit for latching and outputting a signal processed by the circuit in synchronization with a second clock signal, the control signal being input to the semiconductor logic device.
When the control signal is significant, gate means for immediately inputting to the logic circuit regardless of the first clock signal when a signal to be input to the logic circuit is given, and the above-mentioned control signal is input, When this control signal is significant, it is second when the signal output from the logic circuit is given.
And a gate means for immediately outputting regardless of the clock signal.

A second aspect of the semiconductor logic device according to the present invention is the first aspect in which a control signal is input, and when the control signal is significant, a signal to be input to the logic circuit is given. It comprises a gate means for inputting to the logic circuit immediately regardless of the clock signal, and a short-circuit means for directly supplying the output signal of the first latch circuit to the second latch circuit when the control signal is significant.

According to a third aspect of the semiconductor logic device of the present invention, the first control signal is input, and when the first control signal is significant, a signal to be input to the logic circuit is given. In this case, the gate means for immediately inputting to the logic circuit regardless of the first clock signal, and the second control signal are input, and when the second control signal is significant, the signal output from the logic circuit is Gate means for immediately outputting the second clock signal regardless of the second clock signal when supplied.

[0032]

According to the first aspect of the present invention, when the control signal is made significant, the signal applied to the first latch circuit becomes the first signal regardless of both the first and second clock signals. The signal is output from the second latch circuit from the time when the signal is applied to the first latch circuit because the latch circuit, the logic circuit, and the second latch circuit perform real-time processing and output from the second latch circuit. The time required to reach the point is known.

In the second aspect of the present invention, when the control signal is made significant, the signal applied to the first latch circuit causes the logic circuit to operate regardless of both the first and second clock signals. Since it is short-circuited and is processed in the first latch circuit and the second latch circuit in real time and is output from the second latch circuit, it is output from the time when the signal is applied to the first latch circuit and The time required from the time the signal is applied to the second latch circuit to the time it is output is found.

In the third aspect of the present invention, when the first control signal is made significant, regardless of the first clock signal,
The signal applied to the first latch circuit is processed in real time by the first latch circuit and the logic circuit, and is latched and output in synchronization with the second clock signal by the second latch circuit. From the time when the signal is given to the latch circuit of
The time required until the signal is output from the second latch circuit in synchronism with the clock of is determined. Further, when the second control signal is made significant, the signal applied to the first latch circuit is synchronized with the first clock signal in the first latch circuit regardless of the second clock signal. Since it is latched, processed in real time by the logic circuit and the second latch circuit, and output from the second latch circuit, from the time when the signal is latched in the first latch circuit in synchronization with the first clock signal. The time required until the signal is output from the second latch circuit is known.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. First, the first invention of the present invention will be described.

FIG. 1 shows an address latch 100 of a built-in memory unit 4 as a conventional built-in logic circuit shown in FIG. 8 of a microprocessor having a built-in memory unit 4 as a semiconductor logic device of the first invention of the present invention. , 101 and data latch
FIG. 20 is a circuit diagram showing a portion corresponding to an input / output interface portion of 19. The address latches 100 and 101 shown in FIG. 1 also show some of the functions of the control signal latch 13.

In the circuit shown in FIG. 1, the control signal CLK2 is conventionally applied directly to the address latches 100, 101 and the control signal latch 13, but is applied via the 2-input OR gate 27. The control signal TEST1 is applied to the other input of the OR gate 27. Also, in the past, control signals
What was supplied to the data latch 19 directly from CLK4 is provided via the 2-input OR gate 28. This OR gate
Similarly to the OR gate 27 described above, the other input of the control signal TE
ST1 is given.

The control signal TEST1 is the address latch 100, 10
It is a signal which causes the control signal latch 13 and the data latch 19 to constantly receive the input signal during the period of each bus cycle.
OR signal of this control signal TEST1 and conventional control signal CLK2
The control signal ADL1 is newly generated by the OR gate 27, and the control signal TEST1 and the conventional control signal CLK4 are combined.
A control signal DTL1 is newly generated by generating an OR signal in the OR gate 28.

FIG. 2 is a timing chart for explaining the operation of the circuit having the configuration shown in FIG.

In this timing chart, the addresses A _{0 to} A shown in FIG. 2B are used with reference to the basic clock φ generated by the clock generation circuit 1 as shown in FIG. 2A. _2N-1 , the control signal TEST1 shown in FIG. 2 (c), the control signal ADL1 which is the output signal of the OR gate 27 shown in FIG. 2 (d), and the control signal ADL1 shown in FIG. 2 (e). 2 is a control signal DTL1 which is an output signal of the OR gate 28 shown in FIG.
Data D _{0 to DN} on the data bus 7 shown in (f)
Is shown.

In FIG. 2, the bus cycle 1 is shown in FIG.
The same operation as the conventional bus cycle 1 shown in FIG.

However, in the bus cycle T1, the control signal TE
Since the control signal ADL1 becomes "H" by setting ST1 to "H", the address latches 100, 101, control signal latch 13
Latches the address on the address bus 6 and inputs it to the memory 26 regardless of the clock. As a result, the data corresponding to the inputted address is read from the memory 26, but the control signal DTL1 becomes "H" by setting the control signal TEST1 to "H", so that the data latch 19 is not concerned with the clock. Instead, the data output from the memory 26 is latched and output to the data bus 7.

Therefore, as shown in FIG. 2 (c),
The time from when the control signal TEST1 is set to "H" to when the data is output to the data bus 7 as shown in FIG. 2 (f) can be evaluated as the read delay time T _(AMD) .

Next, the second invention of the present invention will be described. FIG. 3 shows address latches 100, 101 and data latch 19 of the conventional internal memory unit 4 shown in FIG. 8 of the internal memory unit 4 as the semiconductor logic device of the second invention of the present invention.
3 is a circuit diagram showing a portion corresponding to the input / output interface portion of FIG. The address latches 100 and 101 shown in FIG. 3 also show some of the functions of the control signal latch 13.

3 is different from FIG. 1 in that a transmission gate 32 is provided in parallel with the memory 26 between the output nodes 30 of the address latches 100 and 101, the control signal latch 13 and the input node 31 of the data latch 19. TEST as a control signal of the point, address latch 100, 101, control signal latch 13.
2 is added and the control signal TEST1,
This is the point where the OR signal of TEST2 and CLK2 is generated. Therefore, the output signal of the OR gate 29 is used as the control signal ADL2.

The transmission gate 32 short-circuits the node 30 and the node 31 when the above-mentioned control signal TEST2 is "H".

FIG. 4 is a timing chart for explaining the operation of the circuit having the configuration shown in FIG.

In this timing chart, the addresses A _{0 to} A shown in FIG. 4B are used with reference to the basic clock φ generated by the clock generation circuit 1 as shown in FIG. 4A. _2N-1 , the control signal TEST1 shown in FIG. 4 (c), the control signal ADL2 which is the output signal of the OR gate 29 shown in FIG. 4 (d), and the control signal ADL2 shown in FIG. 4 (e). The control signal DTL1 which is the output signal of the OR gate 28, which is shown in FIG.
The control signal TEST2 shown in (f) and the data D _{0 to DN} on the data bus 7 shown in FIG. 4 (g) are shown.

In FIG. 4, in the bus cycle T1,
The control signal TEST1 is "H", the control signal TEST2 is "L", the control signal ADL2 which is the output signal of the OR gate 29 is "H", and the transmission gate 32 is connected to the nodes 30 and 31. Is not short-circuited, the same operation as the bus cycle T1 shown in FIG. 2 is performed.

However, in the bus cycle T2, the control signal TE
By setting ST1 to "L" and the control signal TEST2 to "H", the control signal ADL2 which is the output signal of the OR gate 29 is set to "L".
H ”, and the transmission gate 32 becomes a node
Shorts 30 and 31, so address latches 100, 101,
The control signal latch 13 latches the address on the address bus 6 regardless of the clock, outputs it from the node 30 to the node 31 via the transmission gate 32, and causes the data latch 19 to latch it. This allows the address latch 10
The addresses 0, 101, and the address latched by the control signal latch 13 are directly latched by the data latch 19 and output to the data bus 7.

Therefore, by setting the control signal TEST2 to "H", the address latches 100, 101, the control signal latch 13
The delay time T _(AD) of can be evaluated. By subtracting this delay time T _(AD) from the memory read delay time T _(AMD) obtained in the bus cycle T1, the correct read delay time of the memory 26 itself can be obtained.

In this embodiment, the memory 26 is the object, but the delay time of the logic circuit of the ordinary clock synchronization system other than the memory 26 can be measured similarly. In the above embodiment, the first invention and the second invention described above are shown in combination.
Of course, it is also possible to adopt a configuration in which only the second invention is made independent.

Next, the third invention of the present invention will be described. FIG. 5 shows the address latches 100, 101 and the data latch 19 of the conventional built-in memory unit 4 shown in FIG. 8 of the built-in memory unit 4 as the semiconductor logic device of the third invention of the present invention.
3 is a circuit diagram showing a portion corresponding to the input / output interface portion of FIG. The address latches 100 and 101 shown in FIG. 5 also show some of the functions of the control signal latch 13.

5 is different from the first invention shown in FIG. 1 in that the control signal of the data latch 19 is set to TEST3 and is independent of the control signals TEST1 of the address latches 100 and 101 and the control signal latch 13. It is a point. Therefore, the control signal
TEST3 and CLK4 are input to the OR gate 33, and the OR signal of both is used as the control signal DTL2 of the data latch 19.

FIG. 6 is a timing chart for explaining the operation of the circuit having the configuration shown in FIG.

In this timing chart, the addresses A _{0 to} A shown in FIG. 6B are used with reference to the basic clock φ generated by the clock generation circuit 1 as shown in FIG. 6A. _2N-1 , the control signal TEST1 shown in FIG. 6 (c), and the control signal TEST shown in FIG. 6 (d)
3 and the control signal ADL1 which is the output signal of the OR gate 27 shown in FIG. 6 (e) and the OR gate shown in FIG. 6 (f).
A control signal DTL2 33 which is an output signal of the shows and the data D ₀ to D _N on the data bus 7 shown in FIG. 6 (g).

In FIG. 6, in the bus cycle T3, the control signal TEST1 is "H", the control signal TEST3 is "L", and the control signal which is the output signal of the OR gate 27.
ADL1 becomes "H" regardless of the clock and OR
Control signal DTL2, which is the output signal of gate 33, is a bus cycle
It becomes "H" only at φ4 of T3. In other words, the address latches 100, 101 and the control signal latch 13 always latch the address from the address bus 6 regardless of the clock, and the data latch 19 operates in the same manner as the conventional example. Therefore, the delay time for reading the data from the memory 26 to the data latch 19 becomes a prescribed delay time T _Dd1.4 synchronized with the clock, and from the time when the address is determined until the corresponding data is read from the memory 26. The time T _(AM) φ of can be obtained.

On the other hand, in the bus cycle T4, the control signal TEST
1 is "L" and the control signal TEST3 is "H", and the control signal ADL1 which is the output signal of the OR gate 27 becomes "H" only in φ2 of the bus cycle T4.
The control signal DTL2 which is the output signal of the OR gate 33 becomes "H" regardless of the clock. In other words, the address latch
100, 101, control signal latch 13 operates in the same manner as the conventional example, and data latch 19 operates in the memory regardless of the clock.
The data read from 26 is always latched and data bus 7
Output to. Therefore, the setup time from the address bus 6 to the address latches 100, 101 and the control signal latch 13 latching the address and inputting it to the memory 26 is the prescribed setup time T _Ast.3 synchronized with the clock, so that the memory 26 The data read delay time T _(MD) φ from the data latch 19 to the data latch 19 can be obtained.

In each of the above embodiments, the memory 26 and the latch circuits on both sides of the input and output, that is, the address latches 100, 101,
Although the circuit including the control signal latch 13 and the data latch 19 is shown as the semiconductor logic device of the present invention, the circuit is not limited to this.

[0060]

As described in detail above, according to the present invention,
In a semiconductor integrated circuit such as a microprocessor having a built-in memory, the read delay time of the built-in memory can be easily and accurately evaluated.

That is, in the first invention, the time required from the time when the signal is applied to the first latch circuit to the time when the signal is output from the second latch circuit is found.

In the second invention, the time required from the time when the signal is applied to the first latch circuit to the time when the signal is output and the time required from the time when the signal is applied to the second latch circuit to the time when the signal is output. Prove.

Further, in the third invention, the time required from the time when the signal is applied to the first latch circuit to the time when the signal is output from the second latch circuit in synchronization with the second clock is The time required from the time when the signal is latched in the first latch circuit to the time when the signal is output from the second latch circuit in synchronization with the first clock signal is found.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a portion corresponding to an input / output interface portion of a memory unit as a semiconductor logic device of a first invention of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a portion corresponding to an input / output interface portion of a memory unit as a semiconductor logic device of a second invention of the present invention.

FIG. 4 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 5 is a circuit diagram showing a portion corresponding to an input / output interface portion of a memory unit as a semiconductor logic device of a third invention of the present invention.

6 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 7 is a functional block diagram of a microprocessor as an example of a semiconductor integrated circuit including a memory unit as a conventional semiconductor logic device.

8 is a block diagram showing a detailed configuration of a portion corresponding to the built-in memory unit of FIG.

9 is a circuit diagram showing an input / output interface portion of the built-in memory unit shown in FIG.

10 is a timing chart showing only an operation state at the time of memory reading in the circuit shown in FIG.

[Explanation of symbols]

 13 control signal latch 19 data latch 26 memory 27 OR gate 28 OR gate 29 OR gate 32 transmission gate 33 OR gate 100 address latch 101 address latch CLK2 first clock signal CLK4 second clock signal TEST1 control signal TEST2 control signal TEST3 control signal

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[Procedure amendment]

[Submission date] December 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Reference numeral 18 is a sense amplifier, which is an I / O line.
15a, Amplifies the minute signal read to the inverted I / O line 15b. The data signal amplified by the sense amplifier 18 is clocked by the data latch 19 by the control signal CLK4 and then output to the data bus 7 through the driver 20. Reference numeral 21 is a write driver, and the data bus 7
Data is written from the I / O line 15a, the inverted I / O line 15b, and the Y selector 16 to the memory cell 9.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

As shown in the timing chart of FIG. 10, the conventional microcomputer having such a memory has a control signal at φ 2 of each bus cycle.
If the #CS signal 22 and the R / # W signal 24 are input to the address / control signal latch 19 by the time the address is fetched by CLK2, memory reading is possible. However, since the above-described operation is synchronized with the clock, it is not possible to accurately evaluate the time actually required to read the data from the internal memory unit 4.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

That is, in bus cycle 1, the address AA
Is the setup time T rather than the rise of the control signal CLK2
Input to the internal memory unit 4 at the time before _Ast.2 , and the data (AA) for this is delayed by the delay time T from the rise of the control signal CLK4.
Since it is output at the time after _Dd1.4 , the result is the address.
The delay time from the input of AA to the output of data (AA) is
It becomes T _(AMD1) φ which is the sum of φ3 time.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

However, in bus cycle 2, the address BB
Is the setup time T rather than the fall of the control signal CLK2
_The data (BB) corresponding to this is input to the internal memory unit 4 at the time before _Ast.3, but is output at the time after the delay time T _Dd1.4 as in the case of the bus cycle 1. Therefore, the delay time from the input of address BB to the output of data (BB) is both
T _(AMD2) φ, which is the sum of the person and the time of φ3. In addition,
In the bus cycle 3, the built-in memory unit 4 cannot take in the address CC.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

The control signal TEST1 is the address latch 100, 10
It is a signal which causes the control signal latch 13 and the data latch 19 to constantly receive the input signal during the period of each bus cycle.
OR signal of this control signal TEST1 and conventional control signal CLK2
The control signal ADL1 is newly generated by the OR gate 27, and the control signal TEST1 and the conventional control signal CLK4 are combined.
The control signal DTL1 is newly generated by generating the OR signal in the OR gate 28 .

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

However, in the bus cycle T1, the control signal TE
Since the control signal ADL1 becomes "H" by setting ST1 to "H", the address latches 100, 101, control signal latch 13
Outputs the address on the address bus 6 and inputs it to the memory 26 regardless of the clock. As a result, the data corresponding to the input address is read from the memory 26, but the control signal TEST1 is set to "H" to control the signal.
Since DTL1 becomes "H", and outputs the output data outputted from the memory 26 regardless data latch 19 also has a clock to <br/> data bus 7.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Change

[Correction content]

However, in the bus cycle T2, the control signal TE
By setting ST1 to "L" and the control signal TEST2 to "H", the control signal ADL2 which is the output signal of the OR gate 29 is set to "L".
H ”, and the transmission gate 32 becomes a node
Shorts 30 and 31, so address latches 100, 101,
The control signal latch 13 outputs the address on the address bus 6 regardless of the clock and outputs it from the node 30 to the node 31 via the transmission gate 32 and to the data latch 19 . This allows address latches 100, 1
01, the address output from the control signal latch 13 is directly output to the data latch 19 and output to the data bus 7.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] 0057

[Correction method] Change

[Correction content]

In FIG. 6, in the bus cycle T3, the control signal TEST1 is "H", the control signal TEST3 is "L", and the control signal which is the output signal of the OR gate 27.
ADL1 becomes "H" regardless of the clock and OR
Control signal DTL2, which is the output signal of gate 33, is a bus cycle
It becomes "H" only at φ4 of T3. In other words, the address latches 100, 101 and the control signal latch 13 always output the address from the address bus 6 regardless of the clock.
However , the data latch 19 operates similarly to the conventional example. Therefore, the delay time for reading the data from the memory 26 to the data latch 19 becomes a prescribed delay time T _Dd1.4 synchronized with the clock, and from the time when the address is determined until the corresponding data is read from the memory 26. The time T _(AM) φ of can be obtained.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Name of item to be corrected] 0058

[Correction method] Change

[Correction content]

On the other hand, in the bus cycle T4, the control signal TEST
1 is "L" and the control signal TEST3 is "H", and the control signal ADL1 which is the output signal of the OR gate 27 becomes "H" only in φ2 of the bus cycle T4.
The control signal DTL2 which is the output signal of the OR gate 33 becomes "H" regardless of the clock. In other words, the address latch
100, 101, control signal latch 13 operates in the same manner as the conventional example, and data latch 19 operates in the memory regardless of the clock.
The data read from 26 is constantly output and output to the data bus 7. Therefore, from the address bus 6 to the address latch
100, 101, The setup time until the control signal latch 13 latches the address and inputs it to the memory 26 is the specified setup time T _Ast.3 synchronized with the clock.
The data read delay time T _(MD) φ from the memory 26 to the data latch 19 can be obtained.

[Procedure Amendment 12]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

Front page continuation (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location G11C 29/00 303 H 6741-5L H03K 19/00 B 8941-5J

Claims (3)

[Claims] 1. A logic circuit which logically processes an input signal and outputs a resulting signal, and a signal which should be input to the logic circuit is latched in synchronization with a first clock signal and input to the logic circuit. And a second latch circuit for latching the signal output from the logic circuit in synchronization with a second clock signal and outputting the latched signal. A signal and a control signal different from this are input, and when the control signal is significant, the logic is immediately input regardless of the first clock signal when a signal to be input to the logic circuit is given. The first latch so that a signal to be input to a circuit and to be input to the logic circuit when the control signal is not significant is latched in synchronization with the first clock signal and input to the logic circuit. A circuit for controlling a H circuit, the second clock signal and the control signal being input, and when the control signal is significant, the first signal is output when the signal output from the logic circuit is given. The second latch circuit is configured to immediately output regardless of the clock signal, and to latch and output the signal output from the logic circuit in synchronization with the first clock signal when the control signal is not significant. By controlling the control signal to be significant so that the time required from the time when the signal is applied to the first latch circuit to the time when the signal is output from the second latch circuit is increased. A semiconductor logic device characterized by being evaluated. 2. A logic circuit which logically processes an input signal and outputs a resulting signal, and a signal which should be input to the logic circuit is latched in synchronization with a first clock signal and input to the logic circuit. And a second latch circuit for latching the signal output from the logic circuit in synchronization with a second clock signal and outputting the latched signal. A signal and a control signal different from this are input, and when the control signal is significant, the logic is immediately input regardless of the first clock signal when a signal to be input to the logic circuit is given. The first latch so that a signal to be input to a circuit and to be input to the logic circuit when the control signal is not significant is latched in synchronization with the first clock signal and input to the logic circuit. And a short-circuit means for directly applying the output signal of the first latch circuit to the second latch circuit when the control signal is significant, thereby making the control signal significant. Thus, the time required from the time when the signal is applied to the first latch circuit to the time when the signal is output and the time when the signal is applied to the second latch circuit to the time when the signal is output are evaluated. A semiconductor logic device characterized by the above. 3. A logic circuit which logically processes an input signal and outputs a resulting signal, and a signal which should be input to the logic circuit is latched in synchronization with a first clock signal and input to the logic circuit. And a second latch circuit for latching the signal output from the logic circuit in synchronization with a second clock signal and outputting the latched signal. A signal and a first control signal different from the signal, and when the first control signal is significant, the first clock signal is supplied when a signal to be input to the logic circuit is given. Regardless, the signal is input to the logic circuit immediately, and when the first control signal is not significant, the signal to be input to the logic circuit is latched in synchronization with the first clock signal and input to the logic circuit. Let me As described above, means for controlling the first latch circuit, the second clock signal and a second control signal different from the second clock signal are input, and if the second control signal is significant, the logic circuit outputs When the output signal is given, the signal is immediately output regardless of the first clock signal, and when the second control signal is not significant, the signal output from the logic circuit is set to the first clock signal. Means for controlling the second latch circuit so as to latch and output in synchronization with the first control signal by making the first control signal significant.
The time required from the time when a signal is applied to the latch circuit to the time when the signal is output from the second latch circuit in synchronization with the second clock, and the second control signal is significantly changed. To evaluate the time required from the time when the signal is latched in the first latch circuit to the time when the signal is output from the second latch circuit in synchronization with the first clock signal. A semiconductor logic device characterized by being made.