JPH0648873Y2 - マルチチップ実装構造 - Google Patents

マルチチップ実装構造

Info

Publication number
JPH0648873Y2
JPH0648873Y2 JP3719589U JP3719589U JPH0648873Y2 JP H0648873 Y2 JPH0648873 Y2 JP H0648873Y2 JP 3719589 U JP3719589 U JP 3719589U JP 3719589 U JP3719589 U JP 3719589U JP H0648873 Y2 JPH0648873 Y2 JP H0648873Y2
Authority
JP
Japan
Prior art keywords
wiring
chip
substrate
pad
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3719589U
Other languages
English (en)
Japanese (ja)
Other versions
JPH02127040U (enrdf_load_stackoverflow
Inventor
良一 落合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3719589U priority Critical patent/JPH0648873Y2/ja
Publication of JPH02127040U publication Critical patent/JPH02127040U/ja
Application granted granted Critical
Publication of JPH0648873Y2 publication Critical patent/JPH0648873Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
JP3719589U 1989-03-30 1989-03-30 マルチチップ実装構造 Expired - Lifetime JPH0648873Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3719589U JPH0648873Y2 (ja) 1989-03-30 1989-03-30 マルチチップ実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3719589U JPH0648873Y2 (ja) 1989-03-30 1989-03-30 マルチチップ実装構造

Publications (2)

Publication Number Publication Date
JPH02127040U JPH02127040U (enrdf_load_stackoverflow) 1990-10-19
JPH0648873Y2 true JPH0648873Y2 (ja) 1994-12-12

Family

ID=31544087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3719589U Expired - Lifetime JPH0648873Y2 (ja) 1989-03-30 1989-03-30 マルチチップ実装構造

Country Status (1)

Country Link
JP (1) JPH0648873Y2 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114361063B (zh) * 2021-11-24 2024-12-13 苏州科阳半导体有限公司 基板键合方法及基板

Also Published As

Publication number Publication date
JPH02127040U (enrdf_load_stackoverflow) 1990-10-19

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