JPH0638435B2 - Semiconductor Mold Method - Google Patents
Semiconductor Mold MethodInfo
- Publication number
- JPH0638435B2 JPH0638435B2 JP59187572A JP18757284A JPH0638435B2 JP H0638435 B2 JPH0638435 B2 JP H0638435B2 JP 59187572 A JP59187572 A JP 59187572A JP 18757284 A JP18757284 A JP 18757284A JP H0638435 B2 JPH0638435 B2 JP H0638435B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- lead frame
- molding
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［発明の技術分野］ 本発明は半導体素子の樹脂封止を行なう半導体モールド
方法に係り、特にモールド外形寸法が小さく、リード幅
が狭く、リード厚さが薄く、さらに実装時のリード長さ
が短い小型の半導体装置のモールド方法に関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor molding method for resin-sealing a semiconductor element, and particularly to a small mold outer dimension, a narrow lead width, a thin lead thickness, and further mounting. The present invention relates to a method of molding a small semiconductor device having a short lead length.
［発明の技術的背景］ 従来、樹脂封止型の半導体装置は、モールド後は例えば
第６図に示すような状態となっている。すなわち、多数
個の半導体素子載置部分を有するリードフレーム11に半
導体素子に固定し、ワイヤボンディングで配線を行なっ
た後、金型によりモールド樹脂12で封止をしたものであ
る。ここで、13,14,15はそれぞれ外部に取り出されたリ
ードを示す。[Technical Background of the Invention] Conventionally, a resin-encapsulated semiconductor device is in a state, for example, as shown in FIG. 6 after molding. That is, a semiconductor device is fixed to a lead frame 11 having a large number of semiconductor device mounting portions, wiring is performed by wire bonding, and then sealed with a mold resin 12 by a mold. Here, 13, 14 and 15 respectively indicate leads taken out to the outside.
第７図及び第８図はそれぞれモールド金型にリードフレ
ーム11を挿入し、リード13〜15を上金型21、下金型22で
挟持した時の断面を示すものである。下金型22には、挟
持の際、リード変形を起こさないようにリード13〜15が
入るための凹部23が形成されている。この凹部23の幅は
第７図に示すようにリード幅よりも寸法ｔだけ広くなっ
ており、リード13〜15が入りやすくなっている。また、
第８図に於いても凹部24が形成されている。この凹部24
の入口はリード幅よりも寸法ｔだけ広いが、内部になる
につれて狭く、底部ではリード幅と略同寸法となってい
る。ｔ寸法は、リードフレーム11の長さや板厚さによっ
て種々異なるが、例えばリードフレーム11の長さ160m
m、板厚0.125mmのとき、0.05〜0.10mmとしている。FIG. 7 and FIG. 8 show cross sections when the lead frame 11 is inserted into the molding die and the leads 13 to 15 are sandwiched between the upper die 21 and the lower die 22. The lower die 22 is formed with a recess 23 into which the leads 13 to 15 are inserted so as not to deform the leads when being clamped. The width of the recess 23 is wider than the lead width by a dimension t as shown in FIG. 7, so that the leads 13 to 15 can be easily inserted therein. Also,
In FIG. 8 as well, the recess 24 is formed. This recess 24
The inlet is wider than the lead width by a dimension t, but is narrower toward the inside, and has a dimension substantially the same as the lead width at the bottom. The t dimension varies depending on the length and plate thickness of the lead frame 11, but for example, the length of the lead frame 11 is 160 m.
When the thickness is m and the plate thickness is 0.125 mm, it is 0.05 to 0.10 mm.
［背景技術の問題点］ 上記のように従来のモールド金型に於いては、下金型22
の凹部23,24はリード13〜15が入り易いようにリード幅
より２ｔだけ広くしている。このため、第９図に平面図
で、第10図に断面図で示すように、凹部24とリード13〜
15との隙間部分に樹脂が流れ、その結果樹脂ばり25とな
ってリード13〜15の側面部に固着してしまう。リード13
〜15に樹脂ばり25が固着すると、リード13〜15への半田
付けが全周に渡って十分に行えないことになる。すなわ
ち、半導体装置の実装時に於いて、半田付けが十分に行
えない欠点があった。[Problems of background art] As described above, in the conventional mold, the lower mold 22
The recesses 23 and 24 are wider than the lead width by 2t so that the leads 13 to 15 can be easily inserted therein. Therefore, as shown in the plan view of FIG. 9 and the sectional view of FIG.
The resin flows in the gap between the leads 15 and 15 and becomes the resin flash 25, which is fixed to the side surfaces of the leads 13 to 15. Lead 13
If the resin burr 25 is fixed to 15 to 15, soldering to the leads 13 to 15 cannot be sufficiently performed over the entire circumference. That is, there is a drawback that soldering cannot be sufficiently performed when mounting the semiconductor device.
このように、従来は、リードの上下面の樹脂ばりの発生
は上金型21、下金型22で強くリード部を挟持することに
より防止することができたが、リード側面の樹脂ばり25
の発生は防止することができなかった。As described above, conventionally, the occurrence of resin flash on the upper and lower surfaces of the lead could be prevented by strongly pinching the lead portion with the upper mold 21 and the lower mold 22, but the resin flash on the side surface of the lead 25
Could not be prevented.
また、樹脂ばり25を除去しようとしても、この樹脂ばり
25がリード13〜15の側面に固着しているため、非常に取
れにくく、根本まで完全に除去することができなかっ
た。Even if you try to remove the resin flash 25,
Since 25 was firmly attached to the side surface of the leads 13 to 15, it was very difficult to remove it, and the root could not be completely removed.
また、樹脂ばり25を除去しようとしても、この樹脂ばり
25がリード13〜15の側面に固着しているため、非常に取
れにくく、根本まで完全に除去することができなかっ
た。Even if you try to remove the resin flash 25,
Since 25 was firmly attached to the side surface of the leads 13 to 15, it was very difficult to remove it, and the root could not be completely removed.
特に、小型の半導体装置の場合、リードの長さが非常に
短く、リードの根本まで半田付けする必要があるが、樹
脂ばり除去が不十分であるため、リード13〜15への半田
付けが不完全となり不良品となることがあった。In particular, in the case of a small semiconductor device, the length of the lead is very short and it is necessary to solder to the root of the lead.However, since the resin flash removal is insufficient, it is not possible to solder to the leads 13 to 15. It became perfect and sometimes became a defective product.
［発明の目的］ 本発明は上記実情に鑑みてなされたもので、その目的
は、リードの側面部への樹脂ばりの発生を防止し、半導
体装置の実装時に於いて半田付けを良好に行なうことが
でき、不良品の発生を防止することのできる半導体モー
ルド方法を提供することにある。[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the occurrence of resin burrs on the side surfaces of leads and to perform good soldering when mounting a semiconductor device. It is an object of the present invention to provide a semiconductor molding method capable of preventing the occurrence of defective products.
［発明の概要］ 本発明に係る半導体モールド方法は、モールド金型の上
下金型に形成されるリード挟持部分の断面形状を例えば
台形とし、これと同形状で同寸法にリードフレームのリ
ード部分を成形することにより、モールド時の金型とリ
ードとの隙間を無くして、リードの側面に於ける樹脂ば
りの発生を防止するものである。[Summary of the Invention] In the semiconductor molding method according to the present invention, the cross-sectional shape of the lead holding portions formed in the upper and lower molds of the molding die is, for example, a trapezoid, and the lead portions of the lead frame are formed in the same shape and the same size. By molding, the gap between the die and the lead at the time of molding is eliminated, and the occurrence of resin burrs on the side surface of the lead is prevented.
［発明の実施例］ 以下、図面を参照して本発明の一実施例を説明する。第
１図はリードフレーム31に於けるリード32,33部の断面
形状を示すもので、このリード32,33部はそれぞれ逆台
形状をしている。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional shape of the leads 32 and 33 in the lead frame 31, and the leads 32 and 33 have an inverted trapezoidal shape.
第２図はモールド金型のリード挟持部の断面図を示すも
ので、34は上金型、35は下金型である。下金型35にはリ
ード32,33を入れるためのリード32,33と同形状で、同寸
法の凹部36が形成されている。FIG. 2 is a sectional view of the lead holding portion of the molding die, where 34 is an upper die and 35 is a lower die. The lower mold 35 has a recess 36 having the same shape and the same size as the leads 32, 33 for receiving the leads 32, 33.
すなわち、本発明に於いては、先ず、第１図に示したよ
うに、リードフレーム31のリード32,33部を下金型35の
凹部36の断面と同形状に成形する。次に、リードフレー
ム31に半導体素子を固定し、ワイヤボンディングで配線
を行なう。しかる後、モールド金型にリードフレーム31
を挿入し、第２図に示したように凹部36でリード32,33
部を挟持した状態でモールドを行なうものである。That is, in the present invention, first, as shown in FIG. 1, the leads 32 and 33 of the lead frame 31 are formed into the same shape as the cross section of the recess 36 of the lower mold 35. Next, the semiconductor element is fixed to the lead frame 31 and wiring is performed by wire bonding. Then, the lead frame 31 is attached to the mold.
2 and insert the leads 32, 33 in the recess 36 as shown in FIG.
Molding is performed with the parts held in between.
上記方法によれば、 (1)リード32,33を凹部36,36で隙間無く挟持することが
できるため、リード32,33部に樹脂ばりが発生すること
がなく、このため第３図乃至第５図に示すようにリード
部分全体に渡って半田37付けを良好に行なうことができ
る。特に、これは小型の半導体装置に有効である。According to the above method, (1) since the leads 32, 33 can be sandwiched between the recesses 36, 36 without a gap, resin burrs do not occur at the leads 32, 33, and therefore, FIG. As shown in FIG. 5, the solder 37 can be satisfactorily attached over the entire lead portion. In particular, this is effective for a small semiconductor device.
(2)また、リード32,33の断面形状が台形であるので、モ
ールド金型で挟持するときに、リード32,33を容易に挿
入することができる。従って、リード32,33をモールド
金型で潰したり、変形させたりすることがない。(2) Further, since the leads 32 and 33 have a trapezoidal sectional shape, the leads 32 and 33 can be easily inserted when sandwiched by the molding die. Therefore, the leads 32 and 33 are not crushed or deformed by the molding die.
(3)従来困難であったリード32,33の側面の樹脂ばり取り
に要する費用が不要となった。(3) The cost for removing the resin deburring on the side surfaces of the leads 32, 33, which was difficult in the past, is no longer required.
上記リードフレーム31のリード32,33部を第１図に示し
た形状に成形する工程は、従来のリードフレーム順送り
金型に、リード成形工程を一部追加することにより実現
できるので、特別な工程は必要としない。The step of molding the leads 32 and 33 of the lead frame 31 into the shape shown in FIG. 1 can be realized by adding a part of the lead molding step to the conventional lead frame progressive die, so a special step Does not need.
第８図に示したモールド金型の場合は、凹部24が逆台形
状であるので上記リードフレーム31の成形のみで本発明
のモールド方法となるが、第７図に示したモールド金型
の場合は、凹部23が方形状であるので第８図と同形状に
変更する必要がある。In the case of the molding die shown in FIG. 8, since the recess 24 has an inverted trapezoidal shape, the molding method of the present invention can be performed only by molding the lead frame 31, but in the case of the molding die shown in FIG. Since the concave portion 23 has a rectangular shape, it is necessary to change it to the same shape as in FIG.
尚、上記実施例に於いては、リード32,33の断面形状を
台形としたが、これに限定するものではなく、例えば半
月形状、三角形状とし、これに合わせてモールド金型の
形状を変更すれば同様の効果が得られるものである。In the above embodiment, the cross-sectional shape of the leads 32, 33 is trapezoidal, but is not limited to this, for example, a half-moon shape, a triangular shape, and the shape of the molding die is changed accordingly. Then, the same effect can be obtained.
［発明の効果］ 以上のように本発明によれば、リードの側面部への樹脂
ばりの発生を防止できるので、半導体装置の実装時に於
いて半田付けを良好に行なうことができ、不良品の発生
を防止することができる。[Advantages of the Invention] According to the present invention as described above, it is possible to prevent the occurrence of resin burrs on the side surfaces of the leads, so that it is possible to perform good soldering when mounting a semiconductor device, and Occurrence can be prevented.
第１図は本発明の一実施例に係るリードフレームのリー
ド部の断面図、第２図は同じくモールド金型のリード挟
持部の断面図、第３図は本発明の方法により得られた半
導体装置の半田付け状態を示す断面図、第４図は同じく
正面図、第５図は同じく側面図、第６図は従来の半導体
装置のモールド後の状態を示す斜視図、第７図及び第８
図はそれぞれ従来のモールド金型のリード挟持部の断面
図、第９図は第８図のモールド金型でモールドしたとき
の平面図、第10図は第９図のＢ−Ｂ′矢視断面図であ
る。 31……リードフレーム、32,33……リード、34……上金
型、35……下金型、36……凹部、37……半田。FIG. 1 is a sectional view of a lead portion of a lead frame according to an embodiment of the present invention, FIG. 2 is a sectional view of a lead holding portion of the same molding die, and FIG. 3 is a semiconductor obtained by the method of the present invention. Sectional view showing the soldered state of the device, FIG. 4 is the same front view, FIG. 5 is the same side view, and FIG. 6 is a perspective view showing the state of the conventional semiconductor device after molding, FIGS.
Each of the figures is a sectional view of a lead holding portion of a conventional molding die, FIG. 9 is a plan view when molded by the molding die of FIG. 8, and FIG. 10 is a sectional view taken along the line BB ′ of FIG. It is a figure. 31 …… lead frame, 32,33 …… lead, 34 …… upper mold, 35 …… lower mold, 36 …… recess, 37 …… solder.
Claims (1)
ド金型により挟持し、この状態で、前記リードフレーム
上に固定された半導体素子を樹脂封止する半導体モール
ド方法に於いて、 前記上下のモールド金型の一方に形成された、他方のモ
ールド金型との接触面より徐々に狭まる断面形状を有す
るリード挟持部と同一の断面形状および大きさを持っ
て、前記リードフレームのリード部を成形する工程と、 前記リードフレームのリード部を、前記上下のモールド
金型の一方に形成されたリード挟持部に挿入して樹脂封
止を行なう工程と からなることを特徴とする半導体モールド方法。1. A semiconductor molding method, wherein a lead portion of a lead frame is sandwiched by upper and lower mold dies, and in this state, a semiconductor element fixed on the lead frame is resin-sealed. The lead portion of the lead frame is formed so as to have the same cross-sectional shape and size as the lead sandwiching portion formed in one of the molds and having a cross-sectional shape that gradually narrows from the contact surface with the other mold. A semiconductor molding method comprising: a step of inserting a lead portion of the lead frame into a lead holding portion formed in one of the upper and lower molding dies to perform resin sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59187572A JPH0638435B2 (en) | 1984-09-07 | 1984-09-07 | Semiconductor Mold Method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59187572A JPH0638435B2 (en) | 1984-09-07 | 1984-09-07 | Semiconductor Mold Method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6165460A JPS6165460A (en) | 1986-04-04 |
| JPH0638435B2 true JPH0638435B2 (en) | 1994-05-18 |
Family
ID=16208442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59187572A Expired - Lifetime JPH0638435B2 (en) | 1984-09-07 | 1984-09-07 | Semiconductor Mold Method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0638435B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664446A (en) * | 1979-10-29 | 1981-06-01 | Peshitsuku:Kk | Method of molding synthetic resin insert for metal terminal, metal terminal and mold |
-
1984
- 1984-09-07 JP JP59187572A patent/JPH0638435B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6165460A (en) | 1986-04-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |