JP2560194B2 - Method of manufacturing packaged semiconductor device - Google Patents
Method of manufacturing packaged semiconductor deviceInfo
- Publication number
- JP2560194B2 JP2560194B2 JP5121199A JP12119993A JP2560194B2 JP 2560194 B2 JP2560194 B2 JP 2560194B2 JP 5121199 A JP5121199 A JP 5121199A JP 12119993 A JP12119993 A JP 12119993A JP 2560194 B2 JP2560194 B2 JP 2560194B2
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- bent
- mold
- semiconductor device
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Bending Of Plates, Rods, And Pipes (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップの部分を
合成樹脂製のモールド部にてパッケージして成る形式の
いわゆるパッケージ型半導体装置のうち、面実装に適す
るように構成したパッケージ型半導体装置の改良に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package type semiconductor device which is suitable for surface mounting among so-called package type semiconductor devices of the type in which a semiconductor chip part is packaged in a synthetic resin mold part. Related to the improvement of.
【０００２】[0002]
【従来の技術】従来、面実装に適するパッケージ型半導
体装置では、その各リード端子を、合成樹脂製モールド
部の側面から突出し、各リード端子のうちモールド部か
ら突出する部分を、モールド部の底面と同一平面に沿う
ように屈曲する構成にしているから、モールド部から突
出する各リード端子の占有面積が大きくて、プリント基
板に対する高密度実装を妨げると共に、リード端子の強
度が低い等の不具合があった。2. Description of the Related Art Conventionally, in a package type semiconductor device suitable for surface mounting, each lead terminal is projected from a side surface of a synthetic resin mold part, and a portion of each lead terminal projecting from the mold part is a bottom surface of the mold part. Since it is configured to bend along the same plane as, the area occupied by each lead terminal protruding from the mold portion is large, which hinders high-density mounting on the printed circuit board, and the lead terminal has low strength. there were.
【０００３】そこで、先行技術としての特開昭５７−１
７６７５１号公報は、図７及び図８に示すように、半導
体チップ１に対して接続した左右一対のリード端子２，
３を、合成樹脂製のモールド部４内における内部リード
端子部２ａ，３ａと、モールド部４における底面４ａに
露出してこの底面４ａに沿って延びる外部リード端子部
２ｂ，３ｂとに段状に屈曲した構成にすることによっ
て、前記の不具合を解消することを提案している。Therefore, as a prior art, Japanese Patent Laid-Open No. 57-1
76751 discloses a pair of left and right lead terminals 2 connected to a semiconductor chip 1, as shown in FIGS.
3 is stepped into internal lead terminal portions 2a, 3a in the synthetic resin mold portion 4 and external lead terminal portions 2b, 3b exposed on the bottom surface 4a of the mold portion 4 and extending along the bottom surface 4a. It is proposed to eliminate the above-mentioned inconvenience by making a bent structure.
【０００４】[0004]
【発明が解決しようとする課題】しかし、この先行技術
における半導体装置においては、両リード端子２，３
を、モールド部４内において内部リード端子部２ａ，３
ａと、前記モールド部４の底面４ａに露出してこの底面
４ａに沿って延びる外部リード端子部２ｂ，３ｂとに段
状に屈曲するに際して、その屈曲部２ｃ，３ｃには、必
然的に比較的大きい半径Ｒの丸角状に形成されることに
なるので、前記モールド部４の成形に際して、前記屈曲
部２ｃ，３ｃの外周面と、モールド部成形用キャビティ
ーの内面との間に、先窄まりの狭い隙間ができ、この先
窄まりの狭い隙間に合成樹脂が充填されることにより、
前記モールド部４のうち、前記両リード端子２，３にお
ける丸角状屈曲部２ｃ，３ｃに該当する箇所における部
分４ｄ，４ｅは、バリ状のきわめて薄肉の状態になる。However, in the semiconductor device in this prior art, both lead terminals 2 and 3 are used.
In the mold part 4 inside lead terminal parts 2a, 3
a and the external lead terminal portions 2b and 3b exposed on the bottom surface 4a of the mold portion 4 and extending along the bottom surface 4a, the bent portions 2c and 3c are inevitably compared with each other. Since it is formed in a rounded corner shape with a relatively large radius R, when molding the mold portion 4, a tip is formed between the outer peripheral surfaces of the bent portions 2c and 3c and the inner surface of the mold portion molding cavity. A narrow gap is created, and by filling this narrow gap with synthetic resin,
Portions 4d and 4e of the molded portion 4 corresponding to the rounded corner-shaped bent portions 2c and 3c of the lead terminals 2 and 3 have a flash-like extremely thin state.
【０００５】従って、前記モールド部４の成形後におけ
る各種の取扱いに際して、モールド部４のうち前記のよ
うに薄肉状になる部分４ｄ，４ｅに、合成樹脂の剥離や
欠けが発生して、両外部リード端子部２ｂ，３ｂと、モ
ールド部４との境界線が、図８に二点鎖線で示すよう
に、ギザギザになるから、商品価値の低下を招来すると
共に、各リード端子２，３における外部リード端子部２
ｂ，３ｂのモールド部４からの露出寸法（Ｓ）が、可成
り大きく不揃いになると言う問題を招来するのであっ
た。Therefore, during various handling after the molding of the molding portion 4, the thin portions 4d and 4e of the molding portion 4 are peeled or chipped off from the synthetic resin to cause both outsides. The boundary line between the lead terminal portions 2b and 3b and the mold portion 4 is notched as shown by the chain double-dashed line in FIG. Lead terminal 2
This causes a problem that the exposed dimensions (S) of the mold portions 4b and 3b from the mold portion 4 are considerably large and uneven.
【０００６】本発明は、このような問題を招来すること
がないようにした製造方法を提供することを技術的課題
とするものである。An object of the present invention is to provide a manufacturing method which does not cause such a problem.
【０００７】[0007]
【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「少なくとも、半導体チップに複数本
のリード端子を接続する工程と、この各リード端子を、
内部リード端子部と外部リード端子部とに段状に屈曲す
るフォーミング工程と、前記半導体チップの部分を、合
成樹脂製のモールド部にて、各リード端子における外部
リード端子部が当該モールド部の底面に露出してこの底
面に沿って延びるようにパッケージする工程とを有する
パッケージ型半導体装置の製造方法。」において、「前
記フォーミング工程が、リード端子を内部リード端子部
と外部リード端子部とに段状に屈曲するときに、その屈
曲部の内周面を、押圧にて当該屈曲部の外周面が半径の
小さい角張った形状になるようにを押圧して潰し変形す
る工程を含んでいることを特徴とする。」ものである。In order to achieve this technical object, the present invention provides "at least a step of connecting a plurality of lead terminals to a semiconductor chip and each of these lead terminals,
Forming step in which the internal lead terminal portion and the external lead terminal portion are bent in a stepwise manner, and the semiconductor chip portion is molded with a synthetic resin, and the external lead terminal portion of each lead terminal is a bottom surface of the molded portion. And a method of manufacturing a packaged semiconductor device, which includes the step of exposing the package and extending it along the bottom surface. In the "forming step, when the lead terminal is bent stepwise into the internal lead terminal portion and the external lead terminal portion, the inner peripheral surface of the bent portion is pressed, and the outer peripheral surface of the bent portion is pressed. It is characterized by including a step of pressing and deforming so as to have an angular shape with a small radius. ”
【０００８】[0008]
【作 用】このようにすることにより、内部リード端
子部と外部リード端子部との屈曲部における外周面を、
半径の小さい角張った形状にすることができるから、モ
ールド部の成形に際して、各リード端子のうち内部リー
ド端子部は、モールド部成形用キャビティーにおける底
面から当該キャビティー内に向って直接に立ち上がった
状態になり、各リード端子における屈曲部の外周面と、
モールド部形成用キャビティーの底面との間に、前記先
行技術の場合のように、先窄まりの隙間が形成されるこ
とを防止できるか、或いは、先窄まりの隙間をきわめて
小さくすることができる。[Operation] By doing this, the outer peripheral surface at the bent portion of the internal lead terminal portion and the external lead terminal portion is
Since it is possible to form an angular shape with a small radius, when molding the mold part, the internal lead terminal part of each lead terminal rises directly from the bottom surface of the mold part molding cavity into the cavity. And the outer peripheral surface of the bent portion of each lead terminal,
As in the case of the above-mentioned prior art, it is possible to prevent the formation of a tapered gap with the bottom of the cavity for forming the mold portion, or to make the tapered gap extremely small. it can.
【０００９】その結果、モールド部のうち前記各リード
端子の屈曲部に該当する箇所における部分が、バリ状の
薄肉になることを防止できるか、バリ状の薄肉になるこ
とをきわめて小さくすることができるのである。As a result, it is possible to prevent the portion of the molded portion corresponding to the bent portion of each lead terminal from becoming thin in the shape of burrs, or to make the thinning in the shape of burrs extremely small. You can do it.
【００１０】[0010]
【発明の効果】従って、本発明によると、モールド部の
うち各リード端子の屈曲部に該当する箇所における部分
に、合成樹脂の剥離や欠けが発生することを確実に低減
できるから、商品価値を向上することができると共に、
各リード端子における外部リード端子部のモールド部か
らの露出寸法が不揃いになることを大幅に改善できる効
果を有する。Therefore, according to the present invention, it is possible to reliably reduce the occurrence of peeling or chipping of the synthetic resin in the portion of the molded portion corresponding to the bent portion of each lead terminal, and thus the commercial value is obtained. Can be improved,
There is an effect that it is possible to greatly improve the unevenness of the exposed dimension of the external lead terminal portion of each lead terminal from the molded portion.
【００１１】[0011]
【実施例】以下、本発明の実施例を、ダイオードに適用
した場合の図面について説明する。図１及び図２は、本
発明の方法によって製造したダイオードを示す。この図
において符号１２，１３は、半導体チップ１１の上下両
面に接続した左右一対のリード端子を示し、また、符号
１４は、前記半導体チップ１１の全体及び両リード端子
１２，１３の一部を封止するようにした合成樹脂製のモ
ールド部を示す。Embodiments of the present invention will now be described with reference to the drawings when applied to a diode. 1 and 2 show a diode manufactured by the method of the present invention. In this figure, reference numerals 12 and 13 denote a pair of left and right lead terminals connected to the upper and lower surfaces of the semiconductor chip 11, and a reference numeral 14 seals the entire semiconductor chip 11 and a part of both the lead terminals 12 and 13. The mold part made from synthetic resin which was made to stop is shown.
【００１２】前記両リード端子１２，１３は、モールド
部１４内において、内部リード端子部１２ａ，１３ａ
と、前記モールド部１４の底面１４ａに露出してこの底
面１４ａに沿ってモールド部１４の側面１４ｂ，１４ｃ
より突出するように延びる外部リード端子部１２ｂ，１
３ｂとに、段状に屈曲されている。そして、その製造に
際しては、先づ、半導体チップ１１の両面に 両リード
端子１２，１３を接合したのち、両リード端子１２，１
３を、図３及び図４に示すように、一対のフォーミング
金型Ａ，Ｂによる挟み付けにより、内部リード端子部１
２ａ，１３ａと外部リード端子部１２ｂ，１３ｂとに段
状に屈曲するようにフォーミングするのである。The two lead terminals 12 and 13 are provided in the mold portion 14 with internal lead terminal portions 12a and 13a.
And exposed on the bottom surface 14a of the mold portion 14 and along the bottom surface 14a, side surfaces 14b and 14c of the mold portion 14.
External lead terminal portions 12b, 1 extending so as to project further
3b, and is bent stepwise. In manufacturing the same, first, both lead terminals 12 and 13 are joined to both surfaces of the semiconductor chip 11, and then both lead terminals 12 and 1 are joined.
As shown in FIGS. 3 and 4, the internal lead terminal portion 1 is sandwiched by a pair of forming dies A and B.
2a, 13a and the external lead terminal portions 12b, 13b are formed so as to be bent stepwise.
【００１３】このフォーミングに際して、前記一対のフ
ォーミング金型Ａ，Ｂのうち、一方のフォーミング金型
Ａの下面に、突起部ａを一体的に造形して、この突起部
ａによって、前記リード端子１２，１３における屈曲部
１２ｃ，１３ｃの内周面を押圧して潰し変形する。する
と、当該屈曲部１２ｃ，１３ｃの内周面に凹み１２
ｃ′，１３ｃ′ができて、内部リード端子部１２ａ，１
３ａと外部リード端子部１２ｂ，１３ｂとを、この凹み
１２ｃ′，１３ｃ′の存在によって、例えば、半径Ｒが
０．０３mm以下の小さい半径で屈曲することができるか
ら、この屈曲部１２ｃ，１３ｃにおける外周面を、半径
の小さい角張った形状にすることができるのである。In this forming, a protrusion a is integrally formed on the lower surface of one of the pair of forming dies A and B, and the lead terminal 12 is formed by the protrusion a. , 13, the inner peripheral surfaces of the bent portions 12c, 13c are pressed and crushed and deformed. Then, the recess 12 is formed on the inner peripheral surface of the bent portion 12c, 13c.
c ', 13c' are formed, and internal lead terminal portions 12a, 1
3a and the external lead terminal portions 12b and 13b can be bent with a small radius of, for example, 0.03 mm or less due to the presence of the recesses 12c 'and 13c'. The outer peripheral surface can have an angular shape with a small radius.
【００１４】従って、前記フォーミング後において、モ
ールド部１４を成形するに際して、図５及び図６に示す
ように、当該モールド部１４の底面１４ａにおいて分割
した一対の成形用金型Ｃ，Ｄを使用し、この両成形用金
型Ｃ，Ｄの間に、両リード端子１２，１３を挟んだと
き、前記リード端子１２，１３のうち内部リード端子部
１２ａ，１３ａは、モールド部成形用キャビティーＥに
おける底面ｅから当該キャビティーＥ内に向って直接に
立ち上がった状態になり、リード端子１２，１３におけ
る屈曲部１２ｃ，１３ｃの外周面と、モールド部形成用
キャビティーＥの底面ｅとの間に、前記先行技術の場合
のように、先窄まりの隙間が形成されることを防止でき
るか、先窄まりの隙間をきわめて小さくすることができ
るから、前記モールド部形成用キャビティーＥ内への溶
融合成樹脂のゲートＦからの充填によって成形されるモ
ールド部１４のうち前記両リード端子１２，１３の屈曲
部１２ｃ，１３ｃに該当する箇所における部分１４ｄ，
１４ｅが、バリ状の薄肉になることを防止できるか、バ
リ状の薄肉になることをきわめて小さくすることができ
るのである。Therefore, after the forming, when molding the mold portion 14, as shown in FIGS. 5 and 6, a pair of molding dies C and D divided on the bottom surface 14a of the mold portion 14 are used. When the lead terminals 12 and 13 are sandwiched between the molding dies C and D, the inner lead terminal portions 12a and 13a of the lead terminals 12 and 13 are formed in the molding cavity C of the mold portion. It directly rises from the bottom surface e toward the inside of the cavity E, and between the outer peripheral surfaces of the bent portions 12c and 13c of the lead terminals 12 and 13 and the bottom surface e of the mold portion forming cavity E. As in the case of the prior art, it is possible to prevent the formation of the tapered gap or to make the tapered gap extremely small. The bent portion 12c of the two lead terminals 12 and 13 of the mold portion 14 which is formed by filling the gate F of the molten synthetic resin into parts forming cavity within E, portion 14d at a point corresponding to 13c,
It is possible to prevent the burr-like thinning of 14e or to reduce the burr-like thinning extremely.
【００１５】その結果、前記両部分１４ｄ，１４ｅに、
合成樹脂の剥離や欠けが発生することを低減できるか
ら、両リード端子１２，１３における外部リード端子部
１２ｂ，１３ｂのモールド部１４からの露出寸法（Ｓ）
が不揃いになることを大幅に改善できるのである。な
お，前記実施例は、一つの半導体チップに対して二本の
リード端子１２，１３を有するダイオードに適用した場
合を示したが、本発明は、これに限らず、少なくとも三
本のリード端子を備えたトランジスターとか、多数本の
リード端子を備えたＩＣ等のように、他の種類のパッケ
ージ型半導体装置に対しても同様に適用できることは云
うまでもない。As a result, the two parts 14d and 14e are
Since the occurrence of peeling or chipping of the synthetic resin can be reduced, the exposed dimension (S) of the external lead terminal portions 12b and 13b of both lead terminals 12 and 13 from the mold portion 14 (S)
It is possible to greatly improve the non-uniformity. In addition, although the said Example showed the case where it applied to the diode which has two lead terminals 12 and 13 with respect to one semiconductor chip, this invention is not restricted to this, At least three lead terminals are provided. It goes without saying that the present invention can be similarly applied to other types of package-type semiconductor devices such as a provided transistor and an IC having a large number of lead terminals.
【図１】本発明によって製造したダイオードの縦断正面
図である。FIG. 1 is a vertical sectional front view of a diode manufactured according to the present invention.
【図２】図１の底面図である。FIG. 2 is a bottom view of FIG.
【図３】本発明の方法においてリード端子をフォーミン
グする前の状態を示す図である。FIG. 3 is a diagram showing a state before forming a lead terminal in the method of the present invention.
【図４】本発明の方法においてリード端子をフォーミン
グしている状態を示す図である。FIG. 4 is a diagram showing a state in which lead terminals are being formed in the method of the present invention.
【図５】本発明の方法においてモールド部を成形する状
態を示す図である。FIG. 5 is a diagram showing a state in which a mold part is molded in the method of the present invention.
【図６】図５のVI−VI視断面図である。6 is a sectional view taken along line VI-VI of FIG.
【図７】従来の製造方法によるダイオードを示す縦断正
面図である。FIG. 7 is a vertical sectional front view showing a diode manufactured by a conventional manufacturing method.
【図８】図７の底面図である。FIG. 8 is a bottom view of FIG. 7;
１１ 半導体チップ １２，１３ リード端子 １２ａ，１３ａ 内部リード端子部 １２ｂ，１３ｂ 外部リード端子部 １２ｃ，１３ｃ 屈曲部 １４ モールド部 １４ａ モールド部の底面 Ａ，Ｂ フォーミング金型 Ｃ，Ｄ モールド部成形用金型 11 Semiconductor Chips 12, 13 Lead Terminals 12a, 13a Internal Lead Terminals 12b, 13b External Lead Terminals 12c, 13c Bent 14 Molds 14a Bottom of Mold A, B Forming Mold C, D Mold Molds
Claims (1)
ド端子を接続する工程と、この各リード端子を、内部リ
ード端子部と外部リード端子部とに段状に屈曲するフォ
ーミング工程と、前記半導体チップの部分を、合成樹脂
製のモールド部にて、各リード端子における外部リード
端子部が当該モールド部の底面に露出してこの底面に沿
って延びるようにパッケージする工程とを有するパッケ
ージ型半導体装置の製造方法において、前記フォーミン
グ工程が、リード端子を内部リード端子部と外部リード
端子部とに段状に屈曲するときに、その屈曲部の内周面
を、押圧にて当該屈曲部の外周面が半径の小さい角張っ
た形状になるように潰し変形する工程を含んでいること
を特徴とするパッケージ型半導体装置の製造方法。At least a step of connecting a plurality of lead terminals to a semiconductor chip, a forming step of bending each of the lead terminals into an internal lead terminal portion and an external lead terminal portion in a stepwise manner, and the semiconductor chip. Part of the package type semiconductor device in such a manner that the external lead terminal part of each lead terminal is exposed at the bottom surface of the mold part and extends along the bottom surface with a mold part made of synthetic resin. In the manufacturing method, in the forming step, when the lead terminal is bent stepwise into the internal lead terminal portion and the external lead terminal portion, the inner peripheral surface of the bent portion is pressed, and the outer peripheral surface of the bent portion is pressed. Square with a small radius
A method of manufacturing a package-type semiconductor device, comprising the step of crushing and deforming so as to obtain a desired shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5121199A JP2560194B2 (en) | 1993-05-24 | 1993-05-24 | Method of manufacturing packaged semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5121199A JP2560194B2 (en) | 1993-05-24 | 1993-05-24 | Method of manufacturing packaged semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0621295A JPH0621295A (en) | 1994-01-28 |
| JP2560194B2 true JP2560194B2 (en) | 1996-12-04 |
Family
ID=14805324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5121199A Expired - Fee Related JP2560194B2 (en) | 1993-05-24 | 1993-05-24 | Method of manufacturing packaged semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2560194B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121862A (en) * | 1982-12-28 | 1984-07-14 | Fujitsu Ltd | Resin-sealed semiconductor device |
| JPS60189940A (en) * | 1984-03-09 | 1985-09-27 | Nec Corp | Manufacture of resin seal type semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6448051U (en) * | 1987-09-18 | 1989-03-24 |
-
1993
- 1993-05-24 JP JP5121199A patent/JP2560194B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121862A (en) * | 1982-12-28 | 1984-07-14 | Fujitsu Ltd | Resin-sealed semiconductor device |
| JPS60189940A (en) * | 1984-03-09 | 1985-09-27 | Nec Corp | Manufacture of resin seal type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0621295A (en) | 1994-01-28 |
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| LAPS | Cancellation because of no payment of annual fees |