JPH06324890A - Memory access method - Google Patents
Memory access methodInfo
- Publication number
- JPH06324890A JPH06324890A JP5111975A JP11197593A JPH06324890A JP H06324890 A JPH06324890 A JP H06324890A JP 5111975 A JP5111975 A JP 5111975A JP 11197593 A JP11197593 A JP 11197593A JP H06324890 A JPH06324890 A JP H06324890A
- Authority
- JP
- Japan
- Prior art keywords
- state
- address
- area
- abnormality
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、メモリ上に、例えば信
号未検出状態になった時の警報,データがフレームをは
み出す状態になった時の警報,クロックダウン状態にな
った時の警報を書き込む領域を設け、通信装置等が上記
の状態になった時は、該当領域の所定のビット位置のビ
ットを1とし、状態になっていない時は該ビット位置を
0とし、これをCPUが読出して処理をする場合、各領
域のアドレスが変わっても、又ビット位置が変わって
も、ソフトウエアを変更しなくてよいメモリアクセス方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a memory with, for example, an alarm when a signal is not detected, an alarm when data is out of a frame, and an alarm when a clock is down. A writing area is provided, and when the communication device or the like is in the above state, the bit at the predetermined bit position of the corresponding area is set to 1, and when not in the state, the bit position is set to 0, and the CPU reads it. The present invention relates to a memory access method in which software is not required to be changed even if the address of each area is changed or the bit position is changed.
【0002】[0002]
【従来の技術】図5は1例の伝送装置の状態をCPU側
に知らせる装置の要部のブロック図である。2. Description of the Related Art FIG. 5 is a block diagram of a main part of an apparatus for notifying a CPU of the state of an example of a transmission apparatus.
【0003】図5にて、伝送装置11が、信号未検出状
態になった時の警報,データがフレームをはみ出す状態
になった時の警報,クロックダウン状態になった時の警
報をCPU10に知らせる場合は、メモリ3上に各警報
を書き込む領域を設け、伝送装置が上記状態になった時
は、該当領域の所定のビット位置のビットを1とし、上
記状態になっていない時は0とし、これをCPU10が
読出し処理をしている。尚図5のメモリ3では、警報を
書き込むのは上から、8ビットの最後のビットの1とな
っている所、次の8ビットの最後のビットの0となって
いる所,次の8ビットの最後より2番目の1となってい
る所であり、12はプログラム等を記憶しているROM
である。In FIG. 5, the transmission device 11 notifies the CPU 10 of an alarm when the signal is not detected, an alarm when the data is out of the frame, and an alarm when the clock is down. In this case, an area for writing each alarm is provided on the memory 3, and when the transmission device is in the above state, the bit at a predetermined bit position in the corresponding area is set to 1, and when not in the above state, it is set to 0, The CPU 10 is reading this. In the memory 3 of FIG. 5, the alarm is written from the top, where the last bit of the 8 bits is 1, the last bit of the next 8 bits is 0, and the next 8 bits. 2 is the second place from the end, and 12 is a ROM that stores programs, etc.
Is.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、コンピ
ュータが変わると、各状態を示す領域のアドレス,正
常,異常を示すビット位置が変わることがある。However, when the computer changes, the address of the area indicating each state and the bit position indicating normal or abnormal may change.
【0005】この場合、従来は、ソフトウエアの、該当
する部分のアドレス及びビット位置を示す内容を変更せ
ねばならず、手間が多くかかる問題点がある。本発明
は、状態を示す領域のアドレス,正常,異常を示すビッ
ト位置が変わってもソフトウエアは変更しなくてよく、
変更する手間の少ないメモリアクセス方法の提供を目的
としている。In this case, conventionally, it is necessary to change the contents indicating the address and the bit position of the corresponding portion of the software, which causes a problem that it takes much labor. According to the present invention, the software does not have to be changed even if the address of the area indicating the state, the bit position indicating normality, or the abnormality is changed.
The purpose of the present invention is to provide a memory access method that is easy to change.
【0006】[0006]
【課題を解決するための手段】図1は本発明の原理ブロ
ック図である。図1に示す如く、メモリ3の、ある状態
を書き込む領域の状態の正常,異常を示すビット位置を
アクセスするに際し、状態名を書き込む領域の欄、状態
名を書き込む領域のアドレス欄,各状態の正常,異常を
示す欄,状態の正常,異常を示すビット位置を示す欄を
持つ位置情報テーブル1及びアクセス手段2を持たせ、
該アクセス手段2にて、該位置情報テーブル1を参照
し、ある状態を書き込む領域のアドレス及び状態の正
常,異常を示すビット位置を求め、該求めた位置に書込
み、又は求めた位置より読み出す構成とする。FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, when accessing a bit position indicating a normal or abnormal state of a region in which a certain state is written in the memory 3, a column for writing a state name, an address column for writing a state name, The position information table 1 and the access means 2 each having a column indicating normality / abnormality, a column indicating bit position indicating normality / abnormality, and an access unit 2 are provided.
A structure in which the access means 2 refers to the position information table 1 to obtain an address of a region in which a certain state is to be written and a bit position indicating normality / abnormality of the state, and writes to the obtained position, or reads from the obtained position And
【0007】[0007]
【作用】本発明によれば、状態を示す領域のアドレス,
正常,異常を示すビット位置が変わると、位置情報テー
ブル1の変更になった状態名を書き込む領域のアドレ
ス、変更になった状態の正常,異常を示すビット位置を
変更しておけば、アクセス手段2にて、位置情報テーブ
ル1を参照し、ある状態を書き込む領域のアドレス及び
正常,異常を示すビット位置を求め、該求めた位置に書
込み、又は求めた位置より読み出すので、ソフトウエア
は変更しなくてアクセス出来るので、変更する手間は少
なくなる。According to the present invention, the address of the area indicating the state,
When the bit position indicating normal or abnormal is changed, the address of the area in which the changed state name of the position information table 1 is written, and the bit position indicating normal or abnormal in the changed state are changed. 2, the position information table 1 is referred to, and the address of the area in which a certain state is written and the bit position indicating normality / abnormality are obtained, and writing is performed at the obtained position or read from the obtained position, so the software is changed. You can access it without it, so you can change it less.
【0008】[0008]
【実施例】図2は本発明の実施例の位置情報テーブルを
示す図、図3は本発明の実施例の書込み処理のフローチ
ャート、図4は本発明の実施例の読出し処理のフローチ
ャートである。FIG. 2 is a diagram showing a position information table of an embodiment of the present invention, FIG. 3 is a flowchart of a writing process of the embodiment of the present invention, and FIG. 4 is a flowchart of a reading process of the embodiment of the present invention.
【0009】信号未検出状態になった時の警報,データ
がフレームをはみ出す状態になった時の警報,クロック
ダウン状態になった時の警報を書き込む領域のアドレス
が図2に示す如く1000,1000,1001であ
り、正常,異常を示すビット位置が図2に示す如く、L
SBより1,2,1ビットの位置であったとすると、位
置情報テーブルは図2に示す如く、状態名を書き込む領
域の欄には、上から信号未検出状態警報,フレームをは
み出し警報,クロックダウン警報を書込み、状態名を書
き込む領域のアドレス欄には上から1000,100
0,1001を書込み,各状態の正常,異常を示す欄に
は夫々NO,ALM、ALM発生を書込み、状態の正
常,異常を示すビット位置を示す欄には上から1,2,
1を書き込んでおく。Addresses of areas for writing an alarm when a signal is not detected, an alarm when a data is out of a frame, and an alarm when a clock is down are 1000 and 1000 as shown in FIG. , 1001, and the bit positions indicating normality and abnormality are L as shown in FIG.
Assuming that the position is 1, 2, 1 bit from SB, as shown in FIG. 2, in the position information table, in the column of the area for writing the status name, the signal non-detection status alarm, the frame protruding alarm, the clock down In the address field of the area for writing the alarm and the state name, 1000,100 from the top
0, 1001 are written, NO, ALM, ALM occurrence are written in the columns showing normal and abnormal states, respectively, and columns 1, 2 from the top are written in the columns showing bit positions showing normal and abnormal states.
Write 1.
【0010】アクセス手段としては、図5の伝送装置1
1がメモリ3に書き込む処理の場合は図3に示す如くす
るものとし、図5のCPU10がメモリ3より読出し処
理をする場合は図4に示す如くするものとしておく。As the access means, the transmission device 1 shown in FIG.
When 1 is a process of writing to the memory 3, the process is as shown in FIG. 3, and when the CPU 10 of FIG. 5 is a process of reading from the memory 3, the process is as shown in FIG.
【0011】そこで、信号未検出状態となつた警報をC
PUに知らせる場合を例にとり、伝送装置11がメモリ
3に書き込む処理につき図3を用いて説明する。ステッ
プ1にて、信号未検出状態警報及び異常を入力すると、
ステップ2にて、図2の位置情報テーブルを参照し、信
号未検出状態警報領域のアドレスの100と、正常か異
常かを示すビット位置1を得、ステップ3にて、メモリ
のアドレス1000の、このアドレスに書き込むビット
が、例えば8ビットとすると8ビット目に1を書き込
む。Therefore, the alarm that is in the signal undetected state is C
The process of writing to the memory 3 by the transmission device 11 will be described with reference to FIG. In step 1, if the signal non-detection state alarm and abnormality are input,
In step 2, referring to the position information table of FIG. 2, 100 of the address of the signal undetected state alarm area and bit position 1 indicating normal or abnormal are obtained, and in step 3, the address 1000 of the memory If the bit to be written in this address is, for example, 8 bits, 1 is written in the 8th bit.
【0012】次に読出し処理につき図4を用いて説明す
る。ステップ1にて、信号未検出状態警報を入力する
と、ステップ2にて、図2の位置情報テーブルを参照
し、信号未検出状態警報領域のアドレスの1000を求
め、ステップ3にて、又図2の位置情報テーブルより、
アドレスの1000の正常か異常を示すビット位置の1
を求め、ステップ4にて、アドレスの1000の最後の
ビットの1を読出し、信号未検出状態になっていること
が判る。Next, the reading process will be described with reference to FIG. When the signal non-detection state alarm is input in step 1, the address information table 1000 of FIG. From the location information table of
1 in bit position 1000 indicating normal or abnormal address
Then, in step 4, the last bit 1 of 1000 of the address is read, and it is found that the signal is not detected.
【0013】即ち、状態を示す領域のアドレス,正常,
異常を示すビット位置が変わると、位置情報テーブル1
の変更になった状態名を書き込む領域のアドレス、変更
になった状態の正常,異常を示すビット位置を変更して
おけば、ソフトウエアは変更しなくてもアクセスが出来
るので変更する手間は少なくなる。That is, the address of the area showing the status, normal,
When the bit position indicating an abnormality changes, the position information table 1
If you change the address of the area to write the changed state name and the bit position that indicates whether the changed state is normal or abnormal, you can access without changing the software, so there is little effort to change. Become.
【0014】[0014]
【発明の効果】以上詳細に説明せる如く本発明によれ
ば、状態を示す領域のアドレス,正常,異常を示すビッ
ト位置が変わつても、位置情報テーブルの該当個所を変
更するだけで、ソフトウエアは変更しなくてよく、変更
する手間が少なくなる効果がある。As described in detail above, according to the present invention, even if the address of the area indicating the state and the bit position indicating normality or abnormality change, the software can be changed by changing the corresponding portion of the position information table. Does not have to be changed, which has the effect of reducing the trouble of changing.
【図1】は本発明の原理ブロック図、FIG. 1 is a block diagram of the principle of the present invention,
【図2】は本発明の実施例の位置情報テーブルを示す
図、FIG. 2 is a diagram showing a position information table according to the embodiment of the present invention,
【図3】は本発明の実施例の書込み処理のフローチャー
ト、FIG. 3 is a flowchart of a writing process according to an embodiment of the present invention,
【図4】は本発明の実施例の読出し処理のフローチャー
ト、FIG. 4 is a flow chart of read processing according to the embodiment of the present invention,
【図5】は1例の伝送装置の状態をCPU側に知らせる
装置の要部のブロック図である。FIG. 5 is a block diagram of a main part of a device for notifying the CPU side of the status of an example of the transmission device.
1は位置情報テーブル、 2はアクセス手段、 3はメモリ、 10はCPU、 11は伝送装置、 12はROMを示す。 1 is a position information table, 2 is an access means, 3 is a memory, 10 is a CPU, 11 is a transmission device, and 12 is a ROM.
Claims (1)
領域の状態の正常,異常を示すビット位置をアクセスす
るに際し、状態名を書き込む領域の欄、状態名を書き込
む領域のアドレス欄,各状態の正常,異常を示す欄,状
態の正常,異常を示すビット位置を示す欄を持つ位置情
報テーブル(1)及びアクセス手段(2)を持たせ、該
アクセス手段(2)にて、該位置情報テーブル(1)を
参照し、ある状態を書き込む領域のアドレス及び状態の
正常,異常を示すビット位置を求め、該求めた位置に書
込み、又は求めた位置より読み出すようにしたことを特
徴とするメモリアクセス方法。1. When accessing a bit position indicating a normal or abnormal state of an area in which a certain state name is written in a memory (3), a column for writing the state name, an address column for writing the state name, and A position information table (1) having a column indicating normality / abnormality of state, a column indicating bit position indicating normality / abnormality of state, and an access means (2) are provided, and the position is set by the access means (2). The information table (1) is referred to, and the address of the area in which a certain state is written and the bit position indicating normality / abnormality of the state are obtained, and writing is performed at the obtained position or read from the obtained position. Memory access method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5111975A JPH06324890A (en) | 1993-05-14 | 1993-05-14 | Memory access method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5111975A JPH06324890A (en) | 1993-05-14 | 1993-05-14 | Memory access method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06324890A true JPH06324890A (en) | 1994-11-25 |
Family
ID=14574826
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5111975A Withdrawn JPH06324890A (en) | 1993-05-14 | 1993-05-14 | Memory access method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06324890A (en) |
-
1993
- 1993-05-14 JP JP5111975A patent/JPH06324890A/en not_active Withdrawn
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000801 |