JP2001142742A - Debugging information output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a debugging information output device which can monitor for the purpose of debugging the data of an application program running on an OS dynamically securing a storage area for data. SOLUTION: The device has a processor 1, a RAM 2 as a writable memory, and a matching part 9; and the processor 1 writes a predefined data sequence to the memory 2 in predefined order before respective pieces of actual data and the matching part 9 stores a list of at least the data sequence and outputs the actual data written to the memory 2 successively the data sequence when detecting the data sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a processor and an R
In a computer having a writable memory such as an AM, the present invention relates to a debug information output device that monitors data during execution of an application program for debugging.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration of a conventional debug information output device of this kind. In FIG. 6, 1 is a processor, 2 is a writable memory such as a RAM, 3
Is a write signal, 4 is a data signal, 5 is an address signal,
Reference numeral 6 denotes an address collating unit having an address-channel comparison table (not shown) indicating a correspondence relationship between an address and a channel. Reference numeral 7 denotes a channel output indicating a channel designated when data is divided into a plurality of channels and output. Is a data output.

In a conventional debug information output device,
Write data for a preset address is output simultaneously with a channel defined in correspondence with the address.

[0004]

In the conventional debug information output device as described above, it is necessary to set the address of the data to be monitored in advance, so that an empty area is searched for at any time and data is written there. There has been a problem that data of an application program operating on an OS (operation system) that dynamically secures a data storage area cannot be monitored for debugging.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and makes it possible to monitor, for debugging, application program data that operates on an OS that dynamically secures a data storage area. An object is to obtain a debug information output device.

[0006]

DISCLOSURE OF THE INVENTION In view of the above-mentioned object, the first aspect
The invention has a processor, a writable memory, and a collation unit, and the processor writes a predetermined data sequence in the memory in a predetermined order in front of each real data. And outputting the actual data written to the memory following the data sequence when the collation unit stores at least the list of the data sequences and detects the data sequence. In the device.

According to a second aspect of the present invention, in the first aspect, the processor writes a predefined data string to the same address in the memory in the predefined order before each actual data. In addition, writing is performed, the collating unit stores at least the list of the data strings, and outputs the actual data written to the address following the data string when detecting the data string. Debug information output device.

[0008] A third invention is the debug information output device according to the second invention, wherein the collating unit simultaneously outputs the address at that time in addition to the actual data.

In a fourth aspect based on the second aspect, the collating unit stores at least the list of the data strings,
A data string collating unit that sets a corresponding address when the data string is detected, and stores an address set from the data string collating unit, and is written to the address when the set address is detected. And an address collating unit for outputting actual data.

In a fifth aspect based on the fourth aspect, the address collating section outputs a read / write signal together with the actual data read / written to the set address when the set address is detected. A debug information output device.

According to a sixth aspect of the present invention, in the above-mentioned inventions, the collating section has a data sequence-channel comparison table, and when the data sequence is detected, the actual data written following the data sequence is converted into the data sequence. And a debug information output device for outputting simultaneously with a predefined channel.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration of a debug information output device according to a first embodiment of the present invention. The same or corresponding parts as those of the conventional one are denoted by the same reference numerals. In FIG. 1, 1 is a processor, 2 is a writable memory, for example, RAM, 3 is a write signal, 4 is a data signal,
7 is a channel output indicating a channel set when data is divided into a plurality of channels and output, 8 is a data output,
Reference numeral 9 denotes a data string collating unit having a data string-channel comparison table (not particularly shown, the same applies hereinafter) in which correspondence between data strings and channels is defined in advance. In addition, actually, there is a read signal and the like as hardware, but only a portion related to this embodiment is shown.

Next, the operation will be described. For example, actual data (hereinafter referred to as actual data) obtained by a certain application program is
When writing to M2, the processor 1 performs writing by adding a predefined data sequence in front of the actual data in a predefined order.

For example, if the actual data is 15000, 290
0, 31000, 220, and if the data string is a 4-digit number A0A0, B0B0, C0C0, D0D0, (A0A0, 15000), (B0B0, 2900),
(C0C0, 31000), (D0D0, 220) (these are not always written to the memory continuously).

At this time, when the data string collating unit 9 detects the data strings, the data string collating unit 9 converts the actual data 8 written in the RAM 2 following these data strings into a channel 7 defined in advance corresponding to the data string. Output at the same time.

Thus, when debugging an application program operating on an OS that dynamically secures a data storage area, it is possible to continuously define a previously defined data string without previously setting an address of data to be monitored. R
By simply writing to the AM2, it is possible to monitor the execution data of the application program.

Embodiment 2 FIG. FIG. 2 is a diagram showing a configuration of a debug information output device according to a second embodiment of the present invention. Reference numeral 5 denotes an address signal, and 9a denotes a data string collating unit having a data string-channel comparison table.

In this embodiment, the processor 1
When the actual data is written to the same address in such a way that a predefined data sequence is added before the actual data in a predefined order, the data sequence collating unit 9a When the column is detected, the actual data 8 written in the RAM 2 following the data column is output simultaneously with the channel 7.

As a result, in addition to the first embodiment, DMA (direct memory access) is performed on the same RAM.
Even in an environment where other inputs and outputs are congested, each variable
By simply writing in advance a data sequence defined in advance (solution of each process in the application = actual data), it becomes possible to monitor the execution data of the application program.

Embodiment 3 FIG. 3 is a diagram showing a configuration of a debug information output device according to a third embodiment of the present invention. 9b is a data string collating unit having a data string-channel comparison table, and 10 is an address output.

In this embodiment, the processor 1
When the actual data is written to the same address in such a way that a predefined data sequence is added before the actual data in a predefined order, the data sequence collating unit 9b When a column is detected, the address 10 at that time is simultaneously output in accordance with the actual data 8 written in the RAM 2 and the channel 7 following the data sequence.

In this way, in addition to the second embodiment, the execution time data 8 and the physical address 10 of the application program can be monitored only by sequentially writing a data string defined in advance to each variable.

Embodiment 4 FIG. 4 is a diagram showing a configuration of a debug information output device according to a fourth embodiment of the present invention. In FIG. 4, 9c is a data string collating unit having a data string-channel comparison table, 9d is an address collating unit,
11 is an address setting signal, and 12 is a channel setting signal.

In this embodiment, the processor 1
When the actual data is written to the same address in such a way that a predefined data sequence is added before the actual data in a predefined order, the data sequence collating unit 9c When a column is detected, a predetermined channel 12 corresponding to the address 11 and the data sequence at that time is set in the address collating unit 9d, and the address collating unit 9d stores the address and the channel set from the data sequence collating unit 9c. The actual data 8 written to the set address when the set address is detected
(Real data including the added data string) is output simultaneously with the channel 7.

In this way, in addition to the second embodiment, the subsequent change of the variable can be monitored only by sequentially writing a predefined data sequence to each variable, so that the data transition during the execution of the application program can be monitored. Can be monitored.

Embodiment 5 FIG. 5 is a diagram showing a configuration of a debug information output device according to a fifth embodiment of the present invention. In FIG. 5, 9e is an address string collating unit, 13 is a read signal, and 14 is a read / write signal.

In this embodiment, in addition to the fourth embodiment, when the address collating unit 9e detects the set address, the actual data 8 (added data string) read or written to the set address is detected. And the channel 7 and a read / write signal 14 for the set address (indicating which of the read / write was performed to the address)
Is output.

In this way, in addition to the fourth embodiment, subsequent reading and writing of the variable can be monitored only by sequentially writing a predefined data sequence to each variable. Data access can be monitored.

In each of the above-described embodiments, the channel set in the collating unit to output data divided into a plurality of channels is output. However, this may be output as necessary. When the output of the channel is not required, the collating unit need only store the list of the data strings.

[0030]

As described above, according to the first aspect of the present invention, a processor, a writable memory, and a collating unit are provided, and the processor stores data in a predetermined order in the memory in a predetermined order. A column is added before each actual data to perform writing, and the collating unit stores at least the list of the data columns, and when the data column is detected, the actual data written to the memory following the data column. The debug information output device is characterized in that an address of data to be monitored is set in advance when debugging an application program operating on an OS that dynamically secures a data storage area. It is possible to monitor application program execution data simply by writing a predefined data sequence to RAM continuously That.

According to the second aspect, the processor adds a predefined data sequence to the same address in the predefined address in the predefined order before each real data. Writing is performed, and the collating unit stores at least the list of the data strings, and outputs the actual data written to the address following the data string when the data string is detected. ,
Even in an environment where other inputs and outputs such as DMA are congested in the same RAM, it is possible to monitor the execution data of the application program only by sequentially writing a predefined data sequence to each variable.

[0032] According to the third invention, the collating unit includes:
Since the address at that time is output simultaneously in addition to the actual data, in addition to the second aspect of the invention, the data at the time of execution of the application program and the physical Can be monitored.

[0033] According to the fourth invention, the collating unit includes:
A data string collating unit that stores at least the list of the data strings and sets a corresponding address when the data string is detected, and stores an address set from the data string collating unit, and the set address is detected. And an address collating unit that outputs actual data written to the address when the address is changed. In addition to the second aspect of the present invention, it is only necessary to sequentially write a data string defined in advance to each variable, Since the subsequent change of the variable can be monitored, it is possible to monitor the data transition during the execution of the application program.

According to the fifth aspect of the present invention, when the set address is detected, the address collating unit outputs a read / write signal together with the actual data read / written to the set address. Therefore, in addition to the above-described fourth aspect, by simply sequentially writing a predefined data sequence to each variable, subsequent reading and writing of the variable can be monitored, so that data access at the time of execution of the application program can be monitored. Monitoring becomes possible.

According to the sixth aspect of the present invention, the collating unit has a data string-channel comparison table, and when the data string is detected, the actual data written following the data string corresponds to the data string. Since the data is output at the same time as a predefined channel, it is possible to divide the data into a plurality of channels and display the data for each channel.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a debug information output device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a debug information output device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a debug information output device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a debug information output device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a debug information output device according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional debug information output device of this type.

[Explanation of symbols]

1 processor, 2 RAM, 3 write signal, 4
Data signal, 5 address signal, 7 channel output, 8
Data output, 9, 9a, 9b, 9c Data string collating unit, 9d, 9e Address collating unit, 10 address output, 11 address setting signal, 12 channel setting signal, 13 read signal, 14 read / write signal.

Claims (6)

[Claims] 1. A processor having a processor, a writable memory and a collating unit, wherein the processor adds a predefined data sequence to the memory in a predefined order before each actual data. Writing information, the collating unit stores at least the list of the data strings, and outputs the actual data written to the memory following the data strings when the data strings are detected. Output device. 2. The processor according to claim 1, wherein
For the same address, a predefined data sequence is added in front of each real data in a predefined order, and writing is performed. The collating unit stores at least a list of the data sequences, and 2. The debug information output device according to claim 1, further comprising: outputting real data written to the address following the data sequence when the data is detected. 3. The debug information output device according to claim 2, wherein the collation unit simultaneously outputs the address at that time in addition to the actual data. 4. The data collating unit stores at least a list of the data strings, and sets a corresponding address when the data string is detected, and an address set from the data string collating unit. 3. The debug information output device according to claim 2, further comprising: an address collating unit that stores and outputs actual data written to the set address when the set address is detected. 5. The apparatus according to claim 4, wherein the address collating unit outputs a read / write signal together with the actual data read / written to the set address when the set address is detected. Debug information output device. 6. The comparison section has a data string-channel comparison table, and when detecting the data string, writes actual data written following the data string to a channel defined in advance corresponding to the data string. 6. The debug information output device according to claim 1, wherein the debug information is output simultaneously.