JPH06310573A - Carrier tape for tab and tape carrier package that uses it - Google Patents

Abstract

PURPOSE:To make the wiring between chips efficient in spacing when mounting many semiconductor chips on the tape carrier packages. CONSTITUTION:Lead patterns 2 are formed on the lower surface of the tape 1a where window holes 15 are formed, and inner leads 2a, extended into the window holes 15 from the lead patterns, are connected with bumps 9 of the semiconductor chips 8, and the window holes 15 are formed as peripheries of regions, where the bumps of the semiconductor chips 8 are formed, are to be exposed, and the part of the tape 1a covering the semiconductor chips 8 can be used as the region where the wiring patterns are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier tape for tape automated bonding (TAB) and a tape carrier package using the same.

[0002]

2. Description of the Related Art A so-called tape carrier package (TCP) is being adopted as a packaging method for a multi-terminal type semiconductor chip such as an LSI.

This tape carrier package uses a flexible insulating tape (carrier tape) having a lead pattern formed on the surface thereof. The inner lead is extended inward from the lead pattern in the device hole of the carrier tape. This is a package adopting the TAB method, in which gold bumps formed on the terminals of the chip are thermocompression bonded and supported.

FIG. 6 shows an example of the structure of a carrier tape 1 for supporting a semiconductor chip by such a TAB method.

A plurality of lead patterns 2 are formed by etching or the like on the surface of the carrier tape body 1a made of a polyimide film or the like. A device hole 3 is opened in the widthwise center of the tape body 1a, and an outer lead 2b and a cutting slit 4 are formed so as to surround the device hole 3. The lead pattern 2 extends from a test pad 5 provided outside the slit 4, and the four ends of the lead hole 2 cross the slit 4 and project inward from the inner edge of the device hole 3 on the four sides of the device hole 3. Is formed. The slit 4 in the tape body 1a
The region sandwiched between the device hole 3 and the device hole 3 forms a support ring 6 that surrounds the device hole 3 and supports the leads 2.

Generally, a portion of the lead pattern 2 that extends further inward from the support ring 6 into the device hole 3 is called an inner lead 2a, and a portion that crosses the slit 4 is an outer lead. I call it 2b.

The above-described structure is formed in the longitudinal direction of the elongated tape body 1a at a plurality of equal intervals, and the carrier tape 1 is lengthened by utilizing the sprocket holes 7 formed on both side edges thereof. The chip bonding (inner lead bonding) described below is performed while stepwise feeding in the direction.

The semiconductor chip 8 is the carrier tape 1 described above.
2 has a planar shape that can enter the device hole 3, and bumps 9 (FIG. 7) made of gold are formed in advance on the terminal surfaces on the four sides of the upper surface thereof.

As shown in FIG. 7, the bonding tool 10 moves up and down with a lower tool 10a on which the semiconductor chip 8 is placed and heated, and above and below the lower tool 10a to move the inner leads 2a to the bumps 9 And an upper tool 10b which is pressed against. Semiconductor chip 8
After the carrier tape 1 is positioned with respect to the inner tape 2a, the upper tool 10b is moved downward, and the tip end of the upper tool 10b presses the inner leads 2a together onto the bumps 9 in a lump, and the inner leads 2a are semiconductor-bonded by thermocompression bonding. Connected to each terminal on the chip.

In this way, the semiconductor chip 8 is supported on the carrier tape 1. A thermosetting resin 1 such as an epoxy resin is formed on the upper circuit surface 8a of the semiconductor chip 8.
Protected by applying 1.

Next, the outer lead 2b which crosses the slit 4 in the carrier tape 1 is cut, the semiconductor device 12 having the form shown in FIG. 8 is separated from the carrier tape 1, and the outer lead 2b is formed as required. , Mounted on a circuit board.

The tape carrier package 13 using TAB as described above has the following advantages.

First, since the leads can be formed by etching, fine leads can be formed, and correspondingly, the electrode pitch on a semiconductor chip such as an LSI can be made extremely small. As a result, it is possible to further increase the packing density of the semiconductor device.

Secondly, since only the surface circuit forming portion of the chip needs to be covered with the protective resin, it is possible to significantly reduce the thickness of the packaging as compared with a so-called resin package type semiconductor device. It is possible to promote thinning, high density, and multi-layering of the entire substrate on which the semiconductor device is mounted.

[0015]

The example shown in FIG. 6 shows a relatively small number of leads for the purpose of explaining the conventional tape carrier package, but in reality, the inner lead pitch is 100 μm or less. In some cases, Further, it is expected that the degree of integration of semiconductor chips to be supported will further increase in the future, and some chips have relatively large outer shapes. Then, in the structure of the conventional tape carrier package, the device hole 3 becomes large in accordance with the high integration of the semiconductor chip, and the wiring density of the leads is also increased. That is, although the wiring density is increased, the area where such wiring is to be formed is reduced by the size of the device hole as described above, making it difficult to form a complicated wiring pattern on the carrier tape. .

Further, when forming a certain circuit in cooperation with the circuit board, the pattern to be formed on the circuit board must be complicated, which means that the pattern on the circuit board in a certain range is complicated. It makes complicated wiring difficult.

In short, in the conventional tape carrier package or the TAB carrier tape used therefor, the region in the device hole is not used at all for arranging the wiring pattern, and therefore the semiconductor chip is used. It is considered that the higher the degree of integration and the narrower the lead pitch, the more difficult the wiring around the semiconductor chip becomes.

The invention of the present application was conceived based on the above knowledge, and it is possible to mount a tape carrier packaged semiconductor device on a circuit board more efficiently. It is a basic subject.

[0019]

In order to solve the above problems, the present invention takes the following technical means.

According to the first aspect of the present invention, the lead pattern is formed on the lower surface of the tape body having the window hole, and the inner lead extended from the lead pattern into the window hole is formed on the semiconductor chip. A carrier tape for joining bumps to support the semiconductor chip, wherein the window hole is formed so as to partially face the peripheral edge of the semiconductor chip on which the bump is formed,
It is characterized in that the portion of the tape body that covers the semiconductor chip is used as a wiring pattern forming region.

According to the second aspect of the present invention, the lead pattern is formed on the lower surface of the tape body having the window hole, and the inner lead extended from the lead pattern into the window hole is formed on the semiconductor chip. A carrier tape for bonding bumps to support the semiconductor chip, wherein the window hole is formed so as to partially face a peripheral edge of the semiconductor chip on which the bump is formed. The pattern is formed on the lower surface of the portion of the tape body that covers the semiconductor chip, the inner lead is extended from the lead pattern into the window hole, the upper surface of the tape body, A wiring pattern is formed, and some or all of the wiring pattern is electrically connected to the selected one of the lead patterns through the VIA hole. It is characterized in that is.

The invention described in claim 3 of the present application is a tape carrier package constituted by using the carrier tape according to claim 1 or 2, wherein bumps on the upper surface of a semiconductor chip are bonded to the inner leads, and The upper surface of the semiconductor chip is resin-sealed.

Further, the invention described in claim 4 of the present application is the same as the basic concept of the invention described in claim 1 above.
It is applied for a memory chip, and has a tape body having a predetermined width and a constant length in the longitudinal direction, and the tape body has a plurality of memory chip holding portions formed in the longitudinal direction. Each of the memory chip holding portions has a pair of window holes facing each other in the tape width direction, a lead pattern formed in a region between the window holes on the back surface of the tape body, and an inner portion extending from the lead pattern into the window hole. A plurality of signal wiring patterns extending in the longitudinal direction of the tape body are formed over the respective memory chip holding portions on the upper surface of the tape main body. It is characterized in that the selected one of the wiring patterns is electrically connected to the selected one of the lead patterns through the VIA hole.

Further, in the invention described in claim 5 of the present application, in the carrier tape for a memory chip according to claim 4, the signal wiring pattern includes an address bus pattern and / or a data bus pattern,
The patterns for each bus are
It is characterized in that they are commonly connected to the selected lead pattern through a VIA hole.

Furthermore, in the invention as set forth in claim 6, in the carrier tape for a memory chip according to claim 4, a wiring for a power source is formed on the upper surface of the tape main body over the respective memory chip holding portions in the longitudinal direction thereof. A pattern and a ground wiring pattern are further provided, and each of the memory chip holding portions is characterized by being equipped with a bypass capacitor that bridges between the power supply wiring pattern and the ground wiring pattern.

The invention according to claim 7 of the present application is a tape carrier package for a memory chip using the carrier tape for a memory chip according to any one of claims 4 to 6, wherein the memory chip is bumped on its upper surface. Is supported by being connected to inner leads extending to the respective window holes in the respective memory chip holding portions.

[0027]

In summary, the present invention positively utilizes the area where the device hole is provided in the conventional TAB carrier tape as the area where the wiring pattern is to be formed, thereby arranging complicated wiring on the carrier tape. When mounting a tape carrier package in which a semiconductor chip is supported on such a carrier tape on a circuit board, it is possible to avoid complicated wiring on the circuit board and mount the semiconductor device more efficiently. Is what you are trying to do.

As long as it is a tape carrier package, the lead pattern formed on the carrier tape is extended into the window hole to form the inner lead, and the inner lead is thermocompression bonded to the bump on the semiconductor chip, which is the same as before. is there.

However, in the present invention, there is no device hole in the conventional carrier tape. The window hole provided in the tape body to expose the inner lead,
It is the minimum necessary to expose the terminal portion usually provided on the peripheral edge of the upper surface or the bumps formed on the semiconductor chip to be supported. Therefore, the carrier tape body is left with a portion covering the upper surface of the semiconductor chip to be supported. The necessary wiring pattern is formed by utilizing the portion covering the semiconductor chip.

Conventionally, since the device hole exists, the upper surface region of the semiconductor chip carried on the carrier tape has not been used for wiring at all. However, in the present invention, the semiconductor chip is covered as described above. Since the wiring pattern can be formed on the carrier tape, the more complicated wiring can be formed on the carrier tape, and the wiring on the circuit board on which the tape carrier packaged semiconductor device is to be mounted can be simplified accordingly. Can be converted. As a result, the semiconductor device can be mounted on the circuit board more efficiently, and the electronic circuit can be further downsized.

A hybrid IC, a multi-chip module or the like can be considered as a circuit board on which the tape carrier package to which the present invention is applied is to be mounted. Further, as will be described later, there is a memory chip as a semiconductor chip to be supported, and if the tape carrier package for this memory chip is formed according to the configuration described later, the memory substrate will be more efficient.

According to the second aspect of the present invention, the lead pattern connected to the inner lead facing the window hole is formed on the lower surface of the portion of the tape body that covers the semiconductor chip, while the separate wiring is formed on the upper surface of the tape body. A pattern is formed, and the wiring pattern on the upper surface of the tape body and the lead pattern on the lower surface are electrically connected via the VIA hole. As a result, the inner leads can be substantially extended from the inside into the window hole, and the area outside the window hole can be effectively used as a wiring pattern for the peripheral circuit configuration. Become. as a result,
As a whole, the carrier tape main body can be effectively used for wiring for forming the peripheral circuit of the semiconductor chip on which the carrier tape is to be mounted. The circuit board on which the tape carrier packaged semiconductor device is mounted can be simplified, and higher density mounting can be achieved.

Although the upper surface of the semiconductor chip bonded to the carrier tape needs to be resin-sealed,
For example, by providing an opening in the tape body that covers the upper surface of the bonded semiconductor chip and injecting the sealing resin from this opening, the upper surface of the semiconductor chip can be covered with the sealing resin without any problem.

According to the invention described in claim 4 and below, when a large number of memory chips are mounted to form a memory substrate, a carrier tape for TAB is used, and a signal such as an address bus line or a data bus line is applied to the carrier tape. It is designed to be in charge of wiring. Generally, when a memory device having a predetermined capacity is configured using a large number of random access memory (RAM) chips, a plurality of memory chips mounted on a substrate are connected by an address bus or a data bus. The larger the capacity of one memory chip, or the larger the number of such memory chips used, the more complicated the wiring of the bus line on the substrate and the more space on the substrate required for such wiring. As a result, it becomes impossible to increase the mounting density of the memory chips on the memory substrate.

The present invention remarkably improves the above-mentioned conventional problems when a memory substrate is constructed by using a large number of such memory chips.

A plurality of memory chip holding portions are formed in the longitudinal direction on the tape body, and the memory chips are bonded to the respective memory chip holding portions by using the above-described basic concept of the present invention. That is, each memory chip holding portion is provided with the minimum necessary window hole for exposing the terminals or bumps formed on the memory chip, and the area for covering the upper surface of the memory chip is left. Then, the signal wiring pattern is formed so that the portion of the tape main body that covers each memory chip extends in a penetrating manner in the tape longitudinal direction.

On the other hand, on the back surface of each memory chip holding portion,
A lead pattern is formed, and an inner lead extending from the lead pattern is exposed in the window. The signal wiring pattern formed on the front surface of the tape body and the lead pattern formed on the back surface of the tape body in each memory chip holding portion are electrically connected to each other through the VIA hole.

By doing so, most of the large number of bus lines that had to be formed in the peripheral portion of the memory device mounted with a large number of them on the TAB carrier tape to which the memory chips are bonded are formed. Therefore, the wiring area of the substrate can be reduced correspondingly, and high-density mounting of memory chips on the substrate can be achieved.

Of course, it is necessary to connect a power supply system line such as a logic power supply line and a ground line to each memory chip, but such a line is also convenient on the TAB carrier tape like the signal wiring pattern. Can be formed.

According to the invention described in claim 6, in the TAB,
A power supply noise bypass capacitor is mounted between the power supply wiring pattern and the ground wiring pattern formed on the carrier carrier body. In order to operate this kind of random access memory (RAM) conveniently while avoiding obstacles such as noise, it is essential to interpose a power supply noise bypass capacitor between the power supply line (Vcc line) and the ground line. Moreover, it is effective to provide such a bypass capacitor as close to the chip as possible. According to the invention of claim 6, such a requirement can be achieved conveniently. Further, in the past, the above-mentioned bypass capacitor, which had to be provided adjacent to the memory chip on the substrate, can be mounted on the layer above the memory chip via the carrier tape in a hierarchy. As a result, the space efficiency of the substrate on which a large number of memory chips are mounted is improved.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below.
A detailed description will be given with reference to FIGS. 1 to 5. In addition,
In these figures, parts or portions similar to those shown in the drawings starting from FIG. 6 are designated by the same reference numerals.

FIGS. 1 to 4 show a first embodiment of the present invention. When a large number of RAM chips 8 are mounted on a substrate to form a memory substrate having a predetermined capacity, a fixed number of memory chips are used. Is carried on the carrier tape 1 for TAB, and a memory module to be mounted on the substrate at once is configured.

As shown in FIG. 1, a plurality of memory chip holding portions 14 are formed at equal intervals in the longitudinal direction on a tape body 1a having sprocket holes 7 formed on both side edges. A pair of window holes 15, 15 extending in the longitudinal direction of the tape are formed in each memory chip holding portion 14 at predetermined intervals in the tape width direction. These window holes 15,15
1 corresponds to the terminal arrangement of the memory chip 8 to be bonded to the carrier tape 1 as shown in FIG. That is, the memory chip 8 has a rectangular planar shape, and necessary terminals are concentrated in the vicinity of the two opposite sides. Of course, gold bumps 9 are formed in advance on each terminal.

As shown in FIG. 1, the TAB carrier tape 1 of the present invention does not have a large opening corresponding to a device hole unlike the conventional TAB carrier tape shown in FIG. Instead, the pair of window holes 15 and 15 have the minimum size and position necessary to expose the terminals (that is, the bumps) 9 on the chip to which the inner leads 2a to be described later are to be joined.

Therefore, in the case of the embodiment shown in FIG. 1, in each chip holding portion 14, the area between the two window holes 15, 15 is formed so as to cover the upper surface of the chip 8 to be bonded, and the carrier is formed. It is left integrally with the tape body 1a.

On the other hand, a predetermined lead pattern 2 is formed on the back surface of the area of the carrier tape 1 covering the chip 8, that is, the area between the pair of window holes 15 in each chip holding portion 14. Each lead pattern 2 is
Generally, it extends in the width direction of the tape body 1a, and its tip extends into each of the window holes 15 and 15 to form the inner lead 2a.
Is formed.

On the other hand, on the upper surface of the carrier tape main body 1a, each chip holding portion 14 is extended, that is, so as to extend in the longitudinal direction of the carrier tape 1.
A wiring pattern 16 such as a signal wiring pattern is formed. These signal wiring patterns 16 include an address bus pattern, a data bus pattern, a control bus pattern, and the like.

Further, the power supply system wiring pattern 17 may be formed on the upper surface of the carrier tape body 1a so as to be parallel to the signal wiring pattern 16. The power supply system wiring pattern 17 includes a logic power supply (Vc
The wiring pattern 17a for c) and the wiring pattern 17b for ground are included.

The wiring patterns 16 and 17 on the front surface side of the carrier tape and the lead patterns 2 formed on the back surface side of the carrier tape body 1a in each chip holding portion 14 are described.
The electrical continuity between them is provided by the VIA hole 18. As shown in FIG. 3, the VIA hole 18 is a well-known conducting means formed by forming a conductive coating by electroless plating on the inner surface of a small hole penetrating the tape body 1a.

In each chip holding portion 14, each signal wiring pattern 16 is electrically connected to the corresponding lead pattern 2 to the corresponding terminal through the VIA hole 18 as described above.

The wiring patterns 17a and 17b of the power supply system are also electrically connected to the lead pattern 2 electrically connected to the corresponding terminal through the VIA hole 18.

In the embodiment shown in FIG. 1, the tape body 1a
Among the wiring patterns 16 and 17 formed on the upper surface so as to extend in the longitudinal direction, the power supply wiring pattern 17a and the ground wiring pattern 17b are formed adjacent to each other, and the power supply noise bypass is performed in each chip holding portion 14. The capacitor chip 19 is mounted so as to bridge the patterns 17a and 17b.

The operation of holding the memory chip 8 in each chip holding portion 14 using the TAB carrier tape 1 formed as described above can be performed, for example, as follows.

First, the inner leads 2a facing the windows 15 are formed in advance as shown in detail in FIG. That is, the inner lead 2a is formed such that the tip end portion thereof is in a step-down shape with respect to the base end portion.
This is to prevent the inner lead 2a from accidentally coming into contact with the upper surface of the chip and causing a short circuit failure.

The carrier tape 1 is stepwise fed in the longitudinal direction by utilizing the sprocket holes 7. The bonding tool 10 is the chip 8 as before.
Is provided with a lower tool 10a, and an upper tool 10b having a function of pressing the tips of the inner leads 2a facing the respective window holes 15 and 15 against the bumps 9 on the chip. Each of the tools 10a and 10b has a heater incorporated therein so that the bonding portion can be heated to a predetermined temperature. When the planar position between the carrier tape 1 and the lower tool upper chip 8 is adjusted, the upper tool 10b moves downward, pressing the tips of the inner leads 2a against the bumps 9 on the chip. The temperature of the bumps is raised by heat, so that the bumps 9 and the tips of the inner leads 2a are thermocompression-bonded to each other.

When only the inner lead 2a is exposed to the window hole 15 as in the present invention, the upper tool 10b has a U-shaped cross section so that the lower end thereof can project only into the window hole 15.

When the memory chips 8 are thus supported by the chip holding portions 14 of the TAB carrier tape 1, the surfaces of the chips 8 are then resin-sealed. This is performed by injecting a thermosetting resin 11 such as an epoxy resin in a liquid state into the gap between the carrier tape 1 and the semiconductor chip 8. The carrier tape 1 and the chip 8
In order to conveniently inject the encapsulating resin 11 into the gap between the carrier tape body 1a and the carrier tape main body 1a, an encapsulating resin injecting opening 20 may be provided as shown in FIGS.

As described above, a TAB in which a fixed number of memory chips 8 are mounted on a single TAB carrier tape 1
In the multi-memory chip module, unnecessary parts on both sides of the tape body are cut off, and each wiring pattern is extended at both ends in the tape longitudinal direction to form external leads (not shown), and then a predetermined circuit board (not shown) is formed. ) Implemented on.

In forming a memory substrate having a predetermined capacity by using a large number of memory chips 8, it is necessary to connect each chip with a bus line. In the conventional method, the signal wiring pattern such as the bus line has to be formed on the substrate, and increases as the capacity of a single memory chip increases or the number of such memory chips mounted increases. As a result, a large area for forming a signal wiring pattern such as a bus line is required on the substrate, and therefore there is a limit to high-density mounting of memory chips on the substrate. Many parts of the signal wiring such as the bus line which has been forced to be formed can be formed on the TAB carrier tape 1 on which the modularized memory chips are mounted, and therefore, the size of the memory substrate can be greatly reduced. It will be possible.

By applying the technique of the present invention, a large-capacity memory device corresponding to a conventional hard disk memory is constructed by using a large number of high-density mounted memory chips while saving the occupied volume. It's not a dream. An advantage of the large-capacity memory device using such a memory chip is that the access time can be significantly shortened as compared with the case of using a hard disk memory, which may enable a future memory device revolution. It is a thing.

Further, when a circuit is constructed by mounting a memory, a logic IC, etc., it is necessary to interpose a power supply noise bypass capacitor near the chip, and conventionally, this must be mounted on a circuit board. Although this has been a factor that hinders the effective use of the circuit board area, according to the present invention, as shown in FIG. 1, it can be mounted on a carrier tape of a memory module formed into a multi-chip tape module. It becomes easy, and this contributes not a little in increasing the mounting density on the substrate.

According to the present invention, a plurality of memory chips are collectively carried on a carrier tape to form a multi-memory chip tape module as in the above-described embodiments, and a plurality of LSI chips other than the memory chips are used. In the case where a single chip is mounted on a substrate to form a multi-chip module, it is possible to apply a part of the wiring connecting between the chips to a carrier tape.

The gist of the present invention will be described repeatedly. By connecting the lead pattern 1 formed on the lower surface of the carrier tape body 1a and the wiring patterns 16 and 17 formed on the upper surface of the carrier tape body 1 by VIA holes, The carrier tape 1 is capable of forming a complicated wiring pattern. And
Since the part of the carrier tape that covers the upper surface of the chip to be bonded can also be used as the region for forming the wiring pattern, a complicated wiring pattern can be formed in a space-efficient manner.

When a plurality of chips other than memory chips are carried on a single carrier tape to form a module, the carrier tape is provided with chip holding portions 14 'corresponding to various chips to be mounted on the carrier tape. Will be done.

FIG. 5 shows an example of the chip holding portion 14 'on the carrier tape 1 formed to support the LSI chip 8 according to the present invention. A total of four window holes 15 are formed so that the terminals or bumps 9 arranged centrally near the four corners of the rectangular chip 1 are exposed.
Inside the window hole 15, a tape portion that covers the upper surface of the chip 8 remains.

On the back surface of this tape, the lead pattern 2
And the tip of each lead pattern 2 is extended as an inner lead 2a from the inside to the outside in each window hole 15.

On the other hand, a predetermined wiring pattern 16 is formed on the upper surface of the carrier tape body 1a. A part of the wiring pattern 16 serves as the external lead 21 at the edge of the carrier tape 1, and a part of the wiring pattern 16 for the other chip holding portions 14 ″ formed on the same carrier tape. Be extended as'.

Thus, when the module on this tape is mounted on a substrate (not shown) to form a final multi-chip module, according to the present invention, a part of the wiring necessary to form the entire module is used as a carrier. The tape 1 will be shared, wiring to the circuit board will be simplified, and space on the circuit board will be saved.
Finally, high density mounting of multiple chips on the substrate becomes possible.

As described above, according to the present invention,
Since the carrier tape supporting the semiconductor device can share the wiring, when a large number of semiconductor chips are mounted on the circuit board to form a certain functional circuit, higher density mounting is possible, and the circuit configuration is improved. It is possible to greatly contribute to the remarkable miniaturization.

Of course, the scope of the present invention is not limited to the above embodiments. Modifications, changes, implementations or applications within the inventive concept described in each claim of the present application are
All are included in the scope of the present invention.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a first embodiment of the present invention.

FIG. 2 is an enlarged view of part A in FIG.

FIG. 3 is a sectional view taken along line III-III in FIG.

FIG. 4 is an enlarged sectional view taken along line IV-IV in FIG.

FIG. 5 is a schematic plan view of a second embodiment of the present invention.

FIG. 6 is a plan view of a conventional example.

7 is an enlarged sectional view taken along line VII-VII of FIG.

FIG. 8 is a plan view of a semiconductor device packaged in a tape carrier using the carrier tape shown in FIG.

[Explanation of symbols]

 1 TAB carrier tape 1a Tape body 2 Lead pattern 2a Inner lead 8 Semiconductor chip 9 Bump 13 Tape carrier package 14 Chip holding portion 15 Window hole 16 Wiring pattern 18 VIA hole 19 Power noise bypass capacitor 20 Sealing resin injection opening

Claims (7)

[Claims] 1. A lead pattern is formed on a lower surface of a tape main body having a window hole, and bumps on a semiconductor chip are bonded to inner leads extending from the lead pattern into the window hole to form the semiconductor chip. A carrier tape for supporting, wherein the window hole is formed so as to partially face the peripheral edge of the semiconductor chip on which the bump is formed, so that a portion of the tape body that covers the semiconductor chip is formed. A carrier tape for TAB, which is used as a wiring pattern forming region. 2. A lead pattern is formed on a lower surface of a tape body having a window hole, and bumps on a semiconductor chip are bonded to inner leads extended from the lead pattern into the window hole to form the semiconductor chip. A carrier tape for supporting, wherein the window hole is formed so as to partially face a peripheral edge of the semiconductor chip on which the bump is formed, and the lead pattern is formed on the semiconductor body of the tape body. The inner lead is formed on the lower surface of the portion that covers the chip, the inner lead is extended from the lead pattern into the window hole, and the wiring pattern is formed on the upper surface of the tape body. A part or all of the wiring pattern is electrically connected to the selected one of the lead patterns via the VIA hole. Yatape. 3. The tape carrier according to claim 1, wherein the TAB carrier tape is used, bumps on the upper surface of the semiconductor chip are connected to the inner leads, and the upper surface of the semiconductor chip is resin-sealed. package. 4. A tape main body having a predetermined width and having a constant length in the longitudinal direction, wherein the tape main body is formed with a plurality of memory chip holding portions in the longitudinal direction. Comprises a pair of window holes formed at regular intervals, a lead pattern formed in a region between the window holes on the back surface of the tape body, and an inner lead extending from the lead pattern into the window hole. On the upper surface of the tape body, a plurality of signal wiring patterns extending in the longitudinal direction are formed over the respective memory chip holding portions. In each of the memory chip holding portions, selection of the signal wiring pattern is performed. Carrier for a memory chip, characterized in that the selected one is conducted to the selected one of the lead patterns through a VIA hole. Over-flops. 5. The signal wiring pattern includes an address bus pattern and / or a data bus pattern, and each bus pattern is a VIA for a selected read pattern in each memory chip holding unit. The carrier tape for a memory chip according to claim 4, wherein the carrier tapes are commonly connected through a hole. 6. The power supply wiring pattern and the ground wiring pattern, which are formed in the longitudinal direction of the tape body over the respective memory chip holding portions, are further provided on the upper surface of the tape body. 5. The carrier tape for a memory chip according to claim 4, wherein a bypass capacitor bridging between the power supply wiring pattern and the ground wiring pattern is mounted. 7. A plurality of memory chips having terminals with bumps formed in the vicinity of a side facing the upper surface using the carrier tape for a memory chip according to claim 4,
A tape carrier package for a memory chip, wherein each of the memory chip holding portions is supported by bonding the bump to an inner lead extending to each window hole.