JPH06302687A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contract an element isolation region by simultaneously conducting the steps of ion implanting impurity for regulating a transistor threshold value voltage and channel stop implanting, and the channel stop implanting over a silicon oxide film to be formed on the isolation region. CONSTITUTION:An oxidation resistant layer 103 is selectively formed on a region formed with a semiconductor element, and a surface of a silicon substrate 101 of a region not covered with the layer 103 is oxidized to form an element isolation region 106. Impurity ions of the same type as that of a silicon substrate 101 are implanted by acceleration energy arriving at the substrate 101 through the region 106 and the layer 103. Thereafter, the steps of impurity ion implanting for regulating a transistor threshold value voltage and channel stop implanting can be simultaneously conducted, thereby reducing the number of steps and a cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device having a field effect transistor element forming a semiconductor integrated circuit formed on a semiconductor substrate and an element isolation region for electrically isolating a plurality of elements.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memor)
y), SRAM (Static Random Access Memory) and other VLSIs (Large Scale Integrated circuits)
The capacity is increasing four times every three years, and DRAMs currently having a capacity of 256 Kb, 1 Mb or 4 Mb are mainly produced. It will be the mainstream in the future 16
Mb and 64 Mb DRAMs are being studied intensively, and it is certain that the capacity will be further increased to 256 Mb and 1 Gb. Such an improvement in the degree of integration within a limited chip area is brought about by the miniaturization of each element constituting the integrated circuit. For example, the minimum size of a MOS transistor currently used in a 1 Mb DRAM is about 1 μm, and 0.5 μm and 0.2
It is necessary to reduce the size to 5 μm. At the same time, the reduction of the element isolation region is indispensable for high integration, and the isolation width is 1 μm.
It has become necessary to narrow the thickness to less than 0.5 μm.

Generally, a device called a selective oxidation method is used for forming the element isolation region.
No. 268446, Japanese Patent Laid-Open No. 4-22170, and the like. Here, FIGS. 3 and 4 show a method of manufacturing a semiconductor device in which an element isolation region is formed by a conventional selective oxidation method. Hereinafter, a method of manufacturing a semiconductor device will be described with reference to FIGS.

First, the surface of the silicon substrate 201 is thinly oxidized to form a silicon oxide film 202 having a thickness of 10 to 70 nm, and then 100 to 2 is formed by LPCVD (Low Pressure Vapor Deposition).
A 00 nm silicon nitride film 203 is deposited. Next, a resist pattern 204 defining an active region where a semiconductor device is constructed and an element isolation region is formed by a photolithography process. Here, the opening 205 of the resist pattern 204 becomes an element isolation region (FIG. 3A).

Next, using the resist pattern 204 as an etching mask, the silicon nitride film 203 in the opening 205 is formed.
Are etched by the RIE method. As a result, the silicon nitride film 203 is left only in a region which will be an active region later. Here, in order to increase the inversion voltage of the element isolation region, an impurity of the same type as that of the silicon substrate 201 is ion-implanted as needed (for example, boron ions having an energy of 150 ke).
V, and the injection amount is 1 × 10 ¹³ cm ^-2 . ) (Fig. 3
(B)).

Further, after removing the resist pattern 204, if the silicon substrate 201 is thermally oxidized at 1000 to 1100 ° C., oxygen is supplied to the openings 205, the surface of the silicon substrate 201 is oxidized, and silicon for element isolation regions is oxidized. An oxide film 206 (300 to 600 nm) is formed. On the other hand, since the surface of the silicon substrate 201 in the active region is covered with the silicon nitride film 203 which is an oxidation resistant film, oxygen is not supplied and the silicon oxide film does not grow. However,
In the vicinity of the opening 205, the thin silicon oxide film 202 serves as an oxygen supply passage, and the surface of the silicon substrate 201 is oxidized. As a result, the silicon oxide film 206 bites into the silicon nitride film 203 and grows. A region 207 in which the silicon oxide film 206 digs under the silicon nitride film 203 is generally called a bird's beak because of its shape (FIG. 4A).

Next, the silicon nitride film 203 is removed by using a phosphoric acid solution heated to about 150 ° C., whereby thick silicon oxide 206 is selectively left in the element isolation region (FIG. 4B). Here, in order to adjust the threshold voltage of the transistor, boron ions, which are impurities of the same type as the silicon substrate 201, are implanted into the entire surface at 20 keV. With this energy, boron ions do not pass through the element isolation region 206 made of a thick silicon oxide film, and impurities are added only to the surface of the silicon substrate 201 in the active region (FIG. 4).
(C)).

By the way, the boron implantation described in FIG. 3B is intended to increase the inversion voltage of the element isolation region and suppress the expansion of the channel region of the transistor. However, instead of this, the same effect can be obtained by implanting boron ions below the element isolation region 206 at this point (FIG. 4D). That is, in addition to boron implantation for adjusting the threshold voltage, boron is implanted with higher energy to reach the surface of the silicon substrate 201 by penetrating the element isolation region 206 to reduce the impurity concentration below the silicon oxide film 206. Make it higher At this time, boron ions are implanted not only in the element isolation region but also in the active region. However, since the high boron concentration region 208 is formed inside the silicon substrate 201, the surface of the silicon substrate 201 in the active region is hardly affected. In the boron implantation described with reference to FIG. 3B, since the element isolation region 206 is formed after the implantation, a high temperature heat treatment of 1000 ° C. or higher is performed, so that boron re-diffusion occurs. As a result, there is a problem such as a so-called narrow channel effect in which the impurity concentration in the active region near the element isolation region is increased and the effective channel width is narrowed, and further, the threshold voltage is increased in a transistor with a narrow channel width. ing. On the other hand, in the implantation through the isolation oxide film of FIG. 4D, since there is no heat treatment at a high temperature, these problems are solved and it is a method suitable for miniaturization.

Next, after removing the silicon oxide film 202 with a dilute hydrofluoric acid solution, the gate insulating film 2 is subjected to a normal process.
09, the gate electrode 210, the n ⁺ impurity diffusion region 211 as the source and drain regions, the interlayer insulating film 212, the contact wiring 213, the metal wiring 214, etc. are formed and processed, and then electrically separated by the conventional element isolation method. Transistor can be formed (FIG. 4E).

[0010]

As described above, the selective oxidation method has been widely used as a technique for separating semiconductor integrated circuit devices from the past because it can form the device isolation region in a very easy process. However, with the high integration of semiconductor integrated circuits, further reduction of the element isolation region is indispensable. However, the selective oxidation method has the following problems, which makes it difficult to reduce the isolation region. .

First, there is a problem that the miniaturization for enlarging the isolation region, which is called bird's beak, as described above with reference to FIG. 4A, is caused by the biting of the isolation oxide film into the active region. However, the following proposals are actually implemented as a solution to this problem.

For example, a polysilicon pad method ("A 0.5 .mu.m Isola") is used to suppress a bird's beak from biting by arranging a polycrystalline silicon film under a silicon nitride film which is an oxidation resistant film.
tion Technology Using Advanced Poly Silicon Pad LOC
OS (APPL) "T. Nichihara et.al. IEDM88,100-103),
Alternatively, a second film may be formed on the side surface of the patterned silicon nitride film.
Offset Locos method (“A New Isolation Technology for
VLSI ”K.Nojiri et.al. Extended Abstracts17th SSD
M.1985, 337-340).

Second, the narrow channel effect in which the channel of the transistor is narrowed by the re-diffusion of the impurity implanted to prevent the inversion of the isolation region or the threshold voltage of the transistor having a narrow channel width is increased becomes a barrier to miniaturization. .
To address this problem, as described in the related art, it is possible to prevent re-diffusion of impurities by implanting impurities with relatively high energy after forming the isolation oxide film. However, the above method has the following problems.

After forming the isolation oxide film, impurities are implanted into the entire surface with relatively high energy, so that the surface of the silicon substrate is not affected so much, but the impurity concentration inside the silicon substrate in the active region increases. Therefore, when the potential of the silicon substrate changes due to the bias effect of the substrate, there arises a problem that the threshold voltage of the transistor largely changes. Further, since the impurity concentration inside the substrate is increased, n ⁺ / p in the diffusion layer that is the source and drain regions of the transistor is increased.
(Or p ⁺ / n) junction causes an increase in junction capacitance and a decrease in junction breakdown voltage. The increase in the junction capacitance hinders the speeding up of circuit operation, and the decrease in the junction breakdown voltage narrows the allowable voltage range of the semiconductor element and reduces the reliability of the circuit.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide a method of manufacturing a semiconductor device suitable for miniaturization of a semiconductor integrated circuit element.

[0016]

Thus, according to the present invention, there is provided a method of manufacturing a semiconductor device having a semiconductor element and an element isolation region for electrically isolating the semiconductor element on a silicon substrate. An oxidation resistant layer is selectively formed in a region to be formed, the surface of the silicon substrate in a region not covered with the oxidation resistant layer is oxidized to form a device isolation region, and the device isolation region and the acid resistance are formed. A semiconductor device in which impurity ions of the same type as those of the silicon substrate are implanted with acceleration energy that passes through the chemical conversion layer and reaches the silicon substrate, and then the oxidation resistant layer is removed to form an element isolation region. A method of manufacturing the same is provided.

A method of manufacturing the semiconductor device of the present invention will be described below. First, an oxidation resistant layer is laminated on a silicon substrate.
Here, examples of the silicon substrate that can be used in the present invention include substrates having p-type or n-type conductivity. Further, the oxidation resistant layer may have a laminated structure of a plurality of thin films as long as it is a film including at least one oxidation resistant thin film. An example of such an oxidation resistant layer is a silicon nitride film. Further, when a plurality of films are laminated, the structure thereof may be a film composed of a combination of a silicon oxide film, a polycrystalline silicon film and the like. When the oxidation-resistant layer is composed of a plurality of thin films including the oxidation-resistant thin film or the oxidation-resistant thin film, the total thickness of the oxidation-resistant layer is formed so as to have the same ability to prevent impurity ions as the element isolation region to be formed later. Preferably. For example, a silicon substrate is 850 to 10
After thermal oxidation at 00 ° C. to form a silicon oxide film with a thickness of 10 to 50 nm, a silicon nitride layer as an oxidation resistant layer with a thickness of 150 to 250 nm may be laminated by LPCVD (Low Pressure Vapor Deposition). it can.

Next, a resist pattern is formed on the oxidation resistant layer by photolithography. Both positive and negative resist materials can be used. Further, the resist pattern needs to have an opening on an element isolation region to be formed later.

Next, using the resist pattern as an etching mask, the silicon nitride film in the opening is subjected to RIE (reactive ion etching) and ECR (Electron Cyclotron R).
esonance) Etching is used to remove it. In this way, the oxidation resistant layer remains only in the region which will be the active region later.

The resist pattern is removed, and the silicon substrate is thermally oxidized at 1000 to 1100 ° C. This thermal oxidation forms an element isolation region having a layer thickness of 300 to 400 nm. However, the silicon oxide film becomes the oxygen supply channel,
The surface of the silicon substrate in the vicinity of the opening is oxidized so as to push up the end of the oxidation resistant layer to form a so-called bird's beak structure. This bird's beak hinders the miniaturization of the device, but it can also be prevented by using the improvement method described in the section of the prior art to prevent this.

Next, it has the same conductivity type as the silicon substrate.
Impurities are injected. In the present invention, impurities are element isolation regions.
Penetrates through the area and the oxidation resistant layer and becomes the surface layer of the silicon substrate.
Injected. This implantation expands the channel region
Immediately at the same time as
It can be carried out. Impurities to be implanted include N-type transistors.
In the star formation region, P-type impurities such as boron and P-type
In the transistor forming region, N-type impurities such as phosphorus and arsenic
Is mentioned. For example, when implanting boron,
1 × 10 at acceleration energy of 60 to 150 KeV¹²~
1 x 10¹³cm ^-2Injection dose is desired, and phosphorus ion
When injecting, acceleration energy of 150 to 400 KeV
So 1 x 10¹²~ 1 x 10¹³cm^-2Injection amount is desired
It

Next, the oxidation resistant layer is removed using a solution of phosphoric acid heated to about 150 ° C. to form an element isolation region in a desired region. After that, the silicon oxide film is removed with dilute hydrofluoric acid, and then a gate insulating film, a source / drain region, an interlayer insulating film, a contact wiring, a metal wiring, and the like are formed by a known method to obtain a semiconductor device. it can.

[0023]

According to the method of the present invention, since the re-diffusion of the impurities added to the element isolation region is suppressed, it is possible to suppress the narrow channel effect of increasing the threshold voltage in the transistor having a narrow channel width. Further, since the impurity concentration inside the channel substrate is not increased more than necessary, the transistor substrate bias effect is reduced, and the junction capacitance and junction breakdown voltage can be prevented from decreasing.

Further, since the impurity implantation for adjusting the threshold voltage of the transistor and the implantation for the element isolation region for the purpose of channel stop can be performed in the same step, the implantation step and the resist mask forming step can be omitted, and the number of steps can be reduced. And cost reductions.

[0025]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 (a), 1 (b) and 2 (a)-(d). First, the surface of the p-type silicon substrate 101 is thinly oxidized to 30
LPCVD after forming a silicon oxide film 102
A 200 nm silicon nitride film 103 was deposited by (reduced pressure vapor deposition method). Next, a resist pattern 104 that determines an active region where a semiconductor element is formed and an element isolation region.
Was formed by a photolithography process. Here, the opening 105 of the resist pattern 104 becomes an element isolation region (FIG. 1A).

Next, using the resist pattern 104 as an etching mask, the silicon nitride film 103 in the opening 105 is formed.
Was etched by the RIE method. As a result, the silicon nitride film 103 is left only in a region which will be an active region later (FIG. 1B).

After removing the resist pattern 104, the silicon substrate 101 was thermally oxidized at 1000 ° C. to 1100 ° C. Since oxygen was supplied to the opening 105, the surface of the silicon substrate 101 was oxidized and an element isolation region 106 made of a silicon oxide film was formed. In this embodiment, the film thickness of the element isolation region 106 is 350 nm. On the other hand, since the surface of the silicon substrate 101 in the active region is covered with the silicon nitride film 103 which is an oxidation resistant film, oxygen is not supplied and the element isolation region does not grow. However, in the vicinity of the opening 105, the thin silicon oxide film 102 serves as an oxygen supply passage, and the surface of the silicon substrate 101 under the silicon nitride film 103 is oxidized, so that the element isolation region 1 is formed.
06 bites in the form of pushing up the silicon nitride film 103 and grows. A region 107 in which the element isolation region 106 digs under the silicon nitride film 103 is generally called a bird's beak because of its shape (FIG. 2A).

Next, boron implantation for channel stop implantation which defines the spread of the transistor channel region was performed at this stage. In this embodiment, energy 130 Ke
v, boron was injected at an injection amount of 4 × 10 ¹² cm ^-2 . Under this implantation condition, since the range of boron ions is 0.39 μm in the silicon oxide film, the element isolation region 106 having a film thickness of 350 nm in the element isolation region formed in this embodiment penetrates the surface of the silicon substrate 101. It was driven in. Also, since the range is 0.30 μm with respect to the silicon nitride film,
200 nm silicon nitride film 103 even in the active region
And boron ions are implanted into the surface of the silicon substrate 101 through the silicon oxide film 102 of 30 nm and
Impurity region 108 is formed.

As described above, by using this method, it is possible to perform the impurity ion implantation for adjusting the threshold voltage of the transistor and the channel stop implantation in a single implantation step (FIG. 2 (b)). ). Next, the silicon nitride film 103 is removed using a phosphoric acid solution heated to about 150 ° C., so that the element isolation region 106 that is thicker than the isolation region is selectively formed.
Could be left (FIG. 2 (c)).

Next, after removing the silicon oxide film 102 with a dilute hydrofluoric acid solution, the gate insulating film 1 is subjected to a normal process.
09, the gate electrode 110, the n ⁺ diffusion region 111 as the source and drain regions, the interlayer insulating film 112, the contact wiring 113, the metal wiring 114, etc. are formed and processed to form the element isolation region and the field effect transistor according to the present invention. It was able to be formed (FIG.2 (d)).

In the field effect transistor formed by the above steps, the impurity ion implantation for adjusting the transistor threshold voltage and the channel stop implantation can be simultaneously performed in the same ion implantation step, so that it is possible to manufacture an integrated circuit. It was possible to reduce the number of steps and the cost.

Furthermore, since the channel stop implantation is performed through the silicon oxide film formed in the isolation region and the impurities are added, the re-diffusion of the impurities can be reduced. Therefore, even in a transistor having a narrow channel width, the narrow channel effect in which the impurity concentration in the channel portion is increased and the threshold voltage is increased is suppressed, and the channel width is 0.4 μm.
It was possible to obtain a transistor having a constant threshold voltage up to m. Also in the active region, by implanting impurities through the silicon nitride film, it was possible to increase the impurity concentration only in the surface portion of the silicon substrate and set the threshold voltage. As a result, the impurity concentration inside the active region substrate is suppressed to a relatively low concentration, so that it is possible to reduce the substrate bias effect and the junction capacitance. For example, in the case of joining formed by the conventional method, 8 × 1 per unit area
The junction capacitance, which was 0 ^-4 F / m ² , could be reduced to 5 × 10 ^-4 F / m ² . This reduction in the junction capacitance has made it possible to speed up the circuit operation. That is, when operating the circuit, the junction capacitance acts as a parasitic capacitance.

[0033]

As is apparent from the above, according to the method of manufacturing a semiconductor device of the present invention, not only the manufacturing process of semiconductor circuit elements can be shortened and the cost can be reduced, but also the narrow channel effect can be suppressed and the substrate bias can be reduced. By suppressing the effect and reducing the junction capacitance, the semiconductor element can be miniaturized, the reliability can be improved, and the speed can be increased.

[Brief description of drawings]

FIG. 1 is a schematic sectional view illustrating an embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating an embodiment of the present invention.

FIG. 3 is a schematic sectional view illustrating a conventional example.

FIG. 4 is a schematic sectional view illustrating a conventional example.

[Explanation of symbols]

101, 201 silicon substrate 102, 202 silicon oxide film 103, 203 silicon nitride film 104, 204 resist pattern 105, 205 opening of resist pattern 106, 206 element isolation region 107, 207 bird's beak 108, 208 impurity region 109, 209 gate insulation Films 110, 210 Gate electrodes 111, 211 n ⁺ diffusion regions 112, 212 Interlayer insulating films 113, 213 Contact wiring 114, 214 Metal wiring

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a semiconductor element and an element isolation region for electrically isolating the semiconductor element on a silicon substrate, wherein an oxidation resistant layer is selected in a region where the semiconductor element is formed. Formed on the surface of the silicon substrate to oxidize the surface of the silicon substrate in a region not covered by the oxidation resistant layer to form a device isolation region, and then reach the silicon substrate through the device isolation region and the oxidation resistant layer. A method of manufacturing a semiconductor device, characterized in that impurity ions of the same type as those of the silicon substrate are implanted with an accelerating energy to form an element isolation region by removing the oxidation resistant layer. 2. A layer thickness of an oxidation resistant layer formed in a region where a semiconductor element is formed, and a film thickness of an element isolation region have equivalent blocking ability to implanted impurity ions. The method for manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the oxidation resistant layer is composed of a plurality of thin films including at least one oxidation resistant thin film.