JPH0628388A - Vector calculator - Google Patents

Abstract

PURPOSE:To realize a high-speed vector arithmetic processing on the vector calculator executing the vector arithmetic processing according to the vector arithmetic pipeline. CONSTITUTION:The vector calculator is provided with a 1st pipeline and a 2nd pipeline with a throughput different from that of the 1st pipeline. Following a preceding instruction applied to the 1st pipeline, succeeding instructions causing register interference with the preceding instruction are inputted to the 2nd pipeline. The calculator is provided with a detection section 11 detecting the arithmetic operation end time point of the 1st element of the preceding instruction according to the number of stages of the 1st pipeline and a counting section 12 performed the counting processing of the counting speed prescribed by the difference of the throughputs between two instructions when the detection section 11 detects the arithmetic operation end time point and when the counted value reaches the value corresponding to the number of elements of the preceding instruction outputting the purport. When the section 12 outputs 12 outputs the arrival of the counted value, the succeeding instructions are applied to the 2nd pipeline.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector computer that executes vector arithmetic processing according to a vector arithmetic pipeline, and more particularly to a vector computer that enables high-speed vector arithmetic processing.

In recent years, vector computers have a plurality of vector operation pipelines and execute vector operations in parallel to improve data processing performance. However, when the result operand of the preceding instruction and the input operand of the succeeding instruction use the same vector register, the succeeding instruction must be input after the result of the preceding instruction is written in the vector register. If you don't, you'll have to look ahead.

However, the input of the subsequent instruction does not have to wait until the result operands for all elements of the preceding instruction have been written to the vector register. That is, even if there is register interference as described above, if the result of the first element of the preceding instruction is written in the case of an arithmetic instruction processed in the same element order,
It is possible to immediately start the subsequent instruction and input the first element without waiting for writing to the last element. It is called that such a relationship between the preceding instruction and the subsequent instruction is linked.

[0004]

2. Description of the Related Art In a conventional vector computer, when register interference occurs, link control is executed only when the preceding and succeeding instructions have the same operation throughput and the elements have the same operation processing order. It was being done.

That is, as shown in FIG. 8, the number of stages of the vector operation pipeline of the preceding instruction is 5, the throughput is 1τ, and the element order of the preceding instruction is "0, 1, 2,
3,4,5,6 ”, on the other hand, the number of stages of the vector operation pipeline of the subsequent instruction is 4 and the throughput is 1τ,
In the case where the element order of the subsequent instruction is “0,1,2,3,4,5,6”, the result of the element 0 of the preceding instruction is written to the vector register at the next timing. Since the element 0 of the succeeding instruction can be input and the result of the element 1 of the preceding instruction is written to the vector register, the element 1 of the succeeding instruction can be input, so that the first instruction of the preceding instruction can be input. When the result of the second element was written to the vector register, the link control was executed to immediately start the subsequent instruction.

[0006]

However, in the prior art, the link control is executed only when the throughputs of the preceding instruction and the succeeding instruction are equal and the element order is equal. That is, when the throughput differs between the preceding instruction and the succeeding instruction, or when the element order is different, the input of the succeeding instruction is waited until the result of the final element of the preceding instruction is obtained without executing the link control. The method of letting it happen was adopted. From now on, there is a problem that the data processing efficiency is deteriorated.

The present invention has been made in view of the above circumstances. When register interference occurs between a preceding instruction and a succeeding instruction, the preceding instruction and the succeeding instruction have different throughputs, and the element order is different. It is an object of the present invention to provide a new vector computer that realizes performance improvement by realizing link control even when different.

[0008]

FIG. 1 shows the principle configuration of the present invention. In the figure, 1 is a vector register that holds vector data, and 2 is a first vector operation pipeline, which executes specified operation processing on two vector data read from the vector register 1 according to a predetermined number of stages. 3 is a second vector operation pipeline, which executes specified operation processing on two vector data read from the vector register 1 according to a predetermined number of stages, and 4 is first and second Is an instruction management unit that executes management processing of the vector operation pipelines 2 and 3.

The instruction management unit 4 manages the subsequent instruction transmission check unit 5 for checking the transmission of the subsequent instruction, and the operation progress state of the first vector operation pipeline 2 so that the second vector operation pipeline is operated. The first arithmetic pipe management unit 6 that manages whether or not 3 is in the state of being able to transmit
And managing the operation progress state of the second vector operation pipeline 3, the first vector operation pipeline 2
A second arithmetic pipe management unit 7 that manages whether or not the call is in a state where it can make a call.

Reference numeral 8 is a register interference detection unit provided in the subsequent instruction transmission check unit 5 for detecting whether or not register interference occurs between the preceding instruction and the subsequent instruction, and 9 is the subsequent instruction transmission check unit 5. Which is a second pipe start unit included in the above, and in response to the output of the first arithmetic pipe managing unit 6, activates the second arithmetic pipe managing unit 7 and activates the second vector arithmetic pipeline 3. Things, 10
Is a first pipe start unit included in the subsequent instruction transmission check unit 5, and when the preceding instruction uses the first vector operation pipeline 2, the first arithmetic pipe management unit enters the execution of the preceding instruction. The first vector operation pipeline 2 is started while the section 6 is started.

Reference numeral 11 denotes a detection unit provided in the first arithmetic operation pipe management unit 6, which detects a preceding instruction input to the first vector arithmetic operation pipeline 2 in accordance with the number of stages of the first vector arithmetic operation pipeline 2. Detecting the end time of the operation of the first element, reference numeral 12 is a counting unit included in the first operation pipe management unit 6, and when the detection unit 11 detects the end time of the operation of the first element, It enters the counting process of the counting speed specified by the difference in the throughput of the instruction and the subsequent instruction, and outputs that when the count value of this counting process reaches the value according to the number of elements of the preceding instruction. is there.

[0012]

In the present invention, when the preceding instruction uses the first vector operation pipeline 2 and the subsequent instruction uses the second vector operation pipeline 3, the first pipe start unit 10 is The first arithmetic pipe management unit 6 and the first vector arithmetic pipeline 2 are activated to start the execution of the instruction. At this time, if the register interference detection unit 8 detects register interference between the preceding instruction and the subsequent instruction, the second
The pipe start unit 9 suspends the activation of the second arithmetic pipe management unit 7 and the second vector arithmetic pipeline 3.

Upon receiving the activation instruction from the first pipe start unit 10, the detection unit 11 detects the operation end time of the first element of the preceding instruction according to the number of stages of the first vector operation pipeline 2. In response to this detection time, the counting unit 12 determines that the throughput of the preceding instruction is 2τ.
If the throughput of the subsequent instruction is 1τ, then 2τ
The counting process proceeds in units, and the throughput of the preceding instruction is 3
If the throughput of the subsequent instruction is 1τ at τ, then 3
As the counting process proceeds in increments of τ, it enters the counting process of the counting speed specified by the difference in the throughput of the preceding instruction and the subsequent instruction, and the count value of this counting process depends on the number of elements of the preceding instruction. When that value is reached, it is output to that effect. Upon receiving the output of the counting unit 12,
The second pipe start unit 9 includes the second arithmetic pipe management unit 7
Then, the second vector operation pipeline 3 is activated to instruct execution of the subsequent instruction.

According to the processing executed by the first arithmetic pipe management unit 6, as shown in FIG. 2, the number of stages of the first vector arithmetic pipeline 2 for executing the preceding instruction is five.
, The throughput is 2τ, the element order of the preceding instruction is “0,1,2,3,4,5,6,7”, while the stage of the second vector operation pipeline 3 that executes the succeeding instruction. Even if the number is 4, the throughput is 1τ, and the element order of the subsequent instructions is "0,1,2,3,4,5,6,7", until the result of the last element of the preceding instruction is obtained. The subsequent instruction can be input to the second vector operation pipeline 3 without waiting.

Further, as shown in FIG. 3, the number of stages of the first vector operation pipeline 2 for executing the preceding instruction is 5, the throughput is 2τ, and the element order of the preceding instruction is “0, 2, 4, 6,1,3,5,7 ", while the number of stages of the second vector operation pipeline 3 that executes the subsequent instruction is 4, the throughput is 1τ, and the element order of the subsequent instruction is" 0,1 ". , 2,3,4,5,6,7 ”even if you do not wait until the result of the last element of the preceding instruction is obtained,
The subsequent instruction can be input to the second vector operation pipeline 3.

Further, as shown in FIG. 4, the number of stages of the first vector operation pipeline 2 for executing the preceding instruction is 5, the throughput is 3τ, and the element order of the preceding instruction is “0, 3, 6, 1,4,7,2,5 ", while the number of stages of the second vector operation pipeline 3 that executes the subsequent instruction is 4, the throughput is 1τ, and the element order of the subsequent instruction is" 0,1 ". , 2,3,4,5,6,7 ”even if you do not wait until the result of the last element of the preceding instruction is obtained,
The subsequent instruction can be input to the second vector operation pipeline 3.

As described above, according to the present invention, the subsequent instruction can be executed without waiting until the result of the final element of the preceding instruction is obtained.

[0018]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 5 illustrates a device configuration of the vector computer. As shown in this figure, the vector computer has a main memory 100 for storing vector data of main memory data, two access pipelines 200 for accessing the main memory 100, and vector data accessed by the access pipeline 200. Vector register 1 to store
And two vector data from the vector register 1 are subjected to prescribed arithmetic processing and the arithmetic result is written into the vector register 1, and the two vector data from the vector register 1 are prescribed and read. And a second vector operation pipeline 3 for writing the operation result to the vector register 1, and an instruction management unit 4 for executing the management processing of the first and second vector operation pipelines 2 and 3. It is composed of

FIG. 6 shows an embodiment of the circuit configuration of the instruction management unit 4. As described in FIG. 1, the instruction management unit 4
Is composed of a succeeding instruction transmission check unit 5, a first arithmetic pipe management unit 6, and a second arithmetic pipe management unit 7.

The subsequent instruction transmission check unit 5 includes an instruction register 20, comparison circuits 21a and 21b, check circuits 22a and 22b, AND circuits 23a and 23b, flip-flop circuits 24a and 24b, and an AND circuit 25.
a and 25b and AND circuits 26a and 26b.
Here, the circuit with "a" is provided to control the first vector operation pipeline 2, and "b" is provided.
The circuit marked with is provided for controlling the second vector operation pipeline 3.

The instruction register 20 holds the same instruction that is input to the first and second vector operation pipelines 2 and 3. The comparison circuit 21a has a HIGH level (hereinafter abbreviated as HI level) when the preceding instruction is input to the second vector operation pipeline 3 and when register interference occurs between the preceding instruction and the subsequent instruction. When the register interference does not occur, a LOW level (hereinafter abbreviated as LO level) is output. The check circuit 22a outputs H from the terminal when the instruction is an instruction to be executed in the first vector operation pipeline 2.
Outputs I level and outputs second vector operation pipeline 3
When it is an instruction to be executed in, a LO level is output from the terminal, and when other transmission conditions for entering execution in the first vector operation pipeline 2 are satisfied, a HI level is output from the terminal,
When not established, the LO level is output from the terminal.

In the AND circuit 23a, the comparison circuit 21a has an H level.
In addition to outputting the I level, the check circuit 22a outputs the HI level when the terminal outputs the HI level, and otherwise outputs the LO level. The flip-flop circuit 24a is set when the AND circuit 23a outputs the HI level and outputs the HI level,
It is reset according to the reset instruction from the second arithmetic pipe management unit 7 and outputs the LO level. As will be understood later, use of the first vector operation pipeline 2 is prohibited while the flip-flop circuit 24a outputs the HI level. The AND circuit 25a outputs the HI level when the flip-flop circuit 24a outputs the LO level and the check circuit 22a outputs the HI level from the terminal, and otherwise outputs the LO level. AND circuit 26
a transfers the instruction held in the instruction register 20 to the first arithmetic pipe management unit 6 when the AND circuit 25a outputs the HI level.

On the other hand, in the comparison circuit 21b, the first instruction is the first instruction.
When the register interference occurs between the preceding instruction and the succeeding instruction, the HI level is output, and when the register interference does not occur, the LO level is output. The check circuit 22b outputs the HI level from the terminal when the instruction is to be executed in the second vector operation pipeline 3, and outputs the LO level from the terminal when the instruction is to be executed in the first vector operation pipeline 2. In addition to the output, the HI level is output from the terminal when the transmission condition is satisfied for the other transmission conditions for entering the execution in the second vector operation pipeline 3, and the LO level is output from the terminal when the transmission condition is not satisfied.

In the AND circuit 23b, the comparison circuit 21b has an H level.
In addition to outputting the I level, the check circuit 22b outputs the HI level when the HI level is output from the terminal, and otherwise outputs the LO level. The flip-flop circuit 24b is set when the AND circuit 23b outputs the HI level and outputs the HI level,
It is reset according to the reset instruction from the first arithmetic pipe management unit 6 and outputs the LO level. As will be understood later, use of the second vector operation pipeline 3 is prohibited while the flip-flop circuit 24b outputs the HI level. The AND circuit 25b outputs the HI level when the flip-flop circuit 24b outputs the LO level, the check circuit 22b outputs the HI level from the terminal, and otherwise outputs the LO level. AND circuit 26
b transfers the instruction held in the instruction register 20 to the second arithmetic pipe management unit 7 when the AND circuit 25b outputs the HI level.

On the other hand, the first arithmetic pipe management unit 6 includes an instruction register 30, a shifter 31, a programmable register 32, an AND circuit 33, and a counter 34. Here, although omitted in FIG. 6, the second arithmetic pipe management unit 7 is also composed of a similar circuit.

The instruction register 30 holds the instruction transferred from the AND circuit 26a. The shifter 31 is the first
The number of stages of the vector operation pipeline 2 is one less than the number of shift registers, and the AND circuit 2
When 5a outputs the HI level, the delay process for the number of shift registers is executed. The programmable register 32 outputs a value that is one less than the number of elements included in the instruction executed in the first vector operation pipeline 2. The AND circuit 33 outputs the output value output from the programmable register 32 when the shifter 31 outputs the HI level delayed output. The counter 34 uses the value output from the AND circuit 33 as the initial value of the count value, counts down the count value according to the countdown speed defined by the difference in throughput between the preceding instruction and the subsequent instruction, and the count value is zero. When it reaches, the reset instruction is output to the flip-flop circuit 24b.

Next, the instruction management unit 4 configured as above
The operation processing of will be described. Here, for convenience of explanation,
The first vector operation pipeline 2 has five stages.
, The throughput is 2τ, and the second vector operation pipeline 3 has four stages and the throughput is 1τ. Therefore, the shifter 31 of the first arithmetic pipe management unit 6 is composed of four shift registers as shown in FIG. Then, it is assumed that the preceding instruction executed in the first vector operation pipeline 2 and the subsequent instruction executed in the second vector operation pipeline 3 have the same operation order.

It is assumed that the preceding instruction "VA 001,002,003" is held in the instruction register 20 of the succeeding instruction transmission check unit 5. Here, the operation code VA represents an instruction to be executed in the first vector operation pipeline 2. Specifically, this instruction inputs the data in the vector register 002 and the data in the vector register 003, executes an operation in the first vector operation pipeline 2, and writes the operation result in the vector register 001. I'm telling you. Here, the operation code VA is transferred to the OP field,
"001" is the result operand to the R1 field,
“002” and “003” are R2 as an input operand
It is set to R3 respectively.

When the preceding instruction is set in the instruction register 20, the check circuit 22a knows that it is an instruction to be operated in the first vector operation pipeline 2 according to the operation code, and therefore outputs the HI level from the terminal. At the same time, it determines whether or not the transmission conditions for other transmission conditions for starting execution in the first vector operation pipeline 2 are satisfied, and outputs the HI level from the terminal. On the other hand, the comparison circuit 21a outputs the LO signal in response to the fact that the subsequent instruction is not set and the register interference does not occur.
Output level. From now on, the AND circuit 23a becomes L
The O level is output, and the flip-flop circuit 24a receives the LO level output and outputs the LO level.

The AND circuit 25a receives the LO level output of the flip-flop circuit 24a and the check circuit 22a.
The HI level output from the terminal of the first vector operation pipeline 2 is output to output the HI level.
To the AND circuit 26a while instructing the AND circuit 26a to execute the preceding instruction "VA 001, 002, 003" set in the instruction register 20. The transfer is instructed to the instruction register 30 of the first arithmetic pipe management unit 6, and the shifter 31 of the first arithmetic pipe management unit 6 is further used.
To the start of execution of element 0 of this instruction.

According to the activation instruction from the AND circuit 25a, the first vector operation pipeline 2 starts executing the preceding instruction "VA 001,002,003". Then, in response to the notification from the AND circuit 25a, the shifter 31 enters the shift operation in synchronization with the start of execution of the preceding instruction, and as shown in FIG.
Shifts the HI level notified from the AND circuit 25a every time the shifts the stage of the first vector operation pipeline 2. Then, in accordance with the transfer instruction to the AND circuit 26a, of the instructions set in the instruction register 20 of the subsequent instruction transmission check unit 5, the operation code VA is
In the OP field of the instruction register 30 of the first arithmetic pipe management unit 6, "001" is set in the R1 field as a result operand, and "002" and "003" are set in R2 and R3 as input operands, respectively.

Next, it is assumed that the subsequent instruction "VB 004, 001, 005" is held in the instruction register 20 of the subsequent instruction transmission check unit 5. Here, the operation code VB represents that it is an instruction to be executed in the second vector operation pipeline 3. Specifically, this instruction inputs the data in the vector register 001 and the data in the vector register 005, executes an operation in the second vector operation pipeline 3, and writes the operation result in the vector register 004. I'm telling you. Here, the operation code VB is transferred to the OP field.
“004” is the result operand to the R1 field,
"001" and "005" are R2 as an input operand.
It is set to R3 respectively.

When this subsequent instruction is set, the comparison circuit 21b causes the instruction register 2 of the subsequent instruction transmission check unit 5 to perform the operation.
By comparing the R2 / R3 field of 0 with the R1 field of the instruction register 30 of the first arithmetic pipe management unit 6, it is checked whether register interference occurs between the preceding instruction and the subsequent instruction. . In this example, the preceding instruction R1 and the succeeding instruction R2 are both in the vector register 00.
Since 1 is used and register interference occurs, the comparison circuit 21b outputs the HI level according to the check result. On the other hand, since the check circuit 22b knows that the instruction should be executed in the second vector operation pipeline 3 according to the operation code of the subsequent instruction, it outputs the HI level from the terminal and the second vector operation pipe. In line 3, it is judged whether the transmission conditions for other transmission conditions for starting execution are satisfied, and the HI level is output from the terminal.

HI level output of the comparison circuit 21b,
Upon receiving the HI level output from the terminal of the check circuit 22b, the AND circuit 23b outputs the HI level, and upon receiving this HI level output, the flip-flop circuit 24
b outputs the HI level. And the AND circuit 25
b receives the HI level output of the flip-flop circuit 24b, and even if the transmission conditions for other transmission conditions for entering execution in the second vector operation pipeline 3 are satisfied. , LO level is output. According to the LO level output of the AND circuit 25b,
For the second vector operation pipeline 3, the above-mentioned "VB004,00 set in the instruction register 20 is set.
It is instructed not to execute the subsequent instruction "1,005".

On the other hand, when the shifter 31 enters the shift operation in synchronization with the start of execution of the preceding instruction "VA 001, 002, 003" as described above, as shown in FIG. First vector operation pipeline 2
Therefore, the HI level is output to the AND circuit 33 at the time of ending the arithmetic processing. In response to this output, the AND circuit 33 sets a value, which is one less than the number of elements of the preceding instruction output from the program register 32, in the counter 34 as an initial value. In the example of FIG. 7, since the number of elements of the preceding instruction is assumed to be “13”, the counter 34 is set to “12” as the initial value.

When the initial value for starting counting is set, the counter 34 is executed in the second vector operation pipeline 3 when the throughput of the preceding instruction executed in the first vector operation pipeline 2 is 2τ. Corresponding to the throughput of the subsequent instruction being 1τ, as shown in FIG.
The count value is counted down in units of τ. When the count value reaches zero, the flip-flop circuit 2
By sending a reset instruction to 4b, the flip-flop circuit 24b is controlled to output the LO level.

When the flip-flop circuit 24b outputs the LO level, the AND circuit 25b outputs the LO level output of the flip-flop circuit 24b and the check circuit 22.
Upon receiving the HI level output from the terminal b, the above-mentioned "VB 004, 001, 00 set in the instruction register 20 is sent to the second vector operation pipeline 3.
5 ”will be instructed to start execution of the subsequent instruction.

Thus, as shown in FIG. 7, the number of stages of the first vector operation pipeline 2 for executing the preceding instruction is 5 and the throughput is 2τ, while the second vector for executing the succeeding instruction is the second. Even when the number of stages of the vector operation pipeline 3 of 4 is 4 and the throughput is 1τ, the succeeding instruction is processed by the second vector operation pipeline 3 without waiting until the result of the final element of the preceding instruction is obtained. Can be put into.

As described with reference to FIGS. 3 and 4, even when the element order of the preceding instruction and the succeeding instruction is different, it is not necessary to wait until the result of the final element of the preceding instruction is obtained. Then, the subsequent instruction can be input to the second vector operation pipeline 3.

[0040]

As described above, according to the present invention,
Even if there is a difference in throughput or a difference in element order between the preceding vector instruction and the following vector instruction,
It is possible to enter the execution of the subsequent vector instruction without waiting until the result of the final element of the preceding vector instruction is obtained. From now on, high-speed vector operation processing can be realized.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of processing of the present invention.

FIG. 3 is an explanatory diagram of a process of the present invention.

FIG. 4 is an explanatory diagram of processing of the present invention.

FIG. 5 is a system configuration diagram of a vector computer.

FIG. 6 is an example of a circuit configuration of an instruction management unit.

FIG. 7 is an explanatory diagram of a process of the embodiment.

FIG. 8 is an explanatory diagram of an instruction link.

[Explanation of symbols]

 1 Vector Register 2 First Vector Operation Pipeline 3 Second Vector Operation Pipeline 4 Instruction Management Unit 5 Subsequent Instruction Transmission Check Unit 6 First Operation Pipe Management Unit 7 Second Operation Pipe Management Unit 8 Register Interference Detection Unit 9 Second pipe start unit 10 First pipe start unit 11 Detection unit 12 Counting unit

Claims (1)

[Claims] 1. A first vector operation pipeline, and a second vector operation pipeline having a throughput different from that of the first vector operation pipeline are provided, and the first vector operation pipeline is input to the first vector operation pipeline. In a vector computer that inputs a subsequent instruction that causes register interference with the preceding instruction into the second vector operation pipeline, in accordance with the number of stages of the first vector operation pipeline, (11) that detects the operation end time of the first element of the preceding instruction that is input to the vector operation pipeline, and when the detection unit (11) detects the operation end time of the first element , Enter the counting process of the counting speed specified by the difference in throughput between the preceding instruction and the subsequent instruction,
A counting unit (12) which outputs a message when the count value obtained by the counting process reaches a value according to the number of elements of the preceding instruction.
And a vector calculator characterized in that, when the counting unit (12) outputs a count value arrival, processing is performed so that subsequent instructions are input to the second vector operation pipeline.