JPH06283844A - Insulating circuit board - Google Patents

Insulating circuit board

Info

Publication number
JPH06283844A
JPH06283844A JP9041093A JP9041093A JPH06283844A JP H06283844 A JPH06283844 A JP H06283844A JP 9041093 A JP9041093 A JP 9041093A JP 9041093 A JP9041093 A JP 9041093A JP H06283844 A JPH06283844 A JP H06283844A
Authority
JP
Japan
Prior art keywords
film
conductor pattern
circuit board
solder
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9041093A
Other languages
Japanese (ja)
Inventor
Fumisuke Ogawa
文輔 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9041093A priority Critical patent/JPH06283844A/en
Publication of JPH06283844A publication Critical patent/JPH06283844A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Abstract

PURPOSE:To prevent deterioration of reliability by preventing formation of intermetallic compounds due to solder on an insulating circuit board having a conductor pattern applied with an Au film thereby preventing the soldering strength from lowering due to the intermetallic compounds. CONSTITUTION:A conductor pattern applied, at least on the surface thereof, with an Au film 23 is formed on an insulating substrate 1 of alumina ceramic, for example, and an electronic component 4 is mounted on the conductor pattern through a tin solder 5. In such insulating circuit board, a second conductor pattern 3 laminating an Ni film 31 and a thin Au film 32 is formed on the surface of the conductor pattern where the Au film 23 is soldered. Even if an Au-Sn intermetallic compound 6 is produced when a component is soldered to the thin Au film 32, the Ni film 31 functions as a barrier for blocking spread of the intermetallics 6 up to the Au film 23 of the conductor pattern 2 thus preventing deterioration of bonding strength or reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は絶縁基板、例えばアルミ
ナセラミック基板に導体パターンを形成した回路基板に
関し、特に錫半田による接合の強度劣化を防止して信頼
性の向上を図った絶縁回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board in which a conductor pattern is formed on an insulating substrate, for example, an alumina ceramic substrate, and more particularly to an insulating circuit board which prevents deterioration of joint strength due to tin solder and improves reliability. .

【0002】[0002]

【従来の技術】従来のアルミナセラミック基板(以下、
絶縁基板と略称する)の表面に導体薄膜パターンを形成
した回路基板の一例を図3に示す。同図において、1は
絶縁基板であり、その表面に順次Ta2 N膜21、Ni
−Cr膜22、Au膜23を順次形成した多層構造の導
体膜を形成し、かつこの導体膜をフォトリソグラフィ技
術により所要のパターンに形成し、導体パターン2を形
成する。また、絶縁基板1の裏面にもNi−Cr膜22
とAu膜23からなる導体パターン2を形成している。
そして、この導体パターン2にチップ状の電子部品4を
搭載するために、その電極をSn63共晶半田5を用い
て導体パターン2のAu膜23に接合させている。
2. Description of the Related Art Conventional alumina ceramic substrates (hereinafter referred to as
FIG. 3 shows an example of a circuit board having a conductor thin film pattern formed on the surface of an insulating substrate). In the figure, 1 is an insulating substrate, on the surface of which a Ta 2 N film 21 and Ni are sequentially formed.
A conductor film having a multi-layer structure in which the -Cr film 22 and the Au film 23 are sequentially formed is formed, and this conductor film is formed into a desired pattern by the photolithography technique to form the conductor pattern 2. The Ni-Cr film 22 is also formed on the back surface of the insulating substrate 1.
And the conductor pattern 2 composed of the Au film 23 is formed.
Then, in order to mount the chip-shaped electronic component 4 on the conductor pattern 2, the electrode thereof is bonded to the Au film 23 of the conductor pattern 2 by using Sn63 eutectic solder 5.

【0003】[0003]

【発明が解決しようとする課題】このような従来の回路
基板では、導体パターンの最上層には半田との濡れ性の
良いAu膜23が設けられ、このAu膜23に対してS
n63共晶半田5を用いて電子部品4の接合を行ってい
るため、同図に示すように、半田5がAu膜23中に拡
散されて半田付け部の広範囲にわたってAu−Sn系金
属間化合物6が生成されてしまう。このような金属間化
合物が生成されると、この部分でのAu膜23と下地の
Ni−Cr膜22との結合力が低下され、電子部品4の
部品接合強度の劣化、及び信頼性の低下が生じることが
ある。このため、従来では厳しい工事条件の管理及び作
業者の技能管理でこれに対処しているが、管理が極めて
難しく、所期の効果を得ることが困難である。本発明の
目的は、半田による金属間化合物の生成を防止し、この
金属間化合物が原因とされる半田接合強度の劣化や信頼
性の低下を防止した絶縁回路基板を提供することにあ
る。
In such a conventional circuit board, an Au film 23 having a good wettability with solder is provided on the uppermost layer of the conductor pattern.
Since the electronic component 4 is bonded using the n63 eutectic solder 5, as shown in the figure, the solder 5 is diffused in the Au film 23 and the Au-Sn based intermetallic compound is spread over a wide range of the soldering portion. 6 is generated. When such an intermetallic compound is generated, the bonding force between the Au film 23 and the underlying Ni—Cr film 22 is reduced in this portion, the component bonding strength of the electronic component 4 is degraded, and the reliability is reduced. May occur. Therefore, in the past, this has been dealt with by managing severe construction conditions and skill management of workers, but it is extremely difficult to manage and it is difficult to obtain the desired effect. It is an object of the present invention to provide an insulated circuit board which prevents generation of intermetallic compounds by solder and prevents deterioration of solder joint strength and deterioration of reliability due to the intermetallic compounds.

【0004】[0004]

【課題を解決するための手段】本発明は、絶縁基板に形
成した導体パターンの上層がAu膜で構成されてなる絶
縁回路基板において、少なくとも導体パターンの錫半田
付け部の表面にNi膜と薄いAu膜とを積層した第2導
体パターンを形成している。例えば、アルミナセラミッ
ク基板上に、Ta2 N膜、Ni−Cu膜、Au膜を積層
した導体パターンを形成し、少なくともこの導体パター
ンの表面の半田付け部にNi膜と薄いAu膜とを積層し
た第2導体パターンを形成する。また、第2導体パター
ンのAu膜の錫半田付け部の表面に予備半田層を形成し
てもよい。
According to the present invention, in an insulated circuit board in which an upper layer of a conductor pattern formed on an insulating substrate is composed of an Au film, at least a surface of a tin soldering portion of the conductor pattern has a Ni film and a thin film. A second conductor pattern in which an Au film is laminated is formed. For example, a conductor pattern in which a Ta 2 N film, a Ni—Cu film, and an Au film are laminated is formed on an alumina ceramic substrate, and a Ni film and a thin Au film are laminated at least on a soldering portion on the surface of the conductor pattern. A second conductor pattern is formed. Further, a preliminary solder layer may be formed on the surface of the tin soldering portion of the Au film of the second conductor pattern.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の回路基板の一実施例の断面図であ
る。アルミナセラミック基板1の表面にはTa2 N膜2
1、Ni−Cr膜22、Au膜23が順次形成され、か
つこの積層膜をフォトリソグラフィ技術等により所要の
パターンに形成することで導体パターン2を形成する。
ここで、前記Ta2 N膜21は1000Å、Ni−Cr
膜22は2000Å、Au膜23は4〜7μmの膜厚に
形成する。また、ここではアルミナセラミック基板1の
裏面には、Ni−Cr膜22とAu膜23を積層し、導
体パターン2が接地用導体パターンとして形成される。
この裏面側の各膜は表面側の対応する膜と同時に形成さ
れており、したがってそれぞれの膜厚は表面の膜厚と同
じである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the circuit board of the present invention. Ta 2 N film 2 is formed on the surface of alumina ceramic substrate 1.
1, the Ni—Cr film 22 and the Au film 23 are sequentially formed, and the conductor pattern 2 is formed by forming the laminated film into a desired pattern by a photolithography technique or the like.
Here, the Ta 2 N film 21 is 1000 Å, Ni-Cr
The film 22 is formed to a thickness of 2000 Å, and the Au film 23 is formed to a thickness of 4 to 7 μm. Further, here, the Ni-Cr film 22 and the Au film 23 are laminated on the back surface of the alumina ceramic substrate 1 to form the conductor pattern 2 as a grounding conductor pattern.
Each film on the back surface side is formed at the same time as the corresponding film on the front surface side, so that the film thickness of each film is the same as the film thickness on the surface.

【0006】そして、少なくとも前記導体パターン2の
電子部品を搭載する箇所、即ち電子部品の電極を半田に
より接合する部分のAu膜23の上には、Ni膜31及
びAu膜32を重ねて形成した第2導体パターン3を形
成する。Ni膜31は2.5〜5μmの膜厚に形成し、A
u膜32は0.1〜0.3μmと極めて薄く形成する。この
Ni膜31は導体パターン2の最上層のAu膜23及び
自身の上層のAu膜32との接着性が良い一方、錫半田
とは金属間化合物を形成することはない。なお、この実
施例ではアルミナセラミック基板1の裏面においては、
導体パターン2の全面に第2導体パターン3を形成して
いる。
Then, a Ni film 31 and an Au film 32 are formed so as to overlap each other on at least a portion of the conductor pattern 2 where the electronic component is mounted, that is, a portion where the electrode of the electronic component is joined by soldering. The second conductor pattern 3 is formed. The Ni film 31 is formed to have a film thickness of 2.5 to 5 μm.
The u film 32 is formed to a very thin thickness of 0.1 to 0.3 μm. The Ni film 31 has good adhesiveness to the uppermost Au film 23 of the conductor pattern 2 and the Au film 32 of the upper layer of itself, but does not form an intermetallic compound with tin solder. In this embodiment, on the back surface of the alumina ceramic substrate 1,
The second conductor pattern 3 is formed on the entire surface of the conductor pattern 2.

【0007】このような構成のアルミナセラミック回路
基板に、チップ状の電子部品を搭載した例を図2に示
す。同図のように、第2導体パターン3上にチップ状の
電子部品4を搭載し、その電極を錫半田、即ちSn63
共晶半田5により第2導体パターン3のAu膜32に接
続する。このとき、半田5はAu膜32とでAu−Sn
系金属間化合物6を生成するが、Au膜32が極めて薄
く形成されているために、この金属間化合物6の生成は
極僅かな膜厚内に制限される。また、Au膜32の下側
にはSnとは金属間化合物を生成しないNi膜31が形
成されているため、このNi膜31がバリヤとなってA
u−Sn系金属間化合物6がNi膜31及びその下側の
導体パターン2のAu膜23にまで拡大されることはな
い。これにより、電子部品4はSn63共晶半田5によ
りAu膜32及びNi膜31に接合される一方、導体パ
ターン2のAu膜23に金属間化合物が生成されること
がないため、Ni膜31はその下面において導体パター
ン2に一体化された結合状態が確保され、結果として電
子部品4の部品接合強度の劣化、及び信頼性の低下が生
じることはない。
FIG. 2 shows an example in which chip-shaped electronic components are mounted on the alumina ceramic circuit board having such a structure. As shown in the figure, a chip-shaped electronic component 4 is mounted on the second conductor pattern 3, and its electrode is tin solder, that is, Sn63.
The eutectic solder 5 connects to the Au film 32 of the second conductor pattern 3. At this time, the solder 5 forms Au-Sn together with the Au film 32.
Although the intermetallic compound 6 is generated, since the Au film 32 is formed extremely thin, the generation of the intermetallic compound 6 is limited to an extremely small film thickness. Further, since the Ni film 31 that does not form an intermetallic compound with Sn is formed below the Au film 32, this Ni film 31 serves as a barrier.
The u-Sn intermetallic compound 6 does not extend to the Ni film 31 and the Au film 23 of the conductor pattern 2 below the Ni film 31. As a result, the electronic component 4 is bonded to the Au film 32 and the Ni film 31 by the Sn63 eutectic solder 5, while the intermetallic compound is not generated in the Au film 23 of the conductor pattern 2, so that the Ni film 31 is not formed. On the lower surface thereof, a combined state integrated with the conductor pattern 2 is secured, and as a result, deterioration of the component bonding strength of the electronic component 4 and deterioration of reliability do not occur.

【0008】ここで、前記実施例では導体パターン2が
Ta2 N膜、Ni−Cr膜、Au膜で構成された例を示
しているが、最上層にAu膜が形成されている導体パタ
ーンであれば、下側のTa2 N膜とNi−Cr膜は他の
金属で形成されていてもよい。また、前記した各膜の膜
厚寸法は一例を示してものであり、半田付けする部品の
寸法や使用する半田の種類に応じて適宜変更することは
可能である。但し、第2導体パターン3のAu膜32の
膜厚は半田付けに支障が生じない範囲で可及的に薄く形
成することが好ましい。
Here, in the above-described embodiment, the conductor pattern 2 is an example in which it is composed of a Ta 2 N film, a Ni—Cr film, and an Au film, but it is a conductor pattern in which an Au film is formed on the uppermost layer. If so, the lower Ta 2 N film and the Ni—Cr film may be formed of other metals. Further, the film thickness dimension of each film described above is merely an example, and can be appropriately changed according to the dimension of the component to be soldered and the type of solder used. However, it is preferable that the Au film 32 of the second conductor pattern 3 is formed as thin as possible within a range that does not hinder soldering.

【0009】また、第2導体パターン3のAu膜32と
半田との金属間化合物を抑制するために、Au膜32の
表面に予備半田層を形成しておいてもよい。この予備半
田層を形成しておけば、電子部品を半田付けする際に、
予備半田と部品接続用半田とが直ちに濡れて接続が行わ
れるため、Auが半田に拡散されることが抑制され、A
u膜との間でAu−Sn系金属間化合物を生成すること
が抑制される。なお、本発明はアルミナセラミック基板
以外の絶縁基板に導体パターンを形成する回路基板にお
いても同様に適用することが可能である。
In order to suppress the intermetallic compound between the Au film 32 of the second conductor pattern 3 and the solder, a preliminary solder layer may be formed on the surface of the Au film 32. If this preliminary solder layer is formed, when soldering electronic components,
Since the preliminary solder and the component connecting solder are immediately wet and are connected, Au is suppressed from diffusing into the solder.
Generation of an Au—Sn intermetallic compound with the u film is suppressed. The present invention can be similarly applied to a circuit board in which a conductor pattern is formed on an insulating substrate other than the alumina ceramic substrate.

【0010】[0010]

【発明の効果】以上説明したように本発明は、絶縁基板
に形成した導体パターンのAu膜上に、Ni膜と薄いA
u膜とを積層した第2導体パターンを形成しているの
で、薄いAu膜に半田付けを行った際にAu−Sn系金
属間化合物が生成されたとしても、Au膜が極めて薄い
ためにこの金属間化合物の生成は僅かであり、かつこの
金属間化合物がNi膜によって下側の導体パターンのA
u膜にまで到達されることがなく、半田付け部分の強度
劣化防止や信頼性の向上を図ることができる。また、第
2導体パターンのAu膜の錫半田付け部の表面に予備半
田層を形成することで、半田と予備半田とが直ちに濡
れ、Auが半田に拡散されることが抑制され、金属間化
合物が生成されることが防止される。
As described above, according to the present invention, the Ni film and the thin A film are formed on the Au film of the conductor pattern formed on the insulating substrate.
Since the second conductor pattern is formed by laminating the u film, even if an Au-Sn intermetallic compound is generated when soldering is performed on the thin Au film, the Au film is extremely thin and The formation of the intermetallic compound was slight, and this intermetallic compound was formed on the lower conductive pattern A by the Ni film.
It is possible to prevent the strength deterioration of the soldered portion and improve the reliability without reaching the u film. Further, by forming the preliminary solder layer on the surface of the tin soldering portion of the Au film of the second conductor pattern, it is possible to prevent the solder and the preliminary solder from immediately getting wet and Au from diffusing into the solder. Are prevented from being generated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の絶縁回路基板の一実施例の断面図であ
る。
FIG. 1 is a cross-sectional view of an example of an insulated circuit board of the present invention.

【図2】本発明の絶縁回路基板に部品を搭載して半田付
けした状態の断面図である。
FIG. 2 is a cross-sectional view of a state in which components are mounted on the insulated circuit board of the present invention and soldered.

【図3】従来の絶縁回路基板に部品を半田付けした状態
の断面図である。
FIG. 3 is a cross-sectional view of a state in which components are soldered to a conventional insulated circuit board.

【符号の説明】[Explanation of symbols]

1 アルミナセラミック基板 2 導体パターン 21 Ta2 N膜,22 Ni−Cr膜, 23 Au
膜 3 第2導体パターン 31 Ni膜, 32 薄いAu膜 4 電子部品 5 Sn63共晶半田 6 Au−Sn系金属間化合物
DESCRIPTION OF SYMBOLS 1 Alumina ceramic substrate 2 Conductor pattern 21 Ta 2 N film, 22 Ni—Cr film, 23 Au
Film 3 Second conductor pattern 31 Ni film, 32 Thin Au film 4 Electronic component 5 Sn63 Eutectic solder 6 Au-Sn based intermetallic compound

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板に導体パターンを形成し、この
導体パターンの上層がAu膜で構成されてなる絶縁回路
基板において、少なくとも前記導体パターンの錫半田付
け部の表面にNi膜と薄いAu膜とを積層した第2導体
パターンを形成したことを特徴とする絶縁回路基板。
1. An insulated circuit board comprising a conductor pattern formed on an insulating substrate, and an upper layer of the conductor pattern comprising an Au film, wherein a Ni film and a thin Au film are formed on at least a surface of a tin soldering portion of the conductor pattern. An insulated circuit board, characterized in that a second conductor pattern is formed by laminating and.
【請求項2】 アルミナセラミック基板上に、Ta2
膜、Ni−Cu膜、Au膜を積層した導体パターンを形
成し、少なくとも前記導体パターンの表面の錫半田付け
部にNi膜と薄いAu膜とを積層した第2導体パターン
を形成してなる請求項1の絶縁回路基板。
2. Ta 2 N on an alumina ceramic substrate
A conductive pattern is formed by stacking a film, a Ni-Cu film, and an Au film, and a second conductive pattern is formed by stacking a Ni film and a thin Au film on at least a tin soldering portion on the surface of the conductive pattern. Item 1. The insulated circuit board of item 1.
【請求項3】 第2導体パターンのAu膜の錫半田付け
部の表面に予備半田層を形成してなる請求項1または2
の絶縁回路基板。
3. A preliminary solder layer is formed on the surface of the tin soldering portion of the Au film of the second conductor pattern.
Isolated circuit board.
JP9041093A 1993-03-26 1993-03-26 Insulating circuit board Pending JPH06283844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9041093A JPH06283844A (en) 1993-03-26 1993-03-26 Insulating circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9041093A JPH06283844A (en) 1993-03-26 1993-03-26 Insulating circuit board

Publications (1)

Publication Number Publication Date
JPH06283844A true JPH06283844A (en) 1994-10-07

Family

ID=13997821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9041093A Pending JPH06283844A (en) 1993-03-26 1993-03-26 Insulating circuit board

Country Status (1)

Country Link
JP (1) JPH06283844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7902681B2 (en) 2005-08-22 2011-03-08 Rohm Co., Ltd. Semiconductor device, production method for the same, and substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850421A (en) * 1981-09-22 1983-03-24 Tokico Ltd Manufacture of rotary body for flowmeter
JPH03291991A (en) * 1990-04-09 1991-12-24 Fujitsu Ltd Forming method for pad
JPH04101488A (en) * 1990-08-20 1992-04-02 Kyocera Corp Thin film wiring substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
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JPS5850421A (en) * 1981-09-22 1983-03-24 Tokico Ltd Manufacture of rotary body for flowmeter
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7902681B2 (en) 2005-08-22 2011-03-08 Rohm Co., Ltd. Semiconductor device, production method for the same, and substrate
US8368234B2 (en) 2005-08-22 2013-02-05 Rohm Co., Ltd. Semiconductor device, production method for the same, and substrate

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