JPH03291991A - Forming method for pad - Google Patents
Forming method for padInfo
- Publication number
- JPH03291991A JPH03291991A JP9352990A JP9352990A JPH03291991A JP H03291991 A JPH03291991 A JP H03291991A JP 9352990 A JP9352990 A JP 9352990A JP 9352990 A JP9352990 A JP 9352990A JP H03291991 A JPH03291991 A JP H03291991A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- thin film
- conductive layer
- solder
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 34
- 229910000679 solder Inorganic materials 0.000 claims abstract description 30
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052737 gold Inorganic materials 0.000 claims abstract description 7
- 239000010931 gold Substances 0.000 claims abstract description 7
- 238000010030 laminating Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000011651 chromium Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000015096 spirit Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半田の溶着が行われる導電材より成るパッドの形成方法
に関し、
パッドが半田によって溶食されることを防ぐことを目的
とし。[Detailed Description of the Invention] [Summary] The present invention relates to a method of forming a pad made of a conductive material to which solder is welded, and the object is to prevent the pad from being eroded by the solder.
基板の上面に所定の厚みで形成された導電層と、該導電
層の側面が露出されることのないよう該導電層の全体を
覆うように積層されるニッケルメッキによる第１の薄膜
と、該第１の薄膜の上層に、更に積層される金メッキに
よる第２のｆＨＩｌとによってパッドを形成し、溶着す
べき半田が該第２の薄膜の上層に形成されるように構成
する。a conductive layer formed to a predetermined thickness on the upper surface of the substrate; a first thin film made of nickel plating laminated to cover the entire conductive layer so that the side surfaces of the conductive layer are not exposed; A pad is formed on the upper layer of the first thin film by a second fHIl layered with gold, and the solder to be welded is formed on the upper layer of the second thin film.
本発明は半田の溶着が行われる導電材より成るパッドの
形成方法に関する。The present invention relates to a method of forming a pad made of a conductive material to which solder is welded.
電子機器に用いられるプリント基板では、実装される半
導体素子などの電子部品は、−船釣に、電子部品のリー
ド端子をパッドに半田付けすることで行われる。On printed circuit boards used in electronic devices, electronic components such as semiconductor elements are mounted on a boat by soldering lead terminals of the electronic components to pads.
このように電子部品がパッドに半田付けされることで電
気信号の入出力が行われる。By soldering electronic components to pads in this manner, electrical signals are input and output.
したがって、このような半田付けは、電気信号の入出力
に際して、電気特性に影響することのないよう信頼性の
高いことが望まれる。Therefore, such soldering is desired to be highly reliable so as not to affect the electrical characteristics when inputting and outputting electrical signals.
従来は第４図の従来の説明図に示すように構成されてい
た。第４図の（ａ）は側面図、 （ｂ） （ｃ）はパタ
ーンの要部拡大図である。Conventionally, the configuration was as shown in the conventional explanatory diagram of FIG. 4. FIG. 4(a) is a side view, and FIGS. 4(b) and 4(c) are enlarged views of essential parts of the pattern.
第４図の（ａ）に示すように、基板１の上面に配設され
たパッド１１に電子部品１０のリード端子１０Ａを位置
決めし、鉛錫合金Ｐｂ−５ｎまたはインジウム錫合金Ｉ
ｎ−５ｎから戒る半田５を溶融させることでリード端子
１０＾をパッド１１に固着することが行われている。As shown in FIG. 4(a), the lead terminals 10A of the electronic component 10 are positioned on the pads 11 provided on the upper surface of the substrate 1, and
Lead terminals 10^ are fixed to pads 11 by melting solder 5 starting from n-5n.
このパッド１１は、（ｂ）に示すように、クロームＣｒ
およびチタンＴｉをスパッタによって形威した金属層１
１Ｃに銅Ｃｕによる導電層１１Ｂを積層し、導電層１１
Ｂの上層には半田５の濡れ性を良くするためのニッケル
Ｎｉによるニッケルメッキ層１１Ａが施されることで形
威されている。As shown in (b), this pad 11 is made of chrome Cr.
Metal layer 1 formed by sputtering and titanium Ti
A conductive layer 11B made of copper Cu is laminated on the conductive layer 11C.
A nickel plating layer 11A made of nickel Ni is applied to the upper layer B to improve the wettability of the solder 5.
したがって、リード端子１０Ａをパッド１１にボンディ
ングする場合、ニッケルメッキ層１１Ａによって半田５
が確実に溶着されるように配慮されていた。Therefore, when bonding the lead terminal 10A to the pad 11, the solder 5 is bonded to the nickel plating layer 11A.
Care was taken to ensure that the parts were welded securely.
このような金属層１１Ｃ１導電層１１Ｂ、およびニッケ
ルメッキ層１１Ａを積層することで形威されたパッドに
半田５を溶着した場合は、半田５によって溶解され、第
４図の（ｃ）に示すように、金属層１１Ｃを残した状態
で、導電層１１Ｂの銅ＣｕおよびニッケルＮｉが半田５
に溶は込み、パッド１１が痩せ細る問題を有していた。When solder 5 is welded to a pad formed by stacking the metal layer 11C, the conductive layer 11B, and the nickel plating layer 11A, the solder 5 melts and forms a layer as shown in FIG. 4(c). , the copper Cu and nickel Ni of the conductive layer 11B are bonded to the solder 5 with the metal layer 11C remaining.
There was a problem in that the pad 11 became thin due to melting.
尚、このような銅ＣｕおよびニッケルＮｉが半田５に溶
食されることは、パッド１１に溶着された半田５を所定
の日数を経過後、半田５をＣｕ−Ｘ線マツプおよびＮ１
−Ｘ線マツプによって撮影することで、銅Ｃｕおよびニ
ッケルＮｉが溶は込むことが確認されている。It should be noted that such copper Cu and nickel Ni are eroded into the solder 5. After a predetermined number of days have elapsed, the solder 5 is subjected to a Cu-X-ray map and an N1
- It has been confirmed that copper (Cu) and nickel (Ni) penetrate into the metal by taking an image using an X-ray map.
また、このＣｕ−Ｘ線マツプおよびＮ１−Ｘ線マツプに
よる溶は込み状態は、銅Ｃｕ粒子が密集することで分布
され、ニッケルＮｉは繊維状になっていることから、導
電層１１Ｂの側面１１０に於ける銅Ｃｕの溶食によって
ニッケルメッキ層１１ＡのニッケルＮｉが半田５に取り
込まれることになると推察される。In addition, the melt penetration state according to the Cu-X-ray map and the N1-X-ray map is that the copper Cu particles are distributed densely and the nickel Ni is in the form of fibers, so the side surface 110 of the conductive layer 11B It is presumed that the nickel Ni of the nickel plating layer 11A is incorporated into the solder 5 due to corrosion of the copper Cu during the process.
そこで、本発明では、パッドが半田によって溶食される
ことを防ぐことを目的とする。Therefore, an object of the present invention is to prevent the pad from being eroded by solder.
（課題を解決するための手段〕 第１図は本発明の原理説明図である。(Means for solving problems) FIG. 1 is a diagram explaining the principle of the present invention.
第１図に示すように、基板１の上面１Ａに所定の厚みｔ
で形威された導電層２と、該導電層２の側面２Ａが露出
されることのないよう該導電層２の全体を覆うように積
層されるニッケルメッキによる第１の薄膜３と、該第１
の薄ＩＩ３の上層に、更に積層される金メッキによる第
２のＩｍ！４とによってパッド６を形威し、溶着すべき
半田５が該第２の薄膜４の上層に形威されるように構成
する。As shown in FIG. 1, a predetermined thickness t is applied to the upper surface 1A of the substrate 1.
A first thin film 3 made of nickel plating is laminated to cover the entire conductive layer 2 so that the side surface 2A of the conductive layer 2 is not exposed. 1
A second Im! plated with gold is further laminated on top of the thin II3 layer. 4 forms a pad 6, and the solder 5 to be welded is formed on the upper layer of the second thin film 4.
このように構成することによって前述の課題は解決され
る。With this configuration, the above-mentioned problem is solved.
即ち、基板１の表面１Ａに形威された導電Ｎ２の側面２
Ａが露出されないように導電層２の全体をニッケルメッ
キによる第１の薄膜３と、金メッキによる第２の薄膜４
と積層することでパッド６を形威し、半田５の溶着を第
２の薄ｌｌＩ４の上層に行うようにしたものである。That is, the side surface 2 of the conductive N2 formed on the surface 1A of the substrate 1
The entire conductive layer 2 is covered with a first thin film 3 made of nickel plating and a second thin film 4 made of gold plating so that A is not exposed.
The pad 6 is formed by laminating the two layers, and the solder 5 is welded to the upper layer of the second thin layer 4.
そこで、半田５の溶着が第２の薄膜４に行われることに
なるため、第１と第２の薄膜３．４がバリヤとなり、パ
ッド６の溶食が避けられる。Therefore, since the solder 5 is welded to the second thin film 4, the first and second thin films 3.4 act as a barrier, and corrosion of the pad 6 is avoided.
したがって、従来のようにパッドが痩せ細ることがなく
なり、安定したパッドを形成することができ、信頼性の
向上が図れる。Therefore, unlike the conventional pad, the pad does not become thinner and thinner, and a stable pad can be formed, thereby improving reliability.
以下本発明を第２図および第３図を参考に詳細に説明す
る。第２図は本発明による一実施例の斜視図、第３図の
（ａ） 〜（ｈ） 、 （ｃｌ） （ｅｌ） （ｈｌ）
は本発明の製造工程図である。全図を通じて、同一符号
は同一対象物を示す。The present invention will be explained in detail below with reference to FIGS. 2 and 3. Fig. 2 is a perspective view of one embodiment of the present invention, and Fig. 3 (a) to (h), (cl) (el) (hl)
1 is a manufacturing process diagram of the present invention. The same reference numerals indicate the same objects throughout the figures.
第２図に示すように、基板１の表面１Ａに所定の形状に
よって形威された厚みｔの導電層２を覆うように第１の
薄膜３を積層し、更に、第１の１膜３を覆うように第２
の薄膜４の積層を行うことでパッド６が形威されるよう
にしたものである。As shown in FIG. 2, a first thin film 3 is laminated on the surface 1A of the substrate 1 so as to cover the conductive layer 2 having a thickness t defined by a predetermined shape, and a first thin film 3 is further deposited on the surface 1A of the substrate 1 so as to cover the conductive layer 2 having a thickness t. second to cover
The pad 6 is shaped by laminating the thin films 4.
そこで、パッド６に溶着される半田５の固着は第２の薄
膜４の上層４＾に行われるようにし、導電層２が直接半
田５に接触することのないようにしたものである。Therefore, the solder 5 welded to the pad 6 is fixed to the upper layer 4^ of the second thin film 4, so that the conductive layer 2 does not come into direct contact with the solder 5.
この場合、導電層２の側面２Ａも第１の薄膜３と第２の
薄膜４とによって覆われ、側面２Ａが露出されないよう
にすることが重要である。In this case, it is important that the side surface 2A of the conductive layer 2 is also covered with the first thin film 3 and the second thin film 4 so that the side surface 2A is not exposed.
したがって、半田５の溶着に際して、半田５が流れ出て
も、導電層２に半田５に接触すことがなく、前述のよう
な導電層２が溶食されることを防ぐことができる。Therefore, even if the solder 5 flows out during welding of the solder 5, the solder 5 does not come into contact with the conductive layer 2, and the conductive layer 2 can be prevented from being eroded as described above.
また、このような構成は、第３図の製造工程図によって
形成することができる。Moreover, such a structure can be formed according to the manufacturing process diagram of FIG. 3.
第３図の（ａ）に示すように、基板１の上面１Ａにクロ
ームＣｒおよびチタンＴｉをスパッタによって形威した
金属層に電気メッキにより銅Ｃｏを積層することで厚み
ｔの導電層２の形威を行い、形威された導電層２には（
ｂ）に示すように、感光レジスト７の積層を行い、エツ
チングによって所定個所の感光レジスト７および導電層
２を除去し、（ｃ）に示す溝８を形成する。この溝８は
（ｃｌ）に示すように、正方形に形威された場合は、一
つのコーナ部が切れ、導電層２が繋がるように形成する
。As shown in FIG. 3(a), a conductive layer 2 having a thickness of t is formed by laminating copper Co by electroplating on a metal layer formed by sputtering chromium Cr and titanium Ti on the upper surface 1A of the substrate 1. The shaped conductive layer 2 has (
As shown in (b), a photosensitive resist 7 is laminated, and predetermined portions of the photosensitive resist 7 and conductive layer 2 are removed by etching to form grooves 8 as shown in (c). As shown in (cl), when the groove 8 is square, it is formed so that one corner is cut and the conductive layer 2 is connected.
このような溝８を形成後は、（ｄ）に示すように感光レ
ジスト７の除去を行う。After forming such grooves 8, the photoresist 7 is removed as shown in (d).
次に、（ｅ）に示すように、溝８によって囲まれたＡ部
の個所を除いて、感光レジスト７の積層を行う。この場
合、（ｅｌ）に示すように、感光レジスト７の積層は溝
８の幅のほぼ中間まで達するように行う、したがって、
導電層２が繋がった個所では、Ｂ部に示す感光レジスト
７の積層はテーバ状の端面となる。Next, as shown in (e), a photoresist 7 is laminated except for the portion A surrounded by the groove 8. In this case, as shown in (el), the photoresist 7 is laminated so as to reach approximately the middle of the width of the groove 8.
At the locations where the conductive layers 2 are connected, the laminated layer of the photosensitive resist 7 shown in section B becomes a tapered end surface.
このようにして露出されたＡ部に対しては、導電層２を
電極として電気メッキを施し、（ｆ）に示すように、ニ
ッケルＮｉによる第１の薄Ｉｎ！３の積層を行い、第１
の薄膜３の積層された上層には同様に導電層２を電極と
して、更に、（ｇ）に示すように、電気メッキを施し、
金Ａｇによる第２の薄膜４の積層を行う。The thus exposed portion A is electroplated using the conductive layer 2 as an electrode, and as shown in (f), a first thin In! 3 stacking is performed, and the first
Similarly, the upper layer of the laminated thin film 3 is electroplated using the conductive layer 2 as an electrode, as shown in (g),
A second thin film 4 of gold Ag is laminated.
この場合は、導電層２の側面２Ａにも第１と第２のＩＦ
５．４がそれぞれ積層されことにり、また、メッキは、
無電解メッキによることでも可能であるが、膜厚の管理
、および粒子の密度を考慮すると電気メッキの方が良い
。In this case, the first and second IFs are also connected to the side surface 2A of the conductive layer 2.
5.4 are laminated, and the plating is
Electroless plating is also possible, but electroplating is better in terms of film thickness control and particle density.
最後に、エツチングにより、（ｈ）に示すように、感光
レジスト７および第２の薄膜４の積層が行われた個所以
外の導電層２を除去する。この除去によって（ｈｌ）に
示す形状のパッド６の形威が行われる。Finally, by etching, as shown in (h), the conductive layer 2 is removed in areas other than those where the photosensitive resist 7 and the second thin film 4 are laminated. By this removal, a pad 6 having the shape shown in (hl) is formed.
このようにしてパッド６を構成すると、導電層２の銅Ｃ
ｕがパッド６の外周に露出される個所は、コーナ部のＢ
部に示す端面の個所だけとなり、その他は全て第１と第
２のは薄膜３．４によって覆われることになり、半田５
の溶着が行われても、第１と第２の薄膜３，４がバリヤ
となり、銅Ｃｕが半田５に溶は込むことが防げる。When the pad 6 is configured in this way, the copper C of the conductive layer 2
The location where u is exposed on the outer periphery of the pad 6 is at the corner B.
Only the end face shown in Figure 3 is covered, and all other parts are covered with the first and second thin films 3.4, and solder 5.
Even if welding is performed, the first and second thin films 3 and 4 act as a barrier, and the copper Cu can be prevented from melting into the solder 5.
尚、第２の薄膜は本発明では、金メッキによって形威す
ることで説明したが、白金ｐｔを用いることでも同様の
効果が得られる。In the present invention, the second thin film is formed by gold plating, but the same effect can be obtained by using platinum PT.
以上説明したように、本発明によれば、基板の上面に形
威された導電層に、電気メッキによって第１と第２の薄
膜を積層することでパッドを形威し、導電層の全体を第
１と第２の薄膜によって覆うことで、導電層が半田によ
って溶食されることのないようにすることができる。As explained above, according to the present invention, the pad is formed by laminating the first and second thin films by electroplating on the conductive layer formed on the upper surface of the substrate, and the entire conductive layer is formed. By covering with the first and second thin films, the conductive layer can be prevented from being eroded by the solder.
したがって、従来のよなパッドが痩せ細ることがなくな
り、パッドに入出力される電気信号に悪影響を及ぼすこ
とが防げることになり、信頼性の向上が図れ、実用的効
果は大である。Therefore, the pad does not become thin like in the past, and it is possible to prevent an adverse effect on the electrical signals input and output from the pad, thereby improving reliability and having a great practical effect.
第１図は本発明の原理説明図。
第２図は本発明による一実施例の斜視図。
第３図の（ａ） 〜（ｈ） 、 （ｃｌ） （ｅｌ）
（ｈｌ）は本発明の製造工程図。
第４図は従来の説明図で、（ａ）は側面図、 （ｂ）
（ｃ）はパターンの要部拡大図を示す。
図において、
ｌは基板、 ２は導電層。
３は第１の薄膜、 ４は第２の薄膜。
５は半田、 ６はパッド。
１Ａは上面、 ２Ａは側面を示す。
本発明による一大施例の糾規図
第 ２ 図
本発明の原理現明図
夷 １ 図
木発Ｕ月のＭ遣−Ｔ−程図
算３図（℃の１）
３第１の薄膜
本発明
のｌ直工程回
亮３苗（での２）
従来
の
説
明
凶
夷
図FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a perspective view of an embodiment according to the present invention. (a) to (h), (cl) (el) in Figure 3
(hl) is a manufacturing process diagram of the present invention. Figure 4 is a conventional explanatory diagram, (a) is a side view, (b)
(c) shows an enlarged view of the main part of the pattern. In the figure, l is the substrate and 2 is the conductive layer. 3 is the first thin film, 4 is the second thin film. 5 is solder, 6 is pad. 1A shows the top surface, 2A shows the side surface. Figure 2: Principle diagram of the present invention Figure 1: Figure 3: Diagram of the M-T-mode of the U month from the tree (1 of ℃) 3: First thin film book Invention's direct process rotation 3 seedlings (2) Conventional explanation of evil spirits
Claims (1)
れた導電層（２）と、該導電層（２）の側面（２Ａ）が
露出されることのないよう該導電層（２）の全体を覆う
ように積層されるニッケルメッキによる第１の薄膜（３
）と、該第１の薄膜（３）の上層に、更に積層される金
メッキによる第２の薄膜（４）とによってパッド（６）
を形成し、溶着すべき半田（５）が該第２の薄膜（４）
の上層に形成されることを特徴とするパッドの形成方法
。A conductive layer (2) is formed on the upper surface (1A) of the substrate (1) to a predetermined thickness (t), and the conductive layer (2) is formed so that the side surface (2A) of the conductive layer (2) is not exposed. The first thin film (3) made of nickel plating is laminated so as to cover the entire part (2).
) and a second thin film (4) formed by gold plating, which is further laminated on top of the first thin film (3), thereby forming a pad (6).
The solder (5) to be welded is the second thin film (4).
A method for forming a pad, characterized in that it is formed on an upper layer of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2093529A JP2762672B2 (en) | 1990-04-09 | 1990-04-09 | Solder connection pad and method of forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2093529A JP2762672B2 (en) | 1990-04-09 | 1990-04-09 | Solder connection pad and method of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03291991A true JPH03291991A (en) | 1991-12-24 |
| JP2762672B2 JP2762672B2 (en) | 1998-06-04 |
Family
ID=14084836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2093529A Expired - Lifetime JP2762672B2 (en) | 1990-04-09 | 1990-04-09 | Solder connection pad and method of forming the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762672B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575246A (en) * | 1990-09-12 | 1993-03-26 | Macdermid Inc | Printed-circuit forming method |
| JPH06283844A (en) * | 1993-03-26 | 1994-10-07 | Nec Corp | Insulating circuit board |
| WO1998056217A1 (en) * | 1997-06-04 | 1998-12-10 | Ibiden Co., Ltd. | Soldering member for printed wiring boards |
| FR2799337A1 (en) * | 1999-10-05 | 2001-04-06 | St Microelectronics Sa | METHOD FOR MAKING ELECTRICAL CONNECTIONS ON THE SURFACE OF A SEMICONDUCTOR PACKAGE WITH ELECTRICAL CONNECTION DROPS |
| EP1080823A3 (en) * | 1999-09-03 | 2004-01-21 | Nec Corporation | High-strength solder joint |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62232189A (en) * | 1986-04-01 | 1987-10-12 | 日本電気株式会社 | Protruded terminal structure of wiring board |
| JPS63288795A (en) * | 1987-05-21 | 1988-11-25 | 日本電気株式会社 | Manufacture of ic card |
| JPH02185094A (en) * | 1989-01-12 | 1990-07-19 | Hitachi Chem Co Ltd | Manufacture of wiring board for pin grid array package |
-
1990
- 1990-04-09 JP JP2093529A patent/JP2762672B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62232189A (en) * | 1986-04-01 | 1987-10-12 | 日本電気株式会社 | Protruded terminal structure of wiring board |
| JPS63288795A (en) * | 1987-05-21 | 1988-11-25 | 日本電気株式会社 | Manufacture of ic card |
| JPH02185094A (en) * | 1989-01-12 | 1990-07-19 | Hitachi Chem Co Ltd | Manufacture of wiring board for pin grid array package |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575246A (en) * | 1990-09-12 | 1993-03-26 | Macdermid Inc | Printed-circuit forming method |
| JPH06283844A (en) * | 1993-03-26 | 1994-10-07 | Nec Corp | Insulating circuit board |
| WO1998056217A1 (en) * | 1997-06-04 | 1998-12-10 | Ibiden Co., Ltd. | Soldering member for printed wiring boards |
| US6358630B1 (en) | 1997-06-04 | 2002-03-19 | Ibiden Co., Ltd. | Soldering member for printed wiring boards |
| EP1080823A3 (en) * | 1999-09-03 | 2004-01-21 | Nec Corporation | High-strength solder joint |
| US6919137B2 (en) | 1999-09-03 | 2005-07-19 | Nec Corporation | High-strength solder joint |
| FR2799337A1 (en) * | 1999-10-05 | 2001-04-06 | St Microelectronics Sa | METHOD FOR MAKING ELECTRICAL CONNECTIONS ON THE SURFACE OF A SEMICONDUCTOR PACKAGE WITH ELECTRICAL CONNECTION DROPS |
| EP1091627A1 (en) * | 1999-10-05 | 2001-04-11 | STMicroelectronics SA | Process for providing electrical connections on the surface of a semiconductor package using electrical connection bumps |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2762672B2 (en) | 1998-06-04 |
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