JPS60198761A - Soldering method - Google Patents

Soldering method

Info

Publication number
JPS60198761A
JPS60198761A JP5491084A JP5491084A JPS60198761A JP S60198761 A JPS60198761 A JP S60198761A JP 5491084 A JP5491084 A JP 5491084A JP 5491084 A JP5491084 A JP 5491084A JP S60198761 A JPS60198761 A JP S60198761A
Authority
JP
Japan
Prior art keywords
gold
layer
ceramic substrate
brazing
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5491084A
Other languages
Japanese (ja)
Other versions
JPH0227817B2 (en
Inventor
Yuzo Shimada
嶋田 勇三
Kazuaki Uchiumi
和明 内海
Masanori Suzuki
正則 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5491084A priority Critical patent/JPS60198761A/en
Publication of JPS60198761A publication Critical patent/JPS60198761A/en
Publication of JPH0227817B2 publication Critical patent/JPH0227817B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Abstract

PURPOSE:To unnecessitate metallic films for barrier by enabling soldering treatment at low temperatures in a neutral atmosphere by a method wherein a titanium film is formed at the part of soldering on a ceramic substrate. CONSTITUTION:A mask 32 made of a metallic thin plate and having an aperture at the part of soldering is superposed on the surface of a multilayer ceramic substrate 31, and a titanium film 33 is formed from above by sputtering. Next, a layer 34 of palladium a metal of the group VIII in the periodic law table is formed thereon by sputtering; thereafter, the mask 32 is removed. An alloy solder 35 having a weight ratio of Au 80% and Sn 20% is placed on the palladium layer 34, and an input-output electrical connection pin 36 coated with an Au coat layer 37 by plating and the like is heat-treated for 10-30min at a temperature of 300-450 deg.C.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、パッケージ基板における入出力電気接続ピン
を接着する方法に係ル、更に具体的にいえば多層セラミ
ック基板の接続ピンを基板に結合させるための接合手段
に係るO (従来技術) 最近の=ンピュータシステム等の高密度小屋化、高速化
および高パフォーマンス化に対して実装レベルにおける
パッケージ基板の要求はますますきびしいものになって
きている。具体的にはパッケージ基板において配線密度
を高め信号線幅を微細化すること、信号線導体の抵抗値
を下げること、絶縁材料の誘電率を下げること等が要求
されておシ、これに応えるようなパッケージ基板技術が
開発されてきた。例えばアルミナグリーンシートを用い
た多層セラミック基板ガラスセラミックグリーンシート
を用い900℃程度で焼結出来、金および銀−パラジウ
ム系導体が使える低温焼結多層セラミック基板、またセ
ラミック基板上ヘスバッタ蒸着等の薄膜技術を用いたパ
ッケージ基板、更に拡有機絶縁材料(ポリイミド等)を
用い薄膜導体と組み合せたパッケージ基板等々がある0
このよl高密度化、微細化された実装基板上へは、超L
8Iチ、プが多数実装されることKなシ、シたかって、
基板外部と電気的に接続するた恰の入出力端子数は極め
て多くなってくる0そのため入出力端子を多層基板裏面
にピンで形成する技術が開発されている〇 この多層セラ5ツク基板に接続ビンを取シ付ける従来技
術としては、例えばアルミナ多層基板において銀ろうを
用いてコバール又は4・2アpイ等の材質の接続ビンを
取シ付けていた◎第1図は、従来方法を説明するための
図であ)、アルミナグリーンシートに形成したモリブデ
ン又はタングステン等の導体パッド゛およびスルーホー
ル中の導体を1500℃以上の温度で還元雰囲気中で焼
結したのちのセラミック基板lおよびモリブデン又はタ
ングステン等の導体2が示されている口この導体パッド
部分にメッキによルニッケル層3を形成し、次に、コパ
ール又は4会2ア四イの接続ビン5を銀ろう4により取
シ付けている。銀ろうの組成は、一般にはAg 60亀
!チーCu 40 mol−の共晶合金が使われておシ
融点状779℃であシ、ろう付は処理温度は810℃程
度であシ、モリブデン等の導体の酸化を防ぐために水素
還元雰囲気中で行なわれる0次に基板に取シ付けられた
接続ビンおよび導体が劣化しないように金メッキ処理さ
れる0第2図には、金層6が形成された接続ビン付き基
板を示す0本方法はろう付は処理温度が高く、基板上に
形成した微細薄膜パターン等は、この温度に加熱するこ
とは難かしく、一方あらかじめピンを基板に取シ付けた
のち信号線等の微細薄膜パターンを形成する場合におい
ても、ピン付き基板上へ各種パターンを形成する際の精
度が悪くなり、作業性も低下する0また有機絶縁フィル
ム(ポリイミド等)を用いて多層セラミック基板上へパ
ターンを形成するパッケージ技術の場合でも同様である
。更にろう付は後接続ピンおよび導体パッド部を金メッ
キする工程が含まれ作業性が悪い。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for bonding input/output electrical connection pins on a package substrate, and more specifically, to a method for bonding connection pins of a multilayer ceramic substrate to the substrate. (Prior art) With the recent trend towards higher density, higher speed, and higher performance in computer systems, the requirements for package substrates at the mounting level are becoming increasingly strict. . Specifically, there are demands for increasing wiring density and miniaturizing signal line widths on package substrates, lowering the resistance value of signal line conductors, and lowering the dielectric constant of insulating materials. A new package substrate technology has been developed. For example, multilayer ceramic substrates using alumina green sheets, low-temperature sintered multilayer ceramic substrates that can be sintered at around 900°C using glass ceramic green sheets, and can use gold and silver-palladium conductors, and thin film techniques such as Hess Batter deposition on ceramic substrates. There are package substrates using organic insulating materials (polyimide, etc.) in combination with thin film conductors, etc.
Ultra-L
I hope that a large number of 8I chips will be implemented.
The number of input/output terminals that are electrically connected to the outside of the board is becoming extremely large. Therefore, a technology has been developed in which input/output terminals are formed with pins on the back of the multilayer board. * Connected to this multilayer ceramic 5-socket board. Conventional techniques for attaching bottles include, for example, attaching connecting bottles made of materials such as Kovar or 4.2-Api to an alumina multilayer board using silver solder. ◎Figure 1 explains the conventional method. (This is a diagram for the purpose of sintering the ceramic substrate l and molybdenum or tungsten conductor pads formed on the alumina green sheet and the conductors in the through holes at a temperature of 1500°C or higher in a reducing atmosphere.) A nickel layer 3 is formed by plating on the conductor pad portion of the opening where the conductor 2 such as tungsten is shown, and then a copper or 4-way 2-A-4 connection pin 5 is attached using silver solder 4. There is. The composition of silver solder is generally Ag 60! A eutectic alloy of 40 mol-Cu is used, with a melting point of 779°C, and the processing temperature for brazing is about 810°C, in a hydrogen reducing atmosphere to prevent oxidation of conductors such as molybdenum. Next, the connection pins and conductors attached to the board are gold plated to prevent deterioration. Figure 2 shows a board with connection pins on which a gold layer 6 has been formed. The processing temperature is high, and it is difficult to heat fine thin film patterns formed on a substrate to this temperature.On the other hand, when forming fine thin film patterns such as signal lines after attaching pins to the substrate in advance, Also, in the case of packaging technology that uses organic insulating films (polyimide, etc.) to form patterns on multilayer ceramic substrates, the accuracy when forming various patterns on pinned substrates deteriorates, and the workability also decreases. But it's the same. Furthermore, brazing involves a step of gold plating the connection pins and conductor pads, resulting in poor workability.

次に処理温度を低げるためにろう材としてAu−8n又
はAu−8i、 Au−8n−Pd) AAu−8n−
A等が検討された。具体的な一例を第3図および第4図
に示す。第3図においてはセラミック基板11の表面に
モリブデン層12を付着させ、該モリブデン層上にメッ
キ法等の手段により=ツクルの被膜13を形成する。′
次に該ニッケル被膜上に金ペーストによシ金の被膜14
を形成し熱処理によシ金・ニッケル固溶体を形成してい
る0続いて金メッキ17を施した接続ビン16をAu−
8nろう材15によシ結合している。この方法において
金・ニッケル固溶体を形成する際には約700℃の温度
で水素還元中で行なっている。また第4図においてはセ
ラミック基板21の表面にモリブデン層22を付着させ
、該モリブデン層上にニッケル被膜23を形成し、該ニ
ッケル被膜上へ障壁用の金被膜24を形成している口該
金被膜上にはanゲッタリング金属のソースとして働く
第1族の金属層25で被覆されたのち、金メッキ28を
施した接続ビン27をAu−an’ろう材26により結
合されている0これらの方法においては、いずれも中間
層として金層を形成しなければならずコスト的にも不利
である◎また接続ビンを取ル付けるパッド部分には、あ
らかじめモリブデンパッドを形成しておかなけれになら
ず工程的にもコスト的にも不利でsb、さらにろう付は
等の熱処理に際してもモリブデンの酸化を防ぐために水
素還元雰囲気で行なわなければならなかった。さらにモ
リブデンパッドとセラミック基板との密着性をもたせる
ためにガラスフリット等の添加物をモリブデンペースト
中に含めねばならず、導体抵抗も高くなる問題があった
Next, in order to lower the processing temperature, Au-8n or Au-8i, Au-8n-Pd) AAu-8n- was used as a brazing material.
A etc. were considered. A specific example is shown in FIGS. 3 and 4. In FIG. 3, a molybdenum layer 12 is attached to the surface of a ceramic substrate 11, and a thick film 13 is formed on the molybdenum layer by means such as plating. ′
Next, a gold coating 14 is applied to the nickel coating using gold paste.
Then, the connection bottle 16, which was plated with gold 17, was heated to form a gold-nickel solid solution.
8N brazing filler metal 15. In this method, the gold-nickel solid solution is formed at a temperature of about 700° C. under hydrogen reduction. Further, in FIG. 4, a molybdenum layer 22 is attached to the surface of a ceramic substrate 21, a nickel film 23 is formed on the molybdenum layer, and a gold film 24 for a barrier is formed on the nickel film. The coating is coated with a group 1 metal layer 25 that serves as a source of an gettering metal, and then a connecting pin 27 plated with gold 28 is bonded by an Au-an' brazing material 26. In both cases, a gold layer must be formed as an intermediate layer, which is disadvantageous in terms of cost.In addition, a molybdenum pad must be formed in advance on the pad where the connecting bottle is attached, which increases the process cost. This is disadvantageous both in terms of performance and cost, and heat treatments such as sb and brazing must be carried out in a hydrogen-reducing atmosphere to prevent oxidation of molybdenum. Furthermore, in order to provide good adhesion between the molybdenum pad and the ceramic substrate, additives such as glass frit must be included in the molybdenum paste, resulting in the problem of increased conductor resistance.

(発明の目的) 本発明の目的は、このような従来の欠点を除去せしめ、
従来の銀ろう材を用いる方法よシも低温(400℃以下
)で、しかも中性雰囲気で熱処理が出来、また他の従来
法で示したような障壁用の金被膜を施さず、更にはビン
取シ付は部分のモリブデンパッドを形成しない、非常に
単純な構造をもち、作業性およびコスト的に有利でしか
も十分なピン接着強度を有するろう付は方法を提供する
ことにある。
(Object of the invention) The object of the present invention is to eliminate such conventional drawbacks,
Compared to the conventional method using silver brazing material, heat treatment can be performed at low temperatures (below 400°C) and in a neutral atmosphere, and it does not require the application of a gold coating as a barrier as shown in other conventional methods. The object of the present invention is to provide a brazing method that does not require the formation of molybdenum pads on the parts, has a very simple structure, is advantageous in terms of workability and cost, and has sufficient pin bonding strength.

(発明の構成) すなわち本発明はセラミック基板上のろう付けする部分
にチタンの膜を形成する工程と該チタン膜上に周期律表
の第1族の金属層を形成する工程と、ろう材によシ入出
力電気接続ビンを第■族金属層上にろう付けする工程と
を有することを特徴゛とするろう付は方法である。
(Structure of the Invention) That is, the present invention includes a step of forming a titanium film on a portion to be brazed on a ceramic substrate, a step of forming a metal layer of Group 1 of the periodic table on the titanium film, and a step of forming a metal layer of Group 1 of the periodic table on the titanium film. and brazing the input/output electrical connection vias onto the Group I metal layer.

(実施例) 以下本発明を実施例に基づいて詳細に説明する。(Example) The present invention will be described in detail below based on examples.

第5図〜第8図は本発明のろう付は方法を示す図であシ
第9図は実施例において作製したピン付きセラミック基
板の模式図である。第5図に示すように多層セラミック
基板31の上2ミツ2表面上に金属の薄板をエツチング
等の手段によシ形成したろう付は部分の空いているマス
ク32を重ね合わせる。多層セラミック基板31はアル
ミナグリーンシートを用い導体としてモリブデン又はタ
ングステン等を印刷し積層プレス後1500℃以上の水
素還元雰囲気中で焼結したものでもよく、あるいはホウ
ケイ酸鉛系結晶化ガラスとアルミナから出来ているガラ
スセラミックグリーンシートを用い導体として金、銀、
銀−パラジウム系、金−白金系、銀−白金系等を印刷し
、積層プレス後1000℃以下の酸化性雰囲気中で焼結
したいわゆる低温焼結多層セラミック基板等でもよいO
ことでは銀−パラジウムを用いた後者の基板′を用いた
0次にチタン被膜を形成した0第6図に示すように、セ
ラミック基板に重ね合わされたマスクの上からスパッタ
リングによル300又〜100OXの厚さの≠タン膜3
3を形成する。第6図で形成したチタン膜の上から続け
て周期律表の第1族の金属の中からパラジウム層34を
第7図に示すように形成する。パラジウム層はチタン薄
膜形成と同様のスパッタリングによj)10001〜3
000Xの厚さになるように形成した◎スパッタはIQ
 torr以下にした後、Arガスを10 torr程
度まで導入して行なった0第8図にはチタン薄膜、第■
族金属の膜を形成したのちマスクを除去したときの断面
図を示す0第8図かられかるように本方法ではセラミッ
ク基板表面に直接にチタン膜が形成されておシこの点が
他の方法と大きく異なっている特徴の一つである0この
ようにして得られた金属パッド部を有するセラミック基
板を金5Oqb錫20qbf)重量比の合金ろう材35
がそれぞれに3mg程度取付けられた複数のコパール又
は4・2アロイ等の材質の入出力電気接続用ピン36上
に置き、第■族金属であるバラジクム層上に結合させる
。第9図には以上の方法によシ取り付けられた接続ピン
付き多層セラミック基板の模式図を示しであるが、金属
製ピン360表面にはメッキ等によシ形成した金の被膜
層37がコートしである口ろう付けを行なり処理温度と
しては、金8011b錫20%の重量比の合金ろう材の
融点が280℃であることから、300℃〜450℃の
温度範囲で10〜30分間行なった0第■族の金属例え
ばパラジウム層は金−錫ろう材の錫のゲッタリングを引
き起こし、金の錫に対する見かけの割合を多くする゛こ
とになシ、したがって冷却後又はろう材の凝縮後にろう
付けした結合部分の融点を上昇する効果がある0このこ
と社、ピン取シ付は後の熱サイクルを加える工程を有す
る場合に対して有効である口また接続ピンに施したー被
膜層においても、ろう付は処理の際、金被膜層が金−錫
ろり材と共に一部融けることにな〕金−錫ろう材中の金
の割合が増加し結合部分の融点を上昇させ同様の効果が
得られる。本方法によシろう付けした入出力電気接続ピ
ンと多層セラミック基板との接着強度は4. OKt/
−以上を示し、実装基板の入出力ピンとして十分な強度
を示す0 (発明の効果) 以上の如く、本発明のろう付は方法を採用することによ
シ、ろう付は処理を400℃以下という極めて低温で、
しかも中性雰囲気中で行なうことが出来、セラミック基
板表面にピンパッド用の厚膜金属(モリブデン、タング
ステン、金、銀、銀−パラジウム等)層をあらかじめ形
成する必要がなく、また障壁用の金被膜も施さない単純
な構造をもつた十分な接着強度を有するビン付き基板を
得ることが出来るようになりた。さらに本発明の方法は
ピンパッドの金属層を形成する際にエツチング等の湿式
1程を経ないためにセラミックに対する悪影響は全く与
えず信頼性の高いピン付き基板を提供することが出来、
また作業性およびコスト的にも有利となシ、ビン付は後
の熱サイクルに対しても十分に強いピン付は基板を得る
ことが出来るようになった◎ また実施例で用いたパラジウムの他の第1族の金属も使
用できる。さらにスパッタリングでなく、適時蒸着、メ
ッキ、スクリーン印刷などの膜形成手段を用いることが
できる。
5 to 8 are diagrams showing the brazing method of the present invention, and FIG. 9 is a schematic diagram of a ceramic substrate with pins produced in an example. As shown in FIG. 5, a thin metal plate is formed on the upper surface of the multilayer ceramic substrate 31 by means such as etching, and a blank mask 32 is superimposed thereon. The multilayer ceramic substrate 31 may be made of an alumina green sheet, printed with molybdenum or tungsten as a conductor, laminated and pressed, and then sintered in a hydrogen reducing atmosphere at a temperature of 1500° C. or higher, or made of lead borosilicate crystallized glass and alumina. Gold, silver,
It may also be a so-called low-temperature sintered multilayer ceramic substrate printed with silver-palladium, gold-platinum, silver-platinum, etc. and sintered in an oxidizing atmosphere at 1000°C or less after lamination pressing.
In particular, a zero-order titanium film was formed using the latter substrate using silver-palladium.As shown in FIG. 6, 300 to 100 ox thickness of ≠ tan film 3
form 3. Continuing on from the titanium film formed in FIG. 6, a palladium layer 34 is formed from metals of group 1 of the periodic table, as shown in FIG. The palladium layer is formed by sputtering similar to the formation of a titanium thin film j) 10001-3
Formed to a thickness of 000X ◎ Sputtering is IQ
After reducing the pressure to below 10 torr, Ar gas was introduced to about 10 torr.
As can be seen from Figure 8, which shows a cross-sectional view when the mask is removed after forming a film of group metal, this method forms a titanium film directly on the surface of the ceramic substrate, which is different from other methods. One of the characteristics that is significantly different from that of the ceramic substrate having the metal pad portion obtained in this way is that the ceramic substrate having the metal pad portion obtained in this way is mixed with an alloy brazing filler metal with a weight ratio of 5 Oqb of gold and 20 qbf of tin.
It is placed on a plurality of input/output electrical connection pins 36 made of a material such as copal or 4.2 alloy, each having about 3 mg attached thereto, and bonded to a Balazicum layer, which is a group Ⅰ metal. FIG. 9 shows a schematic diagram of a multilayer ceramic board with connecting pins attached by the above method, and the surface of the metal pin 360 is coated with a gold coating layer 37 formed by plating or the like. Since the melting point of the alloy brazing filler metal with a weight ratio of 8011b and 20% tin is 280°C, the processing temperature was 300°C to 450°C for 10 to 30 minutes. A layer of metals from group 0, such as palladium, will cause gettering of the tin in the gold-tin brazing material, increasing the apparent ratio of gold to tin, and therefore after cooling or condensation of the brazing material. This has the effect of raising the melting point of the attached joint part.In this case, attaching a pin attachment is effective when there is a process of applying heat cycles afterwards. During brazing, the gold coating layer partially melts together with the gold-tin filler metal.The proportion of gold in the gold-tin filler metal increases, raising the melting point of the bonded part and producing the same effect. It will be done. The adhesive strength between the input/output electrical connection pins and the multilayer ceramic substrate brazed using this method is 4. OKt/
- Indicates the above, and shows sufficient strength as an input/output pin of a mounting board. (Effects of the invention) As described above, by adopting the brazing method of the present invention, brazing can be performed at temperatures below 400°C. At an extremely low temperature,
Moreover, it can be carried out in a neutral atmosphere, and there is no need to previously form a thick metal layer (molybdenum, tungsten, gold, silver, silver-palladium, etc.) for the pin pad on the surface of the ceramic substrate, and there is no need to form a gold film for the barrier. It has now become possible to obtain a substrate with bottles that has a simple structure that does not require any bonding and has sufficient adhesive strength. Furthermore, since the method of the present invention does not involve wet etching such as etching when forming the metal layer of the pin pad, it does not have any adverse effects on ceramics and can provide a highly reliable substrate with pins.
It is also advantageous in terms of workability and cost, and it is now possible to obtain substrates with pins that are sufficiently strong against later thermal cycles. Group 1 metals can also be used. Furthermore, instead of sputtering, film forming means such as timed vapor deposition, plating, and screen printing can be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は、従来のピン付はセラミック基板を示
した図でう)、第5図〜第8図は本発明の方法を示す図
であル、第9図は本発明の方法によシ作製したピン付き
基板の模式囚である0図において、1.IL 21,3
1・・・セラミック基板、 2. 12. 22・・・
厚膜導体パッド層、3゜13.23・・・ニッケル層、
4・・・銀ろう、L16t27・ 36°°°金属1y
・6・ 17・ 28・ 37、−°。 金被膜層%14・・・金被膜、15,26,35・・・
金−錫ろう、24・・・金被膜、25・・・第■族金属
層、32・・・マスク、33・・・チタン膜、34・・
・第■族金属膜0 第1図 第2図 第3図 第4図 第5図 第6図 3 第7図 第δ図′ 兜9図
Figures 1 to 4 are diagrams showing conventional pin-equipped ceramic substrates, Figures 5 to 8 are diagrams showing the method of the present invention, and Figure 9 is a diagram showing the method of the present invention. In Figure 0, which is a schematic diagram of a board with pins manufactured by the method, 1. IL 21,3
1... Ceramic substrate, 2. 12. 22...
Thick film conductor pad layer, 3°13.23...nickel layer,
4...Silver solder, L16t27・36°°°metal 1y
・6・ 17・ 28・ 37, -°. Gold coating layer %14...Gold coating, 15,26,35...
Gold-tin wax, 24... Gold coating, 25... Group ■ metal layer, 32... Mask, 33... Titanium film, 34...
・Group ■ metal film 0 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 3 Figure 7 Figure δ' Kabuto Figure 9

Claims (2)

【特許請求の範囲】[Claims] (1)セラミック基板に金属製接続ピンをろう材によル
ろう付けする方法であって、セラミック基板上のろう付
けする部分にチタン膜を形成する工程と、該チタン膜上
に周期律表の第1族の金属膜を形成する工程と、ろう材
によシ接続ピンを該第■族金属層上にろう付けする工程
とを有することを特徴とするろう付は方法。
(1) A method of brazing metal connection pins to a ceramic substrate using a brazing material, which includes a step of forming a titanium film on the part to be brazed on the ceramic substrate, and a process of forming a titanium film on the periodic table on the titanium film. A brazing method comprising the steps of forming a Group 1 metal film and brazing a connecting pin onto the Group 1 metal layer using a brazing material.
(2)ろう材は金−錫ろう材である特許請求の範囲第1
項記載のろう付は方法◎ ゛
(2) Claim 1: The brazing material is a gold-tin brazing material.
The brazing method described in the section is ◎ ゛
JP5491084A 1984-03-22 1984-03-22 Soldering method Granted JPS60198761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5491084A JPS60198761A (en) 1984-03-22 1984-03-22 Soldering method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5491084A JPS60198761A (en) 1984-03-22 1984-03-22 Soldering method

Publications (2)

Publication Number Publication Date
JPS60198761A true JPS60198761A (en) 1985-10-08
JPH0227817B2 JPH0227817B2 (en) 1990-06-20

Family

ID=12983753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5491084A Granted JPS60198761A (en) 1984-03-22 1984-03-22 Soldering method

Country Status (1)

Country Link
JP (1) JPS60198761A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034450A1 (en) * 2002-10-11 2004-04-22 Tm Tech Co., Ltd. A sputtering apparatus having enhanced adhesivity of particles and a manufacturing method thereof
WO2004055873A1 (en) * 2002-12-14 2004-07-01 Tm Tech Co., Ltd. Thin film forming apparatus
CN113242650A (en) * 2021-05-20 2021-08-10 上海望友信息科技有限公司 Spraying graph generation method and system, electronic equipment and storage medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119663A (en) * 1981-12-31 1983-07-16 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Method of bonding connecting pin

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119663A (en) * 1981-12-31 1983-07-16 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Method of bonding connecting pin

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034450A1 (en) * 2002-10-11 2004-04-22 Tm Tech Co., Ltd. A sputtering apparatus having enhanced adhesivity of particles and a manufacturing method thereof
WO2004055873A1 (en) * 2002-12-14 2004-07-01 Tm Tech Co., Ltd. Thin film forming apparatus
CN113242650A (en) * 2021-05-20 2021-08-10 上海望友信息科技有限公司 Spraying graph generation method and system, electronic equipment and storage medium
CN113242650B (en) * 2021-05-20 2022-04-15 上海望友信息科技有限公司 Spraying graph generation method and system, electronic equipment and storage medium

Also Published As

Publication number Publication date
JPH0227817B2 (en) 1990-06-20

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