JPS6196754A - Substrate provided with pin - Google Patents
Substrate provided with pinInfo
- Publication number
- JPS6196754A JPS6196754A JP21774884A JP21774884A JPS6196754A JP S6196754 A JPS6196754 A JP S6196754A JP 21774884 A JP21774884 A JP 21774884A JP 21774884 A JP21774884 A JP 21774884A JP S6196754 A JPS6196754 A JP S6196754A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pin
- gold
- metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 239000010931 gold Substances 0.000 claims abstract description 34
- 229910052737 gold Inorganic materials 0.000 claims abstract description 30
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000919 ceramic Substances 0.000 claims abstract description 21
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000010936 titanium Substances 0.000 claims abstract description 11
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 11
- 230000000737 periodic effect Effects 0.000 claims abstract description 5
- 238000005219 brazing Methods 0.000 claims description 19
- 239000000945 filler Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 12
- 239000000463 material Substances 0.000 abstract description 9
- 239000010409 thin film Substances 0.000 abstract description 9
- 229910045601 alloy Inorganic materials 0.000 abstract description 7
- 239000000956 alloy Substances 0.000 abstract description 7
- 229910052763 palladium Inorganic materials 0.000 abstract description 6
- 238000002844 melting Methods 0.000 abstract description 5
- 230000008018 melting Effects 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 abstract description 4
- 229910000833 kovar Inorganic materials 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 3
- 230000007935 neutral effect Effects 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 239000004020 conductor Substances 0.000 description 14
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 13
- 229910052750 molybdenum Inorganic materials 0.000 description 13
- 239000011733 molybdenum Substances 0.000 description 13
- 239000010408 film Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002241 glass-ceramic Substances 0.000 description 2
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- IHWJXGQYRBHUIF-UHFFFAOYSA-N [Ag].[Pt] Chemical compound [Ag].[Pt] IHWJXGQYRBHUIF-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はパッケージ基板におけるピン取り付は構造に係
り、更に具体的にいえば多層セラミック基板の接続ピン
取り付は構造に係る。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to the structure of pin attachment on a package substrate, and more specifically relates to the structure of connection pin attachment on a multilayer ceramic substrate.
（従来技術） 最近のコンピュータシステムの高密度小型化。(Conventional technology) Recent computer systems have become more compact and dense.
高速化および高パフォーマンス化に対して実装レベルに
おけるパッケージ基板への要求はきびしいものになって
きている。具体的にはパッケージ基板において配線密度
を高め信号線幅を微細化したり、信号線導体の抵抗値を
下げること、絶縁材料の誘電率を下げること１等が要求
されており、これに応えるようなパッケージ基板技術が
開発されてきた。例えばアルミナグリーンシートを用い
た多層セラミック基板、ガラスセラミックスグリーンシ
ートを用い９００℃程度で焼結でき、ＡｕおよびＡｇ−
Ｐｄ導体が使える多層セラミック基板、またセラミック
基板上ヘスバッタ、蒸着等の薄膜技術を用いたパッケー
ジ基板、更には有機絶縁材料（ポリイミド等）を用い薄
膜導体と組み合せたパッケージ基板等々がある。このよ
うに高密度化、微細化された実装基板上へは超ＬＳＩチ
ップが多数実装されることになり、したがって、基板外
部と電気的に接続するためのＩ１０端子数は極めて多く
なってくる。そのためＩ１０端子を多層基板裏面にピン
で形成する技術が開発されている。The requirements for package substrates at the mounting level are becoming more and more demanding for higher speeds and higher performance. Specifically, there are demands for increasing wiring density on package substrates, miniaturizing signal line widths, lowering the resistance of signal line conductors, and lowering the dielectric constant of insulating materials. Package substrate technology has been developed. For example, multilayer ceramic substrates using alumina green sheets, glass ceramic green sheets can be sintered at about 900°C, and Au and Ag-
There are multilayer ceramic substrates that can use Pd conductors, package substrates that use thin film techniques such as Hess scattering and vapor deposition on ceramic substrates, and package substrates that use organic insulating materials (polyimide, etc.) in combination with thin film conductors. A large number of VLSI chips will be mounted on such a high-density and miniaturized mounting board, and therefore the number of I10 terminals for electrical connection with the outside of the board will become extremely large. Therefore, a technique has been developed in which the I10 terminal is formed using pins on the back surface of the multilayer substrate.
この多層セラミック基板に接続ピンを取り付ける従来技
術としては１例えばアルミナ多層基板において銀ろうを
用いてコバール又は４・２７０イ等の材質の接続ピンを
取り付けていた。第５図は。As a conventional technique for attaching connection pins to this multilayer ceramic substrate, for example, connection pins made of a material such as Kovar or 4.270I were attached to an alumina multilayer substrate using silver solder. Figure 5 is.
従来方法を説明するための断面図であり、アルミナグリ
ーンシートに形成したモリブデン又はタングステン等の
導体パッドおよびスルーホール中の導体を１５００℃以
上の温度で還元雰囲気中で焼結したのちのセラミ、り基
板１およびモリブデン又はタング反テン等の導体２が示
されている。この導体パッド部分にメッキによりニッケ
ル層３を形成し１次に、コバール又は４・２アロイの接
続ピン５を銀ろう４により取り付けている。銀ろうの組
成は、一般番こは人ｇ ６０ｍｏｇ ％ −Ｃｕ ４０
ｍｏｄ ％ （Ｄ共晶合金が使われており融点は７７
９℃であり、ろう付は処理温度は８１０℃程度であり、
モリブデン等の導体の酸化を防ぐために水素還元雰囲気
中で行なわれる０次に基板に取り付けられた接続ピンを
および導体が劣化しないように金メッキ
処理される。第６図には、金層６が形成された接続ピン
付き基板の断面図を示す０本方法はろう付は処理温度が
高く、基板上に形成した微細薄膜パターン等は、この温
度に加熱することは難かしく、一方あらかじめピンを基
板に取り付けたのち信号線等の微細薄膜パターンを形成
する場合においても、ピン付き基板上へ各種パターンを
形成する際の精度が低くなり作業性が悪くなる。また有
機絶縁フィルム（ポリイミド等）を用いて多層セラミッ
ク基板上へパターンを形成するパッケージ技術の場合で
も同様である。更にろう付は後接続ピンおよび導体パッ
ド部を金メッキする工程が含まれ作業性が悪い。This is a cross-sectional view for explaining the conventional method, in which conductor pads such as molybdenum or tungsten formed on an alumina green sheet and conductors in through holes are sintered in a reducing atmosphere at a temperature of 1500°C or higher. A substrate 1 and a conductor 2, such as molybdenum or tungsten, are shown. A nickel layer 3 is formed on this conductor pad portion by plating, and a connecting pin 5 made of Kovar or 4.2 alloy is then attached using silver solder 4. The composition of silver solder is general bank 60mog% -Cu 40
mod % (D eutectic alloy is used and the melting point is 77
9℃, and the processing temperature for brazing is about 810℃,
In order to prevent oxidation of conductors such as molybdenum, the connection pins attached to the zero-order board are gold-plated to prevent deterioration of the conductors. Figure 6 shows a cross-sectional view of a substrate with connection pins on which a gold layer 6 is formed.The brazing method requires a high processing temperature, and fine thin film patterns formed on the substrate are heated to this temperature. On the other hand, even when forming fine thin film patterns such as signal lines after attaching pins to a substrate in advance, the precision in forming various patterns on the pin-equipped substrate becomes low, resulting in poor workability. The same applies to packaging technology in which a pattern is formed on a multilayer ceramic substrate using an organic insulating film (polyimide or the like). Furthermore, brazing involves a step of gold plating the connection pins and conductor pads, which is difficult to work with.
次に処理温度を低げるためにろう材としてＡｕ −８ｎ
又はＡｕ−８ｉ 、 Ａｕ−ａｎ−Ｐｄ 、 Ａｕ−８
ｎ −Ａｇ等が検討された。具体的な一例を第７図およ
び第８図に示す、第７図においてはセラミック基板１１
の表面にモリブデン層１２を付着させ、該モリブデン層
上にメッキ法等の手段によりニッケルの被膜１３を形成
する。次に該ニッケル被膜上に金ペーストにより金の被
膜１４を形成し熱処理により金・ニッケル固溶体を形成
している。続いて金メッキ１７を施した接続ピン１６を
Ａｕ−ａｎろう材１５により結合してＧ゛る。この方法
において金・二、ケル固溶体を形成する際には約７００
℃の温度で水素還元中で行なっている。また第８図にお
いてはセラミ。Next, in order to lower the processing temperature, Au-8n was used as a brazing material.
Or Au-8i, Au-an-Pd, Au-8
n-Ag etc. were investigated. A specific example is shown in FIGS. 7 and 8. In FIG. 7, the ceramic substrate 11
A molybdenum layer 12 is attached to the surface of the substrate, and a nickel coating 13 is formed on the molybdenum layer by means such as plating. Next, a gold coating 14 is formed using gold paste on the nickel coating, and a gold/nickel solid solution is formed by heat treatment. Subsequently, the connection pins 16 coated with gold plating 17 are connected with the Au-an brazing material 15, and then G. In this method, approximately 700
It is carried out in hydrogen reduction at a temperature of °C. Also, in Figure 8, cerami.
り基板２１の表面にモリブデン層２２を付着させ、該モ
リブデン層上にニッケル被膜ｎを形成し、該ニッケル被
膜上へ障壁用の金被膜２４を形成している。A molybdenum layer 22 is deposited on the surface of the substrate 21, a nickel film n is formed on the molybdenum layer, and a gold film 24 for a barrier is formed on the nickel film.
該金被膜上にはＳｎゲッタリング金属のソースとして働
く第１族の金属層５で被膜したのち、金メッキ２８を施
した接続ピン２７をＡｕ−８ｎろう材２６により結合し
ている。これらの方法においては、いずれも接続ピンを
取り付けるパッド部分には、あ ゛らかしめモリブデ
ンパッドを形成しておかなければならず工程的にもコス
ト的にも不利であり、さらにろう付は等の熱処理に際し
てもモリブデンの酸化を防ぐために水素還元雰囲気で行
なわなければならなかった。さらにモリブデンパッドと
セラミック基板との密着性をもたせるためにガラスフリ
ット等の添加物をモリブデンペースト中に含めねばなら
ず、導体抵抗も高くなる問題があった。The gold film is coated with a metal layer 5 of the first group which acts as a source of Sn gettering metal, and then a connection pin 27 plated with gold 28 is connected by an Au-8n brazing material 26. In all of these methods, a molybdenum pad must be formed on the pad where the connection pin is attached, which is disadvantageous in terms of process and cost, and furthermore, brazing is disadvantageous. Even during heat treatment, it had to be carried out in a hydrogen reducing atmosphere to prevent oxidation of molybdenum. Furthermore, in order to provide good adhesion between the molybdenum pad and the ceramic substrate, additives such as glass frit must be included in the molybdenum paste, resulting in the problem of increased conductor resistance.
（発明の目的）
本発明の目的は、このような従来の欠点を除去せしめ、
従来の銀ろう材を用いる方法よりも低温（４５０℃以下
）で、しかも中性雰囲気で熱処理ができ５作業性が良好
で十分なピン強度を有するピン付き基板を提供すること
にある。(Object of the invention) The object of the present invention is to eliminate such conventional drawbacks,
To provide a substrate with pins that can be heat-treated at a lower temperature (450° C. or less) and in a neutral atmosphere than the conventional method using silver brazing material, has good workability, and has sufficient pin strength.
（発明の構成）
すなわち本発明は、セラミック基板上に形成されたチタ
ン層および該チタン層上に形成された周期律表の第１族
の金属層、更に該金属層上に金層を有し、金属製ピンと
該金層との間にろう材を介してなる構造をもつことを特
徴とするピン付き基板である。(Structure of the Invention) That is, the present invention has a titanium layer formed on a ceramic substrate, a metal layer of Group 1 of the periodic table formed on the titanium layer, and further a gold layer on the metal layer. This is a pin-equipped substrate characterized by having a structure in which a brazing material is interposed between a metal pin and the gold layer.
（実施例） 以下本発明を実施例に基づいて詳細に説明する。(Example) The present invention will be described in detail below based on examples.
第１図〜第４図は本発明を示す図であり第１図は実施例
において作製した本発明のピン付基板の構造を示す模式
図である。第２図に示すようにセラミ、り基板３１の表
面上にチタン金属の薄膜３２を被覆する。このセラミッ
ク基板３１はアルミナグリーンシートを用い内部配線導
体としてモリブデン又はタングステンを印刷し積層プレ
ス後１５００℃以上水素還元雰囲気中で焼結したもの、
あるいはガラスセラミックグリーンシートを用い導体と
して金、銀−パラジウム、金−白金、銀−白金、銀等々
を印刷し積層プレス後１つ００℃以下酸化性雰囲気中で
焼結した。いわゆる低温焼結セラミック基板等が使用で
きる。この実施例では後者の銀−パラジウムを印刷した
低温焼結セラミック基板を用いた。一方チタン薄膜はス
パッタリングにより５００Ａ〜２０００ Ａの厚さに形
成した。1 to 4 are diagrams showing the present invention, and FIG. 1 is a schematic diagram showing the structure of a pin-equipped substrate of the present invention produced in an example. As shown in FIG. 2, the surface of a ceramic substrate 31 is coated with a thin film 32 of titanium metal. This ceramic substrate 31 is made of an alumina green sheet, printed with molybdenum or tungsten as an internal wiring conductor, laminated and pressed, and then sintered in a hydrogen reducing atmosphere at 1500°C or higher.
Alternatively, glass-ceramic green sheets were used to print gold, silver-palladium, gold-platinum, silver-platinum, silver, etc. as conductors, and after laminated pressing, each sheet was sintered in an oxidizing atmosphere below 00°C. A so-called low-temperature sintered ceramic substrate or the like can be used. In this example, a low-temperature sintered ceramic substrate printed with the latter silver-palladium was used. On the other hand, the titanium thin film was formed to a thickness of 500A to 2000A by sputtering.
次に第３図に示すように周期律表第■族の金属として一
例としてパラジウム層３３を第２図に示したチタン薄膜
上に形成する。パラジウム層はチタン薄膜形成と同様に
スパッタリングにより５００Ａ〜２０００ Ａの厚さに
形成した。スパッタリングは（１０−’ ｔｏｒｒ
以下にした後Ａｒガスを導入し１Ｏ−２ｔｏｒｒ 程
度にして行なった。Next, as shown in FIG. 3, a palladium layer 33 is formed on the titanium thin film shown in FIG. 2 as an example of a metal of Group 1 of the periodic table. The palladium layer was formed to a thickness of 500A to 2000A by sputtering similarly to the formation of the titanium thin film. Sputtering is (10-' torr
After the temperature was reduced to below, Ar gas was introduced and the pressure was adjusted to about 10-2 torr.
更に第４図に示すような金層あを形成した。金層の形成
方法としては、スクリーン印刷法等による厚膜形成、又
はメッキ法、又は蒸着法、スパッタ法等々が利用できる
０層厚は５００ Ａ〜２０μｍの範囲であれば十分であ
る。このような第４図に示した構造をもつ金属パッド部
を有するセラミック基板をＡｕ８０（ｉ−８ｎ２０％
の重量比の合金ろう材３６ヲ各ビン当す０．５〜３ｍｇ
程度取り、多数のコバール又は４・２アロイからなる
接続ピン３７上に置き、金Ｍ３４上に結合させる。第１
図には取り付けられたピン付基板の構造の模式図を示し
であるが、接続ピン３７の表面にはメッキ等をこより形
成した金層がコートしである。ろう付けを行なう処理温
度としてはＡｕ ｇＱ ％ −＝ Ｓｎ ２０％の重量
比の合金ろう材の融点が約２８０℃であることから、３
００℃〜４５０℃の温度範囲で１０−（資）分間の条件
で行なった。基板に施した金層Ｕは、熱処理の際Ａｕ−
８ｎろう材と反応することによりＡｕがＳｎに対して見
かけ上、組成的に多くなり、したがって冷却後又はろう
材の凝縮後にろう付けした結合部分の融点を上昇させる
効果がある。このことはピン取り付は後の熱サイクルを
加える工程を有する場合に対して有効である。また接続
ピンに施した金層についてもろう付は処理の際、金層が
Ａｕ−８ｎろう材と共に融けることになりＡｕ−８ｎろ
う材中のＡｕの割合が増加し融点を上昇させ同様の効果
が得られる。ろう付けした接続ピンのセラミック基板と
の接着強度（引張り強度）は４．０〜７ｍ”以上を示し
、実装基板のＩ１０ピンとして十分な強度を示した。Furthermore, a gold layer as shown in FIG. 4 was formed. As a method for forming the gold layer, a thick film formation method such as a screen printing method, a plating method, a vapor deposition method, a sputtering method, etc. can be used, and it is sufficient that the zero layer thickness is in the range of 500 A to 20 μm. A ceramic substrate having a metal pad portion having the structure shown in FIG.
0.5 to 3 mg of alloy brazing filler metal in each bottle of 36 wt.
It is placed on a number of connecting pins 37 made of Kovar or 4.2 alloy, and bonded to gold M34. 1st
The figure shows a schematic diagram of the structure of the attached pin-equipped board, and the surface of the connection pin 37 is coated with a gold layer formed by plating or the like. Since the melting point of the alloy brazing filler metal with a weight ratio of Au gQ % -= Sn 20% is about 280°C, the processing temperature for brazing is 3.
The test was carried out in a temperature range of 00°C to 450°C for 10 minutes. The gold layer U applied to the substrate is Au-
By reacting with the 8n brazing filler metal, Au appears to be more abundant than Sn in terms of composition, which has the effect of increasing the melting point of the brazed joint after cooling or condensation of the brazing filler metal. This is effective in the case where pin attachment includes a subsequent step of applying a thermal cycle. Also, regarding the gold layer applied to the connecting pin, during the brazing process, the gold layer melts together with the Au-8n brazing material, increasing the proportion of Au in the Au-8n brazing material and raising the melting point, resulting in the same effect. is obtained. The adhesion strength (tensile strength) of the brazed connection pin with the ceramic substrate was 4.0 to 7 m'' or more, indicating sufficient strength as the I10 pin of the mounting board.
（発明の効果）
以上の如く１本発明のピン付基板の構造を採用すること
によりろう付は処理を４５０℃以下と低温で、しかもヂ
性雰囲気中で行なうことが出来、セラミック基板表面に
ピンパッド用の厚膜金属（モリブデン、タングステン、
金、金−白金等）層をあらかじめ形成する必要がなく、
十分な接着強度を有するピン付基板を得ることが出来る
ようになったー
さらに本発明により作業性に対しても有利となり、ピン
立て後の熱サイクルに強い実装基板としてのピン付き基
板を得ることが出来るようになつた。(Effects of the Invention) As described above, by adopting the structure of the pin-equipped substrate of the present invention, brazing can be performed at a low temperature of 450°C or less and in a neutral atmosphere, and pin pads can be attached to the surface of the ceramic substrate. thick film metals (molybdenum, tungsten,
Gold, gold-platinum, etc.) layer does not need to be formed in advance,
It is now possible to obtain a board with pins that has sufficient adhesive strength - Furthermore, the present invention has advantages in terms of workability and makes it possible to obtain a board with pins that can be used as a mounting board that is resistant to thermal cycles after pin mounting. Now I can do it.
なお、実施例では第■族金属としてパラジウムを用いた
が他の金属を用いても同様の効果がある。In the examples, palladium was used as the Group Ⅰ metal, but similar effects can be obtained by using other metals.
また金属膜形成方法は、スパッタリングの他に蒸着、メ
ッキ、スクリーン印刷など適時利用できる。In addition to sputtering, metal film forming methods such as vapor deposition, plating, and screen printing can be used as appropriate.
第１図は本発明のビン付基板の構造を示す模式図であり
、第２図〜第４図は不発明の製造工程を示す図であり、
第５図〜第８図は従来のピン付セラミック基板の構造を
示す図である。
図において、
１ 、１１ 、２１ 、３１・・・セラミック基板、２
，１２，２２・・・厚膜導体パッド層、３，１３，２３
・・・ニッケル層、４・・・銀ろう、５ 、１６．２７
．３７・・−接続ピン、６ 、１７ 。
妬、３８・・・金メッキ層、 １４ 、２４・・・金被
膜、１５，２６゜３６・・・Ａｕ−８ｎろう、５・・・
パラジウム層、３２・・・チタン金属被膜、３３・・・
■族金属被膜、あ・・・金層。
３２．７ｉ被膜
３１．セラミック屋ｄ反FIG. 1 is a schematic diagram showing the structure of the substrate with a bottle according to the present invention, and FIGS. 2 to 4 are diagrams showing the manufacturing process according to the invention,
5 to 8 are diagrams showing the structure of a conventional pin-equipped ceramic substrate. In the figure, 1, 11, 21, 31...ceramic substrate, 2
, 12, 22... Thick film conductor pad layer, 3, 13, 23
...Nickel layer, 4...Silver solder, 5, 16.27
．． 37...-Connection pin, 6, 17. 38...Gold plating layer, 14,24...Gold coating, 15,26°36...Au-8n wax, 5...
Palladium layer, 32...Titanium metal coating, 33...
■Group metal coating, ah...gold layer. 32.7i coating 31. ceramic shop dantai
Claims (1)
ン層上に形成された周期律表の第VII族の金属層、更に
該金属層上に金層を有し、金属製ピンと該金層との間に
ろう材を介してなる構造をもつことを特徴とするピン付
き基板。A titanium layer formed on a ceramic substrate, a metal layer of Group VII of the periodic table formed on the titanium layer, and a gold layer on the metal layer, between the metal pin and the gold layer. A board with pins characterized by having a structure made of brazing filler metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21774884A JPS6196754A (en) | 1984-10-17 | 1984-10-17 | Substrate provided with pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21774884A JPS6196754A (en) | 1984-10-17 | 1984-10-17 | Substrate provided with pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6196754A true JPS6196754A (en) | 1986-05-15 |
Family
ID=16709127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21774884A Pending JPS6196754A (en) | 1984-10-17 | 1984-10-17 | Substrate provided with pin |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6196754A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04267544A (en) * | 1991-02-22 | 1992-09-24 | Toshiba Corp | Semiconductor device |
| EP0660404A2 (en) * | 1993-12-27 | 1995-06-28 | Nec Corporation | Element joining pad for semiconductor device mounting board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5715446A (en) * | 1980-07-02 | 1982-01-26 | Hitachi Ltd | Semiconductor device |
| JPS59155950A (en) * | 1983-02-25 | 1984-09-05 | Shinko Electric Ind Co Ltd | Low melting-point glass seal type ceramic package for semiconductor device |
-
1984
- 1984-10-17 JP JP21774884A patent/JPS6196754A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5715446A (en) * | 1980-07-02 | 1982-01-26 | Hitachi Ltd | Semiconductor device |
| JPS59155950A (en) * | 1983-02-25 | 1984-09-05 | Shinko Electric Ind Co Ltd | Low melting-point glass seal type ceramic package for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04267544A (en) * | 1991-02-22 | 1992-09-24 | Toshiba Corp | Semiconductor device |
| EP0660404A2 (en) * | 1993-12-27 | 1995-06-28 | Nec Corporation | Element joining pad for semiconductor device mounting board |
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