JPH06283719A - Insulated-gate semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To operate the title semiconductor device at a higher frequency by a method wherein a semiconductor constituting a channel formation region is irradiated selectively with a laser beam from the vertical direction and a polycrystalline structure whose long axis is in the movement direction of carriers is formed. CONSTITUTION:Laminated bodies S1 to S3, 13 to 15, a conductor 23 and an insulator 24 are covered, and a fourth semiconductor S4 constituting a channel formation region CFR is laminated. When a silicon nitride film 16 is formed on its surface, CFRS 9, 9' are formed at the inside periphery of the S2, and an insulator 16 is formed on them. In addition, a laser beam is irradiated in order to make an amorphous semiconductor for the polycrystalline. Then, only a part which has been irradiated with the laser beam out of the fourth semiconductor is annealed and made polycrystalline. Carriers which flow from a source to a drain do not traverse a polycrystalline grain boundary, and their mobility can be made a high value at 400 to 500cm<2>V/sec.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a vertical channel type laminated insulating gate type semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor on a substrate.

[0002]

According to the present invention, a channel forming region is provided for this IGF, which is provided vertically or substantially perpendicularly to the upper surface of the substrate provided around the side of the laminate having at least three layers. A semiconductor having an amorphous or semi-amorphous structure is irradiated with intense light or laser light to be transformed into a polycrystalline structure having a long axis in the carrier moving direction, and the purpose is to operate at a higher frequency. To do.

According to the present invention, a semiconductor having a single crystal or polycrystalline structure for forming a channel is further provided around two sides of a laminated body having three layers, and two IGFs are formed by using this semiconductor.
The purpose of the present invention is to provide circuit elements such as inverters with high integration.

[0004]

In order to solve the above-mentioned problems, the present invention has a second semiconductor or an insulator and a third semiconductor having substantially the same shape on a first semiconductor on a substrate or an electrode on the substrate. And a first and a third semiconductor to form a source and a drain,
A channel forming region of a fourth semiconductor provided adjacent to a side portion of the stacked body has a polycrystalline structure having a long axis in a carrier moving direction, and a gate insulating film and a gate are formed on the fourth semiconductor. A method of manufacturing an insulating gate type semiconductor device having an electrode, wherein the fourth semiconductor forming a channel formation region is formed on the fourth semiconductor before or after the gate insulating film is formed on the fourth semiconductor. Intense light or laser light is selectively applied to the upper surface of the substrate in a direction perpendicular or substantially perpendicular to give a polycrystalline structure having a long axis in the moving direction of carriers. Further, in the present invention, the second semiconductor or insulator is particularly silicon carbide or silicon nitride, and the fourth semiconductor sandwiched between silicon carbide or silicon carbide as a gate insulating film is an amorphous or semi-amorphous semiconductor. Les - Zaani - by allowed to shift to the polycrystalline by Le, the mobility of carriers in the channel forming region 100 ~500 cm ² V / sec and, 0.05~1cm ² V / sec in the case of the conventional amorphous structure 50 to 100 times that of At this time, since it is possible in the structure of this semiconductor device that the irradiation direction of the laser light is the same as the direction of the current, the carrier mobility in the channel formation region is stable at 400 to 500 cm ² V. The value of / sec is obtained. This is because when performing laser annealing, the crystal axis direction (1,
This is because 0,0) matches the direction of the current. Further, at this time, in order to prevent the second laminated body from being single-crystallized at the same time as the single-crystallized semiconductor and to have a sufficient insulating property and a withstand voltage, the amorphous structure of silicon oxide, silicon carbide or silicon nitride is used. It is characterized by being an insulator.

Further, according to the present invention, hydrogen or fluorine is added to the semiconductor forming the channel forming region, which is the fourth semiconductor, by performing the laser annealing in the step after covering the fourth semiconductor with the gate insulator. Since hydrogen and fluorine segregate the crystal grain boundaries by the laser annealing because silicon and germanium whose main component is the above-mentioned semiconductor are used, the dangling bonds present especially in the crystal grain boundaries are large. It has the feature that it can be neutralized and the interface state density peculiar to IGF can be reduced to 3 × 10 ¹¹ cm ^-2 .

Furthermore, the film thickness of the second semiconductor or insulator is set to 1 μm or less, and the short channel length is set. As a result, we were able to obtain a high cutoff frequency of 50 to 200 MHz.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a longitudinal sectional view of a laminated IGF according to the present invention and its manufacturing process. In this drawing, four IGFs are provided on the same substrate as shown in FIG. 1 (D), but in FIGS. 1 (A) (B) (C), two IGFs (62) (63) are produced. A production example is shown.

The same is true when 10 ² to 10 ⁶ IGFs are formed on the same substrate. In the drawing, a first conductive film (2) (hereinafter referred to as E1) is provided as a lower electrode and a lead on an insulating substrate such as a quartz glass or borosilicate glass substrate. In this embodiment, a translucent conductive film containing tin oxide as a main component is formed to a thickness of 0.5 μm. This was subjected to selective etching. Furthermore, a first non-single crystal semiconductor (2) having P or N type conductivity on this upper surface (hereinafter simply referred to as S1)
1000-3000Å, second semiconductor or insulator, preferably insulator (4) (hereinafter simply referred to as S2) (0.3-3 μ), third semiconductor (5) having the same conductivity type as the first semiconductor
(Hereinafter simply referred to as S3) (0.1 to 0.5 μ) was laminated to provide a laminated body (stack or S). With this stack
It has NIN and PIP structure (I is an insulator).

In the drawing, a heat-resistant metal conductor (6) containing ITO (indium tin oxide), MoSi ₂ , TiSi ₂ , WSi ₂ , W, Ti, Mo, Cr, etc. as a main component is provided on the upper surface in the drawing. Cr was laminated to a thickness of 0.2 μm by the PCVD method. Further, this conductor was selectively removed using a second photomask. Next, in order to make the laminated body thicker, LP CVD method (depressurized gas phase method) PC
The silicon oxide film (7) may be formed to a thickness of 0.3 to 1 μm by the VD method or the photo CVD method. N ₂ O for PCVD method
And SiH ₄ were reacted at 250 ℃.

N and P are N ⁺ N or P ⁺ P and N
It was effective to reduce the contact resistance between P or N and the electrode as ⁺ NINN ⁺ , P ⁺ PIPP ⁺ (I is an insulator or an intrinsic semiconductor). Further, in FIG. 1B, the insulating film (7) is removed by a selective etching method using a mask, and further the conductors (6), S3, S2 and S1 thereunder are removed using the SiO ₂ film (7) as a mask. Then, the remaining laminated bodies were formed into substantially the same shape. Plasma vapor phase etching was performed using the same mask, for example, HF gas or a mixed gas of CF ₄ + O ₂ was used, and the etching rate was 2000 Å / min with 0.1 to 0.5 torr 30 W.

Thereafter, these laminated bodies S1 (13) and S2 (1
4), S3 (15), conductor (23), insulator (24) to cover the channel formation region (hereinafter also referred to as CFR) to form an intrinsic or P-type non-single-crystal semiconductor fourth semiconductor (S4) Was laminated as. This fourth semiconductor is a silane or disilane glow discharge method (PCVD method), a photo CVD method, an LT C method, or the like on the substrate.
Room temperature to 500 ℃ using VD method (also called HOMO CVD method), eg 250 ℃ in PCVD method, 0.1 torr, 30W, 13.56M
Provided under the condition of Hz, amorphous
Alternatively, a non-single-crystal silicon semiconductor with a semi-amorphous (semi-amorphous) or polycrystalline structure is used. In the present invention, an amorphous or semi-amorphous semiconductor (hereinafter referred to as SAS
I say) mainly.

Furthermore, a silicon nitride film (16) is formed on the upper surface of the fourth semiconductor surface in the same reaction furnace without exposing the surface of the fourth semiconductor to the atmosphere.
Is produced by a vapor-phase reaction of silane (disilane may be used) and ammonia by a mercury-excited method by an optical CVD method, and the thickness is 300 ~
It was 2000Å. This insulating film is activated by electromagnetic energy or light energy with a frequency of 13.56MHz to 2.45GHz, and DM
Silicon carbide may be formed by a chemical vapor phase reaction method of methylsilane such as S (H ₂ Si (CH ₃ ) ₂ or MMS (H ₃ Si (CH ₃ )).

Further, silicon nitride may be formed by the PCVD method. Then, in the vicinity of the side of S2 (14), the channel forming regions (9) and (9 ') and the insulator (16) as the gate insulating substance (26) thereon were formed. The fourth semiconductor (S4)
A diode junction is formed with S1 and S3.

Further, in order to polycrystallize the amorphous semiconductor for CFR, the substrate is not turned on without the Q switch.
After the temperature was adjusted to 0 to 300 ° C, laser light was irradiated. To this YAG
Laser (wavelength 1.06μ, repetition frequency 3KHz, operation speed
30 cm / sec, average output 2 W, light diameter 250 μφ). Then, only the portion of the fourth semiconductor irradiated with the laser light is annealed to be polycrystallized (average crystal grain size of 500 Å or more, long axis of crystal grain size of 1 to 5 μm, preferably solute. Length from drain to drain or longer) (Fig. 1
(E) (70)). It goes without saying that it is more preferable that the grain size of this polycrystal is one polycrystal having a thickness of S4 so as to cover the entire channel region in its width. Therefore, the carriers flowing from the source to the drain do not cross the polycrystalline grain boundary (grain boundary), and the mobility thereof is 400 to 500 cm ² V / sec.
And it was possible to make it a high value. That is, even if a grain boundary is formed, it mainly grows in the direction along the flow of carriers, and in addition, this boundary has hydrogen and oxygen existing from the beginning bonded to the dangling bonds at the grain boundary and neutralize it. However, the generation of recombination centers could be minimized.

At this time, since the upper surface of the fourth semiconductor is covered with the gate insulating film, the laser anneal is performed downward from the top of the stack by the downward growth method without contact with the atmosphere. To do. That is, there is one crystallization part at the top. For this reason, crystal growth occurs reasonably, the crystallinity is good, and it was also possible to substantially single crystal the semiconductor in the depth direction of the region irradiated with laser light. The semiconductor of the present invention has a feature that even if it is polycrystallized, its grains are formed in the vertical direction and carrier movement does not cross the grain boundary. It is presumed that this is an inherent effect of laser annealing the fourth semiconductor of the vertical channel IGF having the laminated structure.

Further, in the laser annealing of this YAG laser, the region irradiated with light can be selectively made CFR only by moving the substrate. An amorphous structure was left between adjacent IGFs that do not require carrier movement (Fig. 1 (59)), and isolation between IGFs could be performed.

In FIG. 1B, as the next step, an electrode contact hole (19) is further opened by a third mask, and then, a second gate insulating film (26) is formed on the laminated body so as to cover the gate insulating film (26). The conductive film (17) was formed to a thickness of 0.3-1 μm. This conductive film (17) is a transparent conductive film such as ITO (indium tin oxide), TiSi ₂ , MoSi ₂ , WSi ₂ , W, Ti,
A heat resistant conductive film such as Mo or Cr may be used. Here, a silicon semiconductor (electrical conductivity of 1 to 100 (Ωcm) ^-1 ) doped with a large amount of P or N type impurities was formed by the PCVD method. That is, 1% of phosphorus was added to a thickness of 0.3 μm, and a non-single-crystal semiconductor of microcrystalline (grain size 50 to 300 Å) was produced by the PCVD method.

Then, a resist (18) was formed on the upper surface. Further, as shown in FIG. 2C, anisotropic etching was performed in the vertical direction by the fourth photolithography technique. That is, for example, reactive gases such as CF ₂ Cl ₂ , CF ₄ + O ₂ and HF were turned into plasma, and this plasma was applied vertically from above the substrate as shown by arrow (28). Then conductor (17)
This film is removed by etching the thickness (0.3 μ) on the plane, but has a total of 2-3 μ of the total of the thickness of the stack and the thickness of the film on the side surface in the vertical direction. Therefore, when anisotropic etching was performed in the vertical direction as shown in the drawing, these conductors as shown by broken lines (38) and (38 ') could be left in regions other than the mask (18).

As a result, the gate electrode could be selectively provided only around the side of the laminate. Furthermore, this gate electrode does not exist above the third semiconductor, resulting in the third semiconductor.
The parasitic capacitance between the semiconductor and the gate electrode could be made substantially equal to zero. Thus, FIG. 1C was obtained.

FIG. 1C is a plan view of FIG.
A vertical section of A'is shown. The numbers correspond to each other.
As is clear from FIGS. 1 (C) and (D), IGF (62) (6
3) has two CFRs (9) and (9 '), and has the source or drain (13) and the drain or source (15) in common. It also has two gates (20) (20 '). S3 electrode is a heat-resistant non-reactive metal (23) where IT
It is a laminated body of O + Cr (a metal whose main component is chromium is called Cr).
9) extends to the lead (21) and the lead of S1 is provided by (12). That is, in the drawing, two IGFs can be provided as a pair. This is because S2 between the channels of two IGFs is insulative, and if S2 has a width of 15μ, it has a resistance of several tens of MΩ and can be configured substantially independently. It could have a completely different structure than the semiconductor. Furthermore, in FIG. 1D, another pair of
IGF (61) (64) is shown at the top of the plan view. this
A longitudinal sectional view of CC ′ corresponding to IGF is shown in FIG. 2 (A).

That is, a contact (19 ") is provided with the semiconductor (16) connected to S3 (15) of the IGF (64),
It has a conductor (16) connected to S3 of (61), and further IGF
(64) and IGF (62) (63) are connected to each other by a conductor (16). Between these two conductors (16) (16 ') (58)
Since S3 underneath is amorphous, sufficient insulation is required if it is 10 to 30 μm, so isolation is not particularly required. Of course, in the case of the second photomask of FIG. 1, S3
It is preferable to selectively remove also because the isolation can be further improved.

In the IGF of the present invention, the channel forming regions (9) (9 ') (9 ") (9"') are laser-annealed.
It contains hydrogen or fluorine depending on the polymer and has a polycrystalline structure. The polycrystals are electrically isolated from each other by the amorphous semiconductor region (59) in S4 (25). That is, when the laser annealing is performed by irradiating the laser light from the upper direction, only the region constituting the IGF is selectively irradiated to be single crystal or polycrystal, and the isolation region between the IGFs ( 59) makes it possible to maintain the insulation by leaving the amorphous state.

This is a great difference from the isolation structure when a semiconductor device integrated using only a single crystal semiconductor is provided. Furthermore, this vertical channel type
In IGF, after forming the gate electrode, S4
Of the area not covered by the gate electrode of C, N,
It is also effective to ion-implant or sputter O 2 into an insulated amorphous region.

Further, FIG. 1E shows B in FIG. 1D.
-B 'shows a vertical sectional view. In the drawing, the lower first electrodes (12) (12 ') are independently provided, and the upper second electrodes (16) (23) are connected to leads (21) contacts (19). You can see that Two IGFs (63), (6
The amorphous semiconductor (59) between 4) performs isolation between the polycrystallized (70) CFRs of each IGF.

Thus, the source or drain is connected to S1 (1
3 ') S4 (2 having channel forming regions (9) (9')
5), the drain or source is formed by S3 (15), the gate insulator (16) is formed on the side surface of the single crystal or polycrystalline channel forming region, and the gate electrode (20) is formed on the outer surface thereof.
We were able to make a laminated IGF (10) with (20 '). In the present invention, the channel length is determined by the thickness of S2 (14), and is generally 0.1 to 3 µ, and here 0.5 µ.
Further, since the channel forming region is made single crystal or polycrystal, the cutoff peripheral portion can be set to 30 to 100 MHz, for example, 60 MHz in the N channel IGF. It was effective to control the threshold voltage of S4 (16) by adding a small amount (0.1 to 10 PPM) of boron impurities to form S4 (16) as an intrinsic or P or N semiconductor.

Thus, the drain (15) and the source (1
2), as gate (20) or (20 ') V _PP = 5V, V _GG
= 5V, operating frequency 55.5MHz was obtained. The following is a description of the inverter, which is a major application field of the IGF of the present invention.

In FIGS. 2 (A) and 2 (B), the inverter IGF corresponds to the equivalent circuit in FIGS. 3 (A) and 3 (B). The driver (61) uses the left IGF to
I used the IGF on the right side. In the drawing (A), an enhancement type in which the gate electrode (20) of the load and V _DD (65) are connected continuously, and in FIG. 2 (B), the output (62) and the gate electrode (2) are connected.
Depression-type IGF in which (0) and () are consecutive.

Further, the output of this inverter is composed of (66), and the two IGFs (61) (64) on this substrate are kept in the same semiconductor block (13) (14), (1) without being separated from each other.
The feature is that it is combined with 5). The equivalent circuit of the inverter of FIG. 2 (A) is shown in FIG. 3 (A), but the upper electrodes corresponding to the IGFs (61) and (64) in FIG. 1 (D) are independent as two IGFs. (19 ”) (1
9) Thus, one IGF (64) (load) is connected to the electrode (19), drain (15), channel (9), source (13), electrode (12) or output (66) and the other IGF (load). The driver (61) can be provided as an electrode (12 '), a drain (13), a channel (9'), a source (15), and an electrode (68). As a result, two IGFs could be integrated with one S1-S3 block to form an enhancement-type inverter.

FIG. 2B shows the equivalent circuit of FIG.
As shown in (A), it is a depletion type inverter. That is, FIG. 2B shows a case where the lower electrode is divided into two. One IGF load (64)
At V _DD (65), lower electrode (12), drain (13), channel forming region (9) 'source (15), electrode (19) or output (66), other IGF (driver) ( 61) consists of drain (15), channel forming region (9 ') source (13') electrode (12 ') and V _SS (68), and outputs input (67) to gate electrode (20'). (66) was pulled out from S3.

[0030]

As described above, the present invention has a vertical channel, and the channel forming region has a polycrystalline structure to enable high speed operation. Furthermore, since S2 is insulating,
Even if a large voltage of 30 to 100V is applied between S1 and S3, it will not be short-circuited. In addition, even if either S1 or S3 acts as a drain, it can be said to be the most ideal IGF because the outside is insulated. Furthermore, since S2 is also insulating under the channel of S4, two IGFs that contribute to the improvement of frequency characteristics can be made in pairs at the same time. The number of manufacturing masks is enough to be 5 times, and many features such as mask accuracy are not required.
In addition to being able to make it extremely short, 2 to 1 μ, it was possible to make it possible.

In the backward leak in the IGF of the present invention, S1 or S3 as shown in FIG. 1 is changed to Si _X C _1-X (0 <x <1 for example x = 0.2) to further increase S2. By making it an insulator, the impurities of S1 and S3 are less likely to flow into S2, and the N--I junction or P--I junction is
The value was 10 nA / cm ² or less even when 10 V was applied in the reverse direction.

In operation at higher temperature, the metal of the electrode is liable to be mixed into the non-single crystal S1 and S3 and is likely to be defective. Therefore, the side close to this electrode is Si _X C _{1 -X} (0 <x < For example, x = 0.2). As a result, the device was operated at 150 ° C. for 1000 hours, but no malfunction was observed when 1000 devices were evaluated. This is an extremely high reliability, considering that if S1 or S3 is formed only from amorphous silicon in close contact with this electrode, it will not withstand 10 hours at 150 ° C.

Further, because of such a laminated type IGF, it becomes possible to form a plurality of IGFs, resistors and capacitors on a substrate, particularly an insulating substrate, without using a high precision photolithography technique as in the past. And it has become possible to develop it into a solid-state display such as a liquid crystal display or a chromic display. The non-single crystal semiconductor in the present invention is silicon, germanium or silicon carbide Si _X C _1-X (0
<X <1), and silicon carbide, silicon oxide, or silicon nitride was used as the insulator.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a process of a laminated insulating gate type semiconductor device of the present invention.

FIG. 2 shows an inverter structure of a stacked insulating gate semiconductor device of the present invention.

FIG. 3 shows an equivalent circuit of the inverter shown in FIG.

[Explanation of symbols]

 13 First Semiconductor 14 Second Semiconductor 15 Third Semiconductor 9 Fourth Semiconductor 20 Gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display part // H01L 27/12

Claims (3)

[Claims] 1. A laminated body in which a second semiconductor or an insulator and a third semiconductor are laminated in substantially the same shape on a first semiconductor on a substrate or on an electrode on the substrate, The semiconductor of No. 3 constitutes a source and a drain, and the channel forming region of the fourth semiconductor provided adjacent to the side portion of the laminated body has a polycrystalline structure having a long axis in the carrier moving direction. A method of manufacturing an insulating gate type semiconductor device having a gate insulating film and a gate electrode on the fourth semiconductor, the method comprising: forming a gate insulating film on the fourth semiconductor; In the step, the fourth semiconductor forming the channel formation region is irradiated with intense light or laser light selectively in a direction perpendicular or substantially perpendicular to the upper surface of the substrate to form a polycrystal having a long axis in the moving direction of carriers. The structure Insulated gate semiconductor device manufacturing method according to claim. 2. A laminated body in which a second semiconductor or an insulator and a third semiconductor are laminated in substantially the same shape on a first semiconductor on a substrate or an electrode on the substrate, wherein the first and the first semiconductors are laminated. The semiconductor of No. 3 constitutes a source and a drain, and the channel forming region of the fourth semiconductor provided adjacent to the side portion of the laminated body has a polycrystalline structure having a long axis in the carrier moving direction. A method of manufacturing an insulating gate type semiconductor device, comprising a gate insulating film and a gate electrode provided on the fourth semiconductor, wherein strong light or laser light constitutes a channel formation region in the fourth semiconductor. Insulating gate type semiconductor device characterized by selectively irradiating a region to be transformed into a single crystal or a polycrystal and leaving a fourth semiconductor adjacent to the region as an amorphous or semi-amorphous structure. Manufacturing method. 3. In an insulating gate type semiconductor device, a non-single-crystal semiconductor forming a channel forming region provided on an insulating surface has crystal growth in the direction of carriers moving from a source to a drain, and the non-single crystal semiconductor of the channel forming region is formed. An insulating gate type semiconductor device characterized in that an isolation region having an amorphous structure is provided around the side.