JPS5827364A - Insulated gate type field effect semiconductor device - Google Patents

Abstract

PURPOSE:To obtain characteristics similar to a single crystal semiconductor even in a thin film structure of a field effect semiconductor device by forming a channel forming region under a gate at a semi-amorphous semiconductor having fine crystallinity formed on a substrate. CONSTITUTION:A pair of impurity regions 29, 30 are formed at both sides of a channel forming region on a semi-amorphous semiconductor 20 having fine crystallinity on a substrate 1. Gate electrodes 35 are formed on the channel forming region and an insulator 33. A field insulator 31 is formed on a pair of impurity regions 29, 30 forming a source and a drain.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device (hereinafter referred to as GF
In particular, by using a microcrystalline semi-amorphous semiconductor (hereinafter referred to as SAS) provided on a substrate and having a size of 5 to 200 A for the channel formation region under the gate, it can also be applied to a thin film structure. The aim was to obtain properties similar to those of a single-crystal half body.

In the present invention, a SAS is formed by a plasma OVD method on a substrate, particularly a substrate that does not react with the semi-consolidated material above it, such as a glass or ceramic substrate, or a substrate with which ohmic contact is made in the case of a conductive substrate, and this is actively engineered. GFETK
This is something I wanted to use. Regarding this SAS, 0 is written in patent m (semi-amorphous semiconductor patent application filed on April 30, 1982, filed on April 30, 1982, patent application filed on August 30, 1987-120322855) filed by the present inventor. For example, even in the case of a glass substrate with an amorphous structure that does not have a single crystal in a silicon semiconductor, or a stainless steel substrate with a polycrystalline structure, its electric-photoconductivity is AMI.
When applying light energy of (100mW/c) 1×
The present inventor has experimentally discovered that the SAS has extremely excellent properties with It's quite something.

Furthermore, the present inventor has proposed that such SAS
A structure having a vertical cross-sectional view as shown in FIG. 1 is known as an FET. In FIG. 1, a gate electrode (s), Ql, is made of a heat-resistant material such as molybdenum on an insulating substrate (1).

Furthermore, a gate insulating film (11) is formed of silicon oxide to a thickness of 0.1 to 0.5 μm by CVD. Next, on this top surface
s is formed, and selective etching is performed only on the channel type gate of (5) I (10). Furthermore, the N-type semiconductor layers (6) and (7) in the N-channel IGFET & are selectively formed using the photo-etching method, and aluminum is formed using the vacuum evaporation method for the P-channel IGFET (2). Form and selectively etch the source (9) and drain (8) as shown in Figure 1.
I have completed T.

In this structure, the gate insulator (0]) is formed by the CVD method, so the density is not high, and as a result, the gate electrode (
3) and the semiconductor (5) may be short-circuited, so the insulator 0]) must be made thicker than 0.3 μm.

As a result, the gate voltage becomes a large voltage of 20 to 60 V, and the so-called 1, 5 to 5 gate voltage (6) and the drain (7) -
It is necessary to precisely align the wire. However, when there are irregularities on the substrate, alignment with a high accuracy of 1 μ or more is impossible.

As a result, we created a tolerance of 20 to 30μ,
Therefore, the drain voltage is also as high as 50 to 50V.1.
Low voltage drive of 5-10v is completely impossible.

In addition, the so-called channel-type doped semiconductor with structural sensitivity [closely adheres to the source (6) in this part unless it is completely etched away.

The drain ('7) is shorted. However, even if this back surface becomes the completed structure shown in Figure 1, it will be exposed in the air, so the structural sensitivity may not be a problem in As, but in SAS, such a first The case shown in the figure is completely inappropriate.

In the present invention, SAS is used for the channel forming region, and the lower side,
The upper and side parts are all covered with an insulator or a semiconductor with a high impurity concentration, and the gate is also controlled by utilizing the structural sensitivity of this semiconductor. Therefore, instead of the conventional 40-80V drive, it is possible to drive at 5-IOV for both the gate voltage and the drain voltage, and furthermore, it has the feature that 1.5-IOV drive is essentially possible due to its structure.

Furthermore, in Figure 1, the gate electrode (4), source (6), and drain (7) are made using photomasks four times.
are made of different materials, and if you try to make lead wiring on the board with a metal with low resistance, you will need two photomasks on the top surface, making it six times in total, but only I4 wiring can be done. In addition to making the channel forming region with SAS, it is also a major feature of having it as a device that it can be integrated and manufactured easily.

Embodiment 1 The present invention will be described in detail below with reference to the drawings. Embodiment 1 FIG. 2 is a vertical sectional view showing the manufacturing process of IGF IiiT of the present invention.

In Figure 2 (4), the substrate (1) side is insulating (polysilane) or silicon fluoride is diluted with helium or hydrogen, and the
rr reactor and heated to 100~400@O, e.g. 3000'', the reactive gas is applied with direct current, high frequency (500KH2~50MHz e.g. 13,56
MHz) or microwave (1~10IH2 e.g. 2
．． 45GH2) (7) Apply electromagnetic energy with an output of 2O-200W to cause glow discharge or arc discharge,
These reactive gases and carrier gases are turned into plasma,
An intrinsic or substantially intrinsic SAS having microcrystalline properties is formed on a substrate by decomposition and reaction.

This SAS not only has crystallinity on the order of a short range of 5 to 20 OA, but also has zero recombination center neutralizing agents using halogen elements such as hydrogen and fluorine, which neutralize dangling bonds in silicon. .01 To neutralize, lithium,
1 alkali metal such as sodium or potassium
It may be added to a concentration of 0 to 10 cm-'.

This SAS has a dark conductivity of 1 x 10 to 3 x 10 (fLcm)
', and is 10'-10' (A Cm5', lo ~ 1t 3 times thicker than As. The photoconductivity is IXIσ' ~ 8 x 10L (U Cm)' under AMI conditions. Experimentally, it has 10-3X10 of As (10-10 times larger than acJ).

Therefore, the electron hole flowing through this SAS is 464j/
l is also 10 x 1d times larger than As, and this SAS is
Its use as a semiconductor for the channel formation region of ET is extremely important in making semiconductor devices for high-speed response. Furthermore, Figure 2 (A) shows the mask Q1) selectively formed to a thickness of 1 to 5 μm. Then, the first photomask (2) was used here. This may be a silicon oxide film or a polyimide film made of a heat-resistant organic resin, or a polyimide film made by a low pressure plasma vapor phase method.

In the drawing, the source region (
c), a drain region (a), and a channel forming region (c).

After this, the AS'J or SAS semiconductor layer (
C) was formed to a thickness of 0.1 to 1 μm in the same manner as the semiconductor layer. At this time, 0.2 to 2 t of phosphorus, which is a V-valent impurity, and boron, which is a ■-valent impurity, were added to the N- or P-channel IGFET dXN or P-type semiconductor layer, respectively. .

Thus, FIG. 1(A) was obtained.

Then, a pair of semiconductor layers H, (30) of one conductivity type are formed in regions (c) and (a) as a source and a drain. Furthermore, a field insulator (31) is formed on this upper surface by a film of silicon carbide or polyimide 4 () with a thickness of 0.1 to 1 μm.
Figure 2 was obtained by forming it to a thickness of .

Next, the field insulator in the region (c)' I JIF 5 and the electrode contact hole (32) was selectively removed using a second photomask (3).

After this, the gate insulator (3 oxide film) was processed by plasma oxidation method to 300%
It was formed to a thickness of ~200OA. That is, oxygen or an oxidizing gas is decomposed and activated by microwaves of 2.45 GHz @power 1OO~500 W), and the substrate is placed in this activated oxidizing gas at a temperature of 300~500''C. An oxide film, especially a silicon oxide film, was formed on the surface when the SAS wire was made of silicon.

Insulating film of silicon oxide, silicon nitride, etc.
It may be formed to the thickness of OA. Furthermore, in order to obtain a non-volatile memory, it is effective to form a cluster or a thin film of semiconductor or metal in the gate insulator and use it as a charge trapping center.

Alternatively, it may be MNO8Jfj4. The present invention has a degree of freedom in determining these factors depending on the application of the GFET.

After forming the gate insulator (33) in this manner, an opening (32) is formed in the source or drain (drain in the drawing) using a third 7-oto mask (3), and then an electrode (35) is formed.
, (34)! J-do (36) was fabricated using a metal film selectively using a fourth photomask.

It is effective to form the electrodes and leads by using vacuum evaporation and photoetching of aluminum or the like, or electroless plating and photoetching of metal such as nickel.

? t tr 4-L2 In order to prevent these metals from penetrating into the underlying insulating film or semiconductor layer, a method combining a lift-off method and an electroless plating method was preferred. That is, in FIG. 2(D), the electrode lead (3
5) (See Figure 2 (A) for the part where Qj” is not provided.
In this method, a resist for a mask is provided and a metal film is formed on the upper surface and other surfaces of the resist, and then only the mask and the gold bridge film thereon are selectively eluted and removed.

In the manner described above, an IGNET having the vertical cross-sectional structure shown in FIG. 2(D) was obtained. At this time, a pair of impurity regions (c) + (30) function as a source and a drain,
The channel forming region α has a channel length of 0°3 to 20°.
In particular, μ can be set to 2 to 3 μ, and a frequency response 10 to 10 times higher than that of the conventional structure shown in FIG. 1 using As can be obtained.

Furthermore, the driving voltage is 1.5. ~IOV typically 5-10
It was possible with V, and it was possible to lower it to 1/2 to 115 of the conventional value. As is clear from the drawing, the SAS constituting the channel forming region 0 has a gate insulator (33
) and has a lower electrode (1)
In particular, the channel forming region is all covered with an insulating film and a semiconductor on the top, bottom, and side surfaces, so there is no deterioration due to exposure to air or air.

Furthermore, in the present invention, the SAS has the characteristics that it is formed on a material that does not react with 61AS'4, such as a glass substrate, and there is no impurity problem on the channel formation region of the SAS, compared to the AS.

Although the present invention shows only one mechanical GFET, it is easy to integrate and provide a plurality of mechanical GFETs on the same substrate. It is also easy to arrange the leads in multiple layers.

Further, when the substrate (1) is made of translucent glass, it is possible to make it act as a phototransistor that irradiates light from the lower layer and detects the presence or absence of the light. Furthermore, various applications are possible, such as integrating this and using it as an imaging semiconductor device.

The present invention focuses on silicon. But sic i (0i x
zl), Si, N, -, (0<x<4), germanium, IV compounds are also suitable.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a conventional semiconductor device. FIG. 2 is a vertical cross-sectional view showing the semiconductor of the present invention and its manufacturing process. Summary 1

Claims (1)

[Claims] (1) An insulated gate field effect semiconductor device 02, characterized in that a semi-amorphous semiconductor having microcrystalline properties is provided on a substrate, and a channel formation region under the gate is provided. A pair of impurity regions are provided on a semi-amorphous semi-substrate having microcrystallinity with a channel forming region in between, and on the channel forming region and on the insulator. An insulated gate field effect semiconductor device characterized in that a field insulator is provided on a pair of impurity regions forming a source and a drain.