JP2535721B2 - Insulated gate type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to an insulating gate type semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor on a substrate.
Regarding

[0002]

According to the present invention, a channel forming region is provided for the IGF, which is provided in the periphery of the side of the laminated body in which at least three layers are laminated, and which is provided perpendicularly or substantially perpendicularly to the upper surface of the substrate. A semiconductor having an amorphous or semi-amorphous structure is irradiated with intense light or laser light to be transformed into a polycrystalline structure having a long axis in the carrier moving direction, and a higher frequency operation is performed.

[0003]

In order to solve the above problems, the present invention provides a first semiconductor, a second semiconductor or an insulator,
The first semiconductor and the third semiconductor are provided by contacting the third semiconductor with the second semiconductor or the insulator.
The third semiconductor and the third semiconductor to form a source and a drain, and a fourth semiconductor adjacent to a side portion of the first semiconductor, the second semiconductor or the insulator, a third semiconductor, and the third semiconductor. A gate insulating film and a gate electrode are provided on the semiconductor of No. 4, and the portion forming the channel forming region of the fourth semiconductor has crystal growth in the direction of carriers moving from the source to the drain. The semiconductor device has a structure in which an isolation region having an amorphous structure is provided around the side of the channel formation region.

The second semiconductor or insulator of the device of the present invention is particularly silicon carbide or silicon nitride, and the fourth semiconductor sandwiched between silicon carbide or silicon carbide as a gate insulating film is amorphous or by allowed to denature the semi-amorphous semiconductor into a polycrystalline by laser annealing, and 100~500cm ² V / sec the mobility of carriers in the channel forming region, in the case of the conventional amorphous structure 0.05~1cm ² V / 5 of sec
It is also possible to set 0 to 100 times . At this time, since it is possible in the structure of this semiconductor device to make the irradiation direction of the laser light the same as the direction of the current, the carrier mobility in the channel formation region is stable at 400 to 500 cm ² V / V.
The value of sec is obtained. This is because the crystal axis direction (1, 0, 0) coincides with the direction of current when performing laser annealing. Further, at this time, in order to prevent the second laminated body from being single-crystallized at the same time as the single-crystallized semiconductor and to have a sufficient insulating property and a withstand voltage, the amorphous structure of silicon oxide, silicon carbide or silicon nitride is used. It is characterized by being an insulator.

When manufacturing the semiconductor device of the present invention ,
By performing laser annealing in a step after covering the fourth semiconductor with a gate insulator, silicon having hydrogen or fluorine added to the semiconductor forming the channel formation region, which is the fourth semiconductor, as a main component, Since germanium is used, these hydrogen and fluorine segregate the crystal grain boundaries by laser annealing, and can neutralize dangling bonds that are particularly abundant at the crystal grain boundaries, and the interface state density peculiar to IGF can be obtained. It has a feature that it can be reduced to 3 × 10 ¹¹ cm ⁻² .

Furthermore, the film thickness of the second semiconductor or insulator is set to 1 μm or less, and the short channel length is set. As a result, a high cutoff frequency of 50 to 200 MHz could be obtained.

A semiconductor having a single crystal or polycrystal structure for forming a channel is further provided around the two sides of a laminate having three layers, and two IGFs are produced by using this semiconductor to form an inverter or the like. It is also possible to highly integrate and provide a circuit element.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows one embodiment embodying the idea of the present invention, showing a longitudinal sectional view of a laminated IGF and its manufacturing process. This drawing is shown in FIG.
Although four IGFs are provided as shown in FIG.
(A) (B) (C) shows a production example for producing two IGFs of IGF (62) (63).

The same applies to the case where 10 ² to 10 ⁶ IGFs are formed on the same substrate. In the drawing, a first conductive film (2) (hereinafter referred to as E1) is provided as a lower electrode and a lead on an insulating substrate such as a quartz glass or borosilicate glass substrate. In this embodiment, a transparent conductive film containing tin oxide as a main component is formed to a thickness of 0.5 μm. This was subjected to selective etching. Further, a first non-single crystal semiconductor (2) (hereinafter simply referred to as S1) having a P or N type conductivity on the upper surface is 1000 to 3000 Å, and a second semiconductor or insulator, preferably an insulator (4) (hereinafter Simply referred to as S2 (0.3 to 3 μ), a third semiconductor (5) having the same conductivity type as the first semiconductor (hereinafter simply referred to as S3) (0.
1 to 0.5 μ) were laminated to provide a laminate (stack or S). By this stacking, NIN, PIP structure (I
Is an insulator).

In the drawings, ITO (indium tin oxide), MoSi ₂ , TiSi ₂ , WSi ₂ , and
A heat-resistant metal conductor (6) containing W, Ti, Mo, Cr or the like as a main component was laminated with Cr to a thickness of 0.2 μm by the PCVD method. Further, this conductor was selectively removed using a second photomask. Next, in order to make the laminated body thicker, the silicon oxide film (7) may be formed in advance to a thickness of 0.3 to 1 μm by the LP CVD method (pressure-reduced vapor phase method) PCVD method or the photo CVD method. . In the case of the PCVD method, the reaction between N ₂ O and SiH ₄ was performed at 250 ° C.

Let N and P be N ⁺ N or P ⁺ P and N
It was effective to lower the contact resistance between P or N and the electrode as ⁺ NINN ⁺ , P ⁺ PIPP ⁺ (I is an insulator or an intrinsic semiconductor). Further, in FIG. 1B, the insulating film (7) is removed by a selective etching method using a mask, and further the conductors (6), S3, S2 and S1 thereunder are removed using the SiO ₂ film (7) as a mask. Then, the remaining laminated bodies were formed into substantially the same shape. Plasma vapor etching, eg HF gas or CF ₄ +, all with the same mask
0.1 to 0.5 torr 30 using a mixed gas of O ₂
An etch rate of 2000Å / min was set as W.

After this, these laminated bodies S1 (13) and S2
(14), S3 (15), conductor (23), insulator (2
4) Covering the channel formation region (hereinafter also referred to as CFR)
Intrinsic or P-type non-single-crystal semiconductor constituting the above was laminated as a fourth semiconductor (S4). This fourth semiconductor is
Glow discharge method (PCV of silane or disilane on the substrate
D method), photo CVD method, LT CVD method (HOMO CV
Room temperature to 500 ° C, for example, 250 ° C in PCVD method, 0.1 torr, 30
It is provided under the condition of W, 13.56 MHz, and uses a non-single-crystal silicon semiconductor having an amorphous structure, a semi-amorphous structure, or a polycrystalline structure. In the present invention, an amorphous or semi-amorphous semiconductor (hereinafter referred to as SAS) is mainly shown.

Furthermore, a silicon nitride film (1) is formed on the upper surface thereof in the same reaction furnace without exposing the fourth semiconductor surface to the atmosphere.
6) was prepared by a photo-CVD method using silane (disilane may be used) and ammonia by a gas phase reaction of a mercury excitation method, and the thickness was 300 to 2000 Å. This insulation film is 13.56M
DMS (H ₂ Si (CH ₃ )) activated by electromagnetic energy or light energy with a frequency of Hz to 2.45 GHz.
₂ , silicon carbide may be formed by a chemical vapor phase reaction method of methylsilane such as MMS (H ₃ Si (CH ₃ )).

Further, silicon nitride may be formed by the PCVD method. Then, around the side of S2 (14), the channel forming regions (9) and (9 ') and the insulating material (16) as the gate insulating material (26) thereon were formed. The fourth semiconductor (S4) forms a diode junction with S1 and S3.

Further, in order to polycrystallize the amorphous semiconductor for CFR, the substrate was heated to 200 to 300 ° C. without the Q switch and then irradiated with laser light. YAG laser (wavelength 1.06μ, repetition frequency 3KH
z, operation speed 30 cm / sec, average output 2 W, light diameter 250 μφ). Then, only the portion of the fourth semiconductor irradiated with the laser beam is annealed to be polycrystallized (average crystal grain size of 500 Å or more, long axis of crystal grain size 1 to 5).
μ, preferably the length from the source to the drain or more) (FIG. 1E (70)). It goes without saying that it is more preferable if the grain size of this polycrystal is one polycrystal having a thickness of S4 so as to cover the entire channel region in its width. Therefore, carriers flowing from the source to the drain did not cross the polycrystalline grain boundary (grain boundary), and the mobility could be set to a high value of 400 to 500 cm ² V / sec. That is, even if a grain boundary is formed, it mainly grows in the direction along the carrier flow. However, the generation of recombination centers could be minimized.

At this time, since the upper surface of the fourth semiconductor is covered with the gate insulating film, the laser annealing is performed downward from the upper portion of the stack by the downward growth method without contact with the atmosphere. That is, there is one crystallization part at the top. For this reason, crystal growth naturally occurs, the crystallinity is good, and it was also possible to substantially single crystal the semiconductor in the depth direction of the region irradiated with the laser light. The semiconductor of the present invention has a feature that even if it is polycrystallized, its grains are formed in the vertical direction and carrier movement does not cross the grain boundary. It is estimated that this is an inherent effect of laser annealing the fourth semiconductor of the laminated vertical channel IGF.

Further, in the laser annealing of this YAG laser, the region irradiated with light can be selectively made CFR only by moving the substrate. It was possible to perform isolation between IGFs by leaving an amorphous structure between adjacent IGFs that do not require carrier movement (FIG. 1 (59)).

In FIG. 1B, as the next step, an electrode contact hole (19) is further opened by a third mask, and thereafter, a gate insulating film (2) is formed on the laminated body.
A second conductive film (17) having a thickness of 0.3 to 1 μm was formed so as to cover 6). This conductive film (17) is a transparent conductive film such as ITO (indium tin oxide), TiSi ₂ ,
A heat resistant conductive film such as MoSi ₂ , WSi ₂ , W, Ti, Mo, Cr may be used. Here, a silicon semiconductor (electric conductivity of 1 to 10) heavily doped with P or N type impurities is used.
0 (Ωcm) ⁻¹ ) was made by the PCVD method. That is, 0.
A non-single crystal semiconductor having a thickness of 3 μm and containing 1% of phosphorus and having a microcrystalline property (particle size 50 to 300 Å) was produced by the PCVD method.

Then, a resist (18) was formed on the upper surface. Further, as shown in FIG. 2C, anisotropic etching was performed in the vertical direction by the fourth photolithography technique. That is, for example, CF ₂ Cl ₂ , CF ₄ + O ₂ , H
A reactive gas such as F was turned into plasma, and this plasma was applied vertically from above the substrate as shown by the arrow (28). Then, the conductor (17) has a thickness (0.3 μ) on the plane.
Etching removes this coating, but on the sides it has a vertical thickness of 2-3 .mu.m, which is the sum of the laminate thickness and the coating thickness. Therefore, when anisotropic etching is performed in the vertical direction as shown in the drawing, these conductors as shown by broken lines (38) and (38 ') could be left in regions other than the mask (18).

As a result, the gate electrode could be selectively provided only around the side of the laminate. Furthermore, this gate electrode does not exist above the third semiconductor, resulting in the third semiconductor.
The parasitic capacitance between the semiconductor and the gate electrode could be made substantially equal to zero. Thus, FIG. 1C was obtained.

FIG. 1C is a plan view A- of FIG.
A vertical section of A'is shown. The numbers correspond to each other.
As is clear from FIGS. 1 (C) and (D), IGF (62)
(63) has two CFRs (9) and (9 '), and is a source or drain (13), a drain or source (1
5) have in common. Two gates again (20)
(20 '). The electrode of S3 is a laminated body of heat resistant non-reactive metal (23) here ITO + Cr (a metal whose main component is chromium is referred to as Cr), and a contact (19) for the multilayer film is further provided here with a lead ( 21) and the lead of S1 is provided by (12). That is, in the drawing, two IGFs can be provided as a pair. This is because S2 between the two IGF channels is insulative, and if S2 has a width of 15 μ, it has a resistance of several tens of MΩ and can be configured substantially independently. It could have a completely different structure than the semiconductor. Further, in FIG. 1D, another pair of IG
F (61) (64) are shown at the top of the plan view. A longitudinal sectional view of CC ′ corresponding to this IGF is shown in FIG.

That is, the semiconductor (16) connected to S3 (15) of IGF (64) is provided with a contact (19 "), and has a conductor (16) connected to S3 of IGF (61). IGF (64) and IGF (62) (63)
Are connected to each other by conductors (16). Between the two conductors (16) and (16 ') (58), since S3 under the conductor (58) is amorphous and has a sufficient insulating property of 10 to 30 .mu.m, isolation is not particularly required.
Of course, in the case of the second photomask in FIG. 1, it is preferable to selectively remove S3 as well because the isolation can be further improved.

Further, in the IGF of the present invention, the channel forming regions (9), (9 '), (9 ") and (9"') contain hydrogen or fluorine by laser annealing and have a polycrystalline structure. The polycrystals are electrically isolated from each other by the amorphous semiconductor regions (59) in S4 (25). That is, when the laser annealing is performed by irradiating the laser beam from above, only the region forming the IGF is selectively irradiated to be made single crystal or polycrystal, and the isolation region between IGFs (59).
It is possible to maintain the insulating property by leaving the amorphous state.

This is a great difference from the isolation structure when a semiconductor device integrated using only a single crystal semiconductor is provided. Further, in this vertical channel type IGF, after the gate electrode is formed,
It is also effective to ion-implant or sputter C, N, and O into a region of S4 that is not covered by the gate electrode to form an insulated amorphous region.

Further, FIG. 1E shows B in FIG. 1D.
-B 'shows a vertical cross-sectional view. In the drawing, the lower first electrodes (12) (12 ′) are independently provided, and the upper second electrodes (12) (12 ′) are provided.
It can be seen that the electrodes (16) and (23) of (3) are connected to the leads (21) and contacts (19). Also two IG
Amorphous semiconductor (59) between F (63) and (64)
Has performed isolation between polycrystallized (70) CFRs of each IGF.

Thus, the source or drain is connected to S1 (1
3 ') S4 having channel forming regions (9) (9')
(25), a drain or a source is formed by S3 (15), a gate insulator (16) is formed on the side surface of the single crystal or polycrystalline channel forming region, and gate electrodes (20), (20 ') are formed on the outer surface thereof. Stacked type IGF (10)
I was able to make In the present invention, the channel length is determined by the thickness of S2 (14), which is generally 0.1 to 3 μm.
Here, it is set to 0.5 μ. Further, since the channel forming region is made single crystal or polycrystal, the cutoff peripheral portion is 30 to 100 MHz, for example, 6 in N channel IGF.
It could be 0 MHz. It was effective to add a small amount (0.1 to 10 PPM) of boron impurities to S4 (16) during film formation to control the threshold voltage as an intrinsic or P or N semiconductor.

Thus, the drain (15) and the source (1
2), V _PP = as the gate (20) or (20 ')
It was possible to obtain 5V, V _GG = 5V, and an operating frequency of 55.5 MHz. An inverter, which is a large application field of the IGF of the present invention, will be described below.

In FIGS. 2 (A) and 2 (B), the inverter IGF corresponds to the equivalent circuit in FIGS. 3 (A) and 3 (B). Driver (61) is the left IGF
Was used for loading. In the drawing (A), the enhancement type in which the gate electrode (20) of the load and V _DD (65) are connected continuously, and in FIG.
2 shows a depletion type IGF in which the gate electrode (20) and the gate electrode (20) are connected.

Further, the output of this inverter is composed of (66), and the two IGFs (61) and (64) on this substrate are not separated from each other and are the same semiconductor block (13).
The inverter of FIG. 2 (A), which is characterized by being provided in combination with (14) and (15), has an equivalent circuit shown in FIG. 3 (A).
The upper electrodes corresponding to 1) and (64) are made to be independent as two IGFs (19 ″) and (19).
One IGF (64) (load) to electrode (19), drain (15), channel (9), source (13), electrode (12) or output (66) and another IGF (driver).
The electrode (12 ′) of (61) can be provided as the drain (13), the channel (9 ′), the source (15), and the electrode (68). As a result, two IGFs are replaced by one S
An enhancement type inverter could be integrated with the blocks 1 to S3.

FIG. 2B shows the equivalent circuit of FIG.
As shown in (A), a depletion type inverter is configured. That is, FIG. 2B shows a case where the lower electrode is divided into two. 1 IGF load (6
4) V _DD (65), lower electrode (12), drain (13), channel forming region (9) 'source (15),
Electrode (19) or output (66), drain (15) in other IGF (driver) (61), channel forming region (9 ′) source (13 ′) electrode (12 ′), V _SS (6
8), the input (67) is pulled out to the gate electrode (20 ') and the output (66) is pulled out from S3.

[0030]

As described above, the present invention enables a high speed operation by forming the channel forming region into a polycrystalline structure. Furthermore, since S2 is insulative, no short circuit occurs even if a large voltage of 30 to 100 V is applied between S1 and S3. Even if either S1 or S3 acts as a drain, it can be said to be the most ideal IGF because the outside is insulated. Further, under the channel of S4, two IGFs that contribute to the improvement of frequency characteristics can be arranged in pairs at the same time because S2 is insulating.

The backward leak in the IGF of the present invention is
S1 or S3 as shown in FIG. 1 is replaced with Si _x C _1-x (0
<X <1 For example, x = 0.2), the impurities of S1 and S3 are converted into S2 by converting S2 into an insulator.
Flow into the N-I junction or P
-I junction leakage is 10 nA even if 10 V is applied in the reverse direction.
/ Cm ² or less.

In operation at higher temperature, the metal of the electrode is liable to be mixed into the non-single crystal S1 and S3, which is likely to cause a defect. Therefore, the side close to this electrode is Si _x C _1-x (0 <x
<1 for example x = 0.2). The result is 1 at 150 ° C
The device was operated for 000 hours, but no malfunction was observed when 1000 devices were evaluated. This is an extremely high reliability, considering that if S1 or S3 is formed only from amorphous silicon in close contact with this electrode, it will not withstand 10 hours at 150 ° C.

Further, when the laminated type IGF is used, it becomes possible to form a plurality of IGFs, resistors and capacitors on a substrate, particularly an insulating substrate, without using a high precision photolithography technique as in the past. And it has become possible to develop it into a solid-state display such as a liquid crystal display or a chromic display. The non-single crystal semiconductor in the present invention is silicon, germanium or silicon carbide Si _x C.
_1-x (0 <x <1), and silicon carbide, silicon oxide, or silicon nitride was used as the insulator. Further, also in terms of manufacturing the semiconductor device of the present invention, it is sufficient to use the manufacturing mask 5 times,
In addition to the fact that the channel length can be extremely shortened to 0.2 to 1 μm, many features such as no need for mask precision can be provided.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a process of a laminated insulating gate type semiconductor device of the present invention.

FIG. 2 shows an inverter structure of a stacked type insulated gate semiconductor device of the present invention.

FIG. 3 shows an equivalent circuit of the inverter of FIG.

[Explanation of symbols]

 13 First Semiconductor 14 Second Semiconductor 15 Third Semiconductor 9 Fourth Semiconductor 20 Gate

Claims (1)

(57) [Claims] 1. A first semiconductor, a second semiconductor or an insulator, and a third semiconductor are provided in contact with the second semiconductor or an insulator to provide the first semiconductor and the third semiconductor.
A first semiconductor and a third semiconductor to form a source and a drain, a first semiconductor, a second semiconductor or an insulator, a fourth semiconductor adjacent to a side portion of the third semiconductor , A gate insulating film and a gate are formed on the fourth semiconductor.
An electrode is provided, a portion forming the channel forming region of the fourth semiconductor has crystal growth in the direction of carriers moving from the source to the drain, and an amorphous region is formed around the channel forming region. An insulating gate type semiconductor device characterized in that an isolation region having a structure is provided.