JPH088366B2 - Insulated gate type field effect semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical channel type stacked gate type insulated gate field effect semiconductor device using a non-single crystal semiconductor on a substrate.

[0002]

2. Description of the Related Art Conventionally, a vertical channel type insulated gate field effect semiconductor intended to operate at a higher frequency by providing a channel forming region of a short distance around the side of a laminated body having at least three layers. The device is known.

[0003]

However, it is desirable that the channel forming region in the vertical channel type insulated gate field effect semiconductor device is made single crystal. However, due to manufacturing problems, a single crystal semiconductor is used in advance. Difficult to form. Therefore, the present invention relates to an insulated gate field effect semiconductor device developed to solve the above problems. That is, in the present invention, the grain boundary is formed in the channel formation region in the insulated gate field effect semiconductor device parallel to the carrier flow direction even if it has a polycrystalline structure, and the grain boundary is generated so as to cross the carrier flow direction. It is something that is not allowed. Therefore, the present invention makes it possible to irradiate the channel forming region of a semiconductor having an amorphous or semi-amorphous structure with intense light or laser light to transform it into a single crystal or polycrystal structure and to operate at a higher frequency. .

According to the present invention, the second semiconductor or insulator is particularly silicon carbide or silicon nitride, and the fourth semiconductor sandwiched between silicon carbide or silicon carbide as a gate insulating film is amorphous or semi-crystalline. As an amorphous semiconductor, these are transformed by laser annealing into a single crystal or a polycrystal so that the grain boundary does not cross the carrier flow. According to the present invention, the fourth semiconductor is a semi-amorphous semiconductor having an intermediate property between a single crystal semiconductor and an amorphous semiconductor, so that the carrier mobility in this channel formation region is 10 cm ² V / sec.
To a 500 cm ² V / sec, to no 0.051 cm ² V / sec in the case of the conventional amorphous structure is obtained by a 100-fold to 10-fold of 1cm ² V / sec. Further, at this time, the second semiconductor or the insulator at the same time as the single-crystallized fourth semiconductor is prevented from being single-crystallized and has sufficient insulating property and withstand voltage. The feature is that it is made of silicon or silicon nitride.

The semiconductor forming the channel forming region, which is the fourth semiconductor, is covered with a gate insulator and then the laser is formed.
When the annealing is performed, the interface state density peculiar to the insulated gate field effect semiconductor device is 3 × 10 ¹¹ cm because silicon and germanium containing hydrogen or fluorine added as the main component are used. It becomes a small value of ^-2 . Furthermore, in the present invention, the film thickness of the second semiconductor or the insulator is 1 μm or less, and the short channel length is set. As a result, the cut-off frequency of the insulated gate field effect semiconductor device is 50
I was able to make it as high as MHz or 200 MHz.

[0006]

In order to achieve the above object, an insulated gate field effect semiconductor device according to the present invention comprises a first
The substrate (1) on which the electrode (12) of
2) A first semiconductor (13) formed on the first semiconductor (13) and a second semiconductor or insulator (14) formed on the first semiconductor (13)
At least a third semiconductor (15) formed on the second semiconductor or insulator (14), a second electrode (16) formed on the third semiconductor (15), A laminated body in which the first to third semiconductors (13) to (15) are laminated in substantially the same shape, and a single crystal semiconductor and a non-single crystal semiconductor provided adjacent to a side portion of the laminated body. A fourth semiconductor (25) made of a semi-amorphous semiconductor having an intermediate property of the above, and gate electrodes (20), (20) provided on the fourth semiconductor (25) via a gate insulating film (26). ′) And the first and third semiconductors (13) and (15) form a source region and a drain region, and a fourth semiconductor (25) near the end of the source region or the drain region. The channel forming regions (9) and (9 ') formed in
(9) and (9 ') are characterized by having a polycrystal structure modified so that the carriers that move in (9') do not cross the grain boundary.

[0007]

[Operation] According to the present invention, after the laminated body made of the first to third semiconductors is formed, the fourth laminated body is formed so as to cover the laminated body.
The semiconductor of is formed. Next, after the insulating gate film is formed on the fourth semiconductor, the channel formation region is annealed from the insulating gate film with laser light. The fourth semiconductor having an intermediate property between the single crystal semiconductor and the non-single crystal semiconductor is annealed so that only the region forming the channel formation region has a polycrystalline structure. With such a structure, the characteristics of the insulated gate field effect semiconductor device at high frequencies can be improved by crystallizing only the channel formation region having a short distance.

Further, according to the present invention, when the channel formation region is annealed, carriers are transformed so as to have a grain boundary that does not cross the grain boundary, so that disappearance due to recombination centers existing in the grain boundary is reduced. can do. Further, according to the present invention, after forming the insulated gate film on the fourth semiconductor, only the region which becomes the channel formation region is annealed. Therefore, when the channel formation region is annealed, it is covered with the gate insulation film and exposed to the atmosphere. A crystal structure having good crystallinity.

[0009]

EXAMPLES FIGS. 1A to 1E are vertical cross-sectional views of a stacked insulated gate field effect semiconductor device of this example. In FIG. 1, as shown on the same substrate, 4
Although one insulated gate field effect semiconductor device is provided, FIGS. 1 (A), (B) and (C) show two insulated gate field effect semiconductor devices (62) and (63). An example of an effect semiconductor device is shown. 10 ² or more on the same substrate
The same applies to the case of making 10 ⁶ insulated gate field effect semiconductor devices.

In FIG. 1, a first conductive film (2) is provided as a lower electrode or lead on an insulating substrate (1) such as a quartz glass or borosilicate glass substrate. In this embodiment, the first conductive film (2) is formed as a translucent conductive film containing tin oxide as a main component and having a thickness of 0.5 μm. This was subjected to selective etching. Further, on the first conductive film (2), a P type or N type is formed.
Å to 3000Å of a first non-single-crystal semiconductor (3) (hereinafter, simply referred to as the first semiconductor S1) having a conductivity type of
A second semiconductor or insulator, preferably an insulator (4) (hereinafter simply referred to as the second semiconductor S2), with a thickness of 0.3 μm to 3 μm, and further above A third semiconductor (5) having the same conductivity type as the first semiconductor (hereinafter, simply referred to as the third semiconductor S3) is 0.1 μm
Or 0.5 μm thick.

The first semiconductor S1 to the third semiconductor S3 are laminated to form one laminated body (stack, that is, S). The laminated body S
Has a NIN, PIP structure (I is an insulator or an intrinsic semiconductor) by the above lamination. In Figure 1, ITO on top
(Indium tin oxide) MoSi ₂ , TiSi ₂ , WSi ₂ , W
, A heat-resistant metal conductor (6) such as Ti, Mo, or Cr is used here as Cr.
Was laminated by PCVD to a thickness of 0.2 μm. Further, this conductor was selectively removed by using the second photomask.

Next, in order to make the laminated body S thicker,
A silicon oxide film (7) with a thickness of 0.3 μm to 1 μm prepared in advance by LP CVD method (decompression vapor phase method), PCVD method, or optical CVD method.
May be formed. In case of PCVD method, N ₂ O and SiH ₄
It was prepared by carrying out the reaction with 250 ° C. This N, P
As N ⁺ N or P ⁺ P as N ⁺ NINN ⁺ , P ⁺ PIPP
It was effective to reduce the contact resistance between P or N and the electrode as ⁺ (I is an insulator or an intrinsic semiconductor). Further, in FIG. 1B, the insulating film made of the silicon oxide film (7) is removed by a selective etching method using a mask, and the conductor (6) below the silicon oxide film (7) is used as a mask. The third semiconductor S3, the second semiconductor S2, and the first semiconductor S1 were removed, and the remaining stacked bodies S were formed into substantially the same shape. Plasma vapor phase etching was performed using the same mask, for example, HF gas or a mixed gas of CF + O 2 was used, and the etching rate was 2000 Å / min at 0.1 torr to 0.5 torr 30 W.

Thereafter, a channel is formed by covering the first semiconductor S1 (13), the second semiconductor S2 (14), the third semiconductor S3 (15), the conductor (23) and the insulator (24). The intrinsic or P-type non-single-crystal semiconductor forming the region is used as a fourth semiconductor S4.
Was laminated as. This fourth semiconductor S4 is a silane or disilane glow discharge method (PCVD method, photo CVD method) on the substrate.
Method, LT CVD method (also called HOMO CVD method)) at room temperature to 500 ℃, for example 250 ℃ in PCVD method,
It is provided under the condition of 0.1torr, 30W, 13.56MHz.
A non-single crystal silicon semiconductor having an amorphous structure, a semi-amorphous structure, or a polycrystalline structure is used. In this embodiment, an amorphous or semi-amorphous semiconductor is mainly shown.

Further, on the upper surface thereof, in the same reaction furnace,
The silicon nitride film (16) was prepared by the photo-CVD method without exposing the semiconductor surface to the atmosphere, and silane (disilane was acceptable) and ammonia by the vapor-phase reaction of the mercury excitation method, and the thickness was 300 Å Or 2000 Å. This insulating film is 13.5
DMS (H ₂ Si (CH ₃ ) ₂ ) activated by electromagnetic energy or light energy with a frequency of 6MHz to 2.45GHz
Silicon carbide may be formed by a chemical vapor phase reaction method of methylsilane as described above. Alternatively, silicon nitride may be formed by the PCVD method. Then, in the periphery of the second semiconductor S2 (14) side, the channel forming regions (9) and (9 ') and the insulator (16) thereon as the gate insulator (26) were formed.
The fourth semiconductor (S4) is formed so as to cover the first semiconductor S1 to the third semiconductor S3, and also the first semiconductor S1.
And the third semiconductor S3 form a diode junction.

Further, laser light is irradiated to single crystallize the fourth semiconductor S4 which becomes the channel forming region.
YAG laser (wavelength 1.06μm, repetition frequency 3KH
z, operation speed 30 cm / sec, average output 2 W, light diameter 250 μ
mφ). Then, in the fourth semiconductor S4,
Only the part irradiated with the light is annealed to be single crystal or polycrystal (average crystal grain size of 500 Å or more). At this time, the fourth semiconductor S4 has a gate insulator (2
Since it is surrounded by 6), it does not come into contact with the atmosphere, and since the anneal is performed downward from the top of the stack by the downward growth method, it has good crystallinity and can be substantially single crystallized. It was possible.

Even when polycrystallized, the laser light is irradiated to the upper part of the stack, that is, one part of the channel formation region in the channel length direction, so that crystals grow from one to the other. Thus, when the carrier moves, the grain boundary is formed in the direction parallel to the flow of the carrier so that the carrier does not cross the grain boundary. As a result, carriers do not have to cross the grain boundary without fail, and as a result, carriers can be prevented from disappearing due to the presence of recombination centers. That is, the leak current in the reverse direction can be further reduced, and the decrease in the forward current can be suppressed as compared with the single crystal. Further, since the reverse leakage current can be further reduced, high speed operation can be achieved.

It is presumed that this is a peculiar effect due to the laser annealing of the vertical channel type insulated gate field effect semiconductor device having the laminated structure. Further, in the laser annealing of this YAG laser, the region irradiated with light can be selectively made to be only the channel forming region by moving the substrate. For this reason, among the substrates having an insulating surface, the fourth one of the particularly required insulated gate field effect semiconductor devices is used.
It has a great feature that only the semiconductor S4 can be selectively made into single crystal or polycrystal.

In FIG. 1B, as the next step, the electrode contact (19) is further drilled by the third mask, and then the gate insulating film (26) on the laminated body is covered. The second conductive film (17) is 0.3 μm to 1
It was formed to a thickness of μm. This conductive film (17) is a translucent conductive film such as ITO (indium tin oxide), TiS.
A heat resistant conductive film of i ₂ , MoSi ₂ , WSi ₂ , W, Ti, Mo, Cr or the like may be used. Here, a silicon semiconductor (electric conductivity 1 (Ωcm) ⁻¹ ) doped with a large amount of P-type or N-type impurities is used.
Or 100 (Ωcm) ^-1 ) was made by the PCVD method. That is, 1% phosphorus was added to a thickness of 0.3 μm, and a microcrystalline (grain size 50Å to 300Å) non-single-crystal semiconductor was produced by the PCVD method.

Thereafter, a mask (18) was formed on the upper surface of the resist. Further, as shown in FIG. 2C, anisotropic etching was performed in the vertical direction by the fourth photolithography technique. That is, for example, CF
Reactive gases such as ₂ Cl ₂ , CF ₄ + O ₂ and HF were turned into plasma, and this plasma was applied vertically from above the substrate as shown by arrow (28). Then, when the conductor (17) is etched to a thickness of 0.3 μm on a plane, the coating of this portion is removed, but on the side surface, the total thickness of the laminate and the coating is 2 μm to 3 μm in the vertical direction. Have.
Therefore, as shown in the drawing, when anisotropic etching is performed in the vertical direction, these conductors such as the broken lines (38) and (38 ') can be left outside the region where the mask (18) is present.

As a result, the gate electrode could be selectively provided only around the side of the laminate. Furthermore, this gate electrode did not exist above the third semiconductor, and as a result, the parasitic capacitance between the third semiconductor and the gate electrode could be made substantially equal. Thus, FIG. 1C was obtained. FIG. 1C is a vertical sectional view taken along the line AA ′ in the plan view of FIG. The reference numerals correspond to each other. FIG.
As is clear from (C) and (D), the insulated gate field effect semiconductor devices (62) and (63) have two channel forming regions (9) and (9 ') and a source region. Alternatively, they have the drain region (13), the drain region or the source region (15) in common. Also, two gate electrodes (20),
It has (20 '). The electrode of the third semiconductor S3 is connected to the heat-resistant and non-reactive metal (23) (in this embodiment, as a laminated body of ITO + Cr) via the contact (19) for the multilayer film. It extends to (21). The first semiconductor has the first conductive film (12) as a lead.

That is, in the drawing, two insulated gate field effect semiconductor devices can be provided as a pair. For example, if the second semiconductor S2 between the channels of two insulated gate field effect semiconductor devices is insulative and has a width of 15 μm, it has a resistance of several tens of MΩ and is substantially independent. Become. In addition, this structure could have a completely different structure from the crystalline semiconductor. Furthermore, FIG.
In (D), another pair of insulated gate field effect semiconductor devices (61) and (64) is shown at the top of the plan view.
C-C corresponding to this insulated gate field effect semiconductor device
A vertical cross-sectional view of ′ is shown in FIG.

That is, the conductor (16) connected to the third semiconductor S3 (15) of the insulated gate field effect semiconductor device (64).
Is provided with a contact (19 ″), has a conductor (16 ′) connected to the third semiconductor S3 of the insulated gate field effect semiconductor device (61), and further has an insulated gate field effect semiconductor device (64). ) And an insulated gate field effect semiconductor device (62),
The (63) are connected to each other by a conductor (16). Between the two conductors (16) and (16 ') (58), the third semiconductor S3 thereunder is amorphous, so that it is 10 μm to 30 μm.
Since m has a sufficient insulating property, the isolation is unnecessary. Of course, it is preferable to selectively remove the third semiconductor S3 in the case of the second photomask in FIG. 1 because the isolation can be further improved.

Further, the insulated gate field effect semiconductor device according to the present invention has a channel forming region (9),
(9 '), (9 ") and (9"') contain hydrogen or fluorine by laser anneal and have a single crystal or polycrystal structure. The fourth semiconductor S4 (25) is electrically isolated by the amorphous semiconductor region (59), that is, the laser annealing is performed from the source region or drain region in the upward direction toward the channel formation region. -When irradiating with the light, only the region constituting the insulated gate field effect semiconductor device is selectively irradiated to be made single crystal or polycrystal, and the isolation region between the insulated gate field effect semiconductor devices ( In 59), it is possible to maintain the insulating property by leaving the amorphous state.

Thus, even in the case of a polycrystal, its grain boundaries (grain boundaries) can be made parallel to the direction of carrier flow, and as a result, the disappearance of carriers at the grain boundaries can be further reduced. Have. This is a great difference from the isolation structure when a semiconductor device integrated using only a single crystal semiconductor is provided. Furthermore, in this vertical channel type insulated gate field effect semiconductor device, after the gate electrode is formed, C, N, O is applied to the region of the fourth semiconductor S4 which is not covered with the gate electrode. Is also effective to form an insulated amorphous region by ion implantation or sputtering.

Further, FIG. 1 (E) is a vertical sectional view taken along line BB ′ in FIG. 1 (D). In the drawing, the lower first
It can be seen that the electrodes (12) and (12 ') are independently provided, and the upper second electrodes (16) and (23) are connected to the lead (21) and the contact (19). . Further, the amorphous semiconductor region (59) between the two insulated gate field effect semiconductor devices (63) and (64) isolates each insulated gate field effect semiconductor device. Thus, the source or drain region is the first semiconductor (13), the fourth semiconductor S4 (25) having the channel forming regions (9), (9 '), and the drain or source region is the third. It is formed by the semiconductor S3 (15), and has a laminated structure in which the gate insulator (16) is provided on the side surface of the single crystal or polycrystalline channel formation region and the gate electrodes (20) and (20 ') are provided on the outer surface thereof. An insulated gate field effect semiconductor device could be made.

The channel length is determined by the thickness of the second semiconductor S2 (14), and is generally 0.1 μm to 3 μm, and in this embodiment, 0.5 μm. Further, since the channel forming region is made single crystal or polycrystal, the cutoff peripheral portion can be set to 30 MHz to 100 MHz, for example, 60 MHz in the N channel insulated gate field effect semiconductor device. The boron semiconductor is added to the fourth semiconductor S4 in a slight amount (0.1 PPM to 10 PPM) at the time of forming the film to form an intrinsic semiconductor, P
It was effective to control the threshold voltage as a N-type semiconductor or N-type semiconductor.

Thus, as the drain region (15), the source region (12), the gate electrode (20) or (20 '), V =
We were able to obtain 5V, V _GG = 5V and operating frequency 15.5MHz. An inverter, which is a large application field of the insulated gate field effect semiconductor device of the present invention, will be described below. Figure 2
(A) And (B) is a figure which shows the inverter structure of the laminated | stacked insulated gate semiconductor device of a present Example. 3 (A) and 3 (B) are equivalent circuit diagrams of the inverter shown in FIGS. 2 (A) and 2 (B). 2A and 2B, the inverter insulated gate field effect semiconductor device corresponds to the equivalent circuits of FIGS. 3A and 3B. The driver (61) uses the insulated gate field effect semiconductor device on the left side and the insulated gate field effect semiconductor device on the right side for the load. In FIG. 3 (A), an enhancement type in which the gate electrode (20) of the _load and V _DD (65) are continuous, and in FIG. 2 (B), the output and the gate electrode (20) are continuous. 1 shows a depletion type insulated gate field effect semiconductor device.

Further, the output of this inverter is composed of (66), and the two insulated gate field effect semiconductor devices (61) and (64) on this substrate are not separated from each other and are the same semiconductor block (13). , (14), (15) are combined and provided. The equivalent circuit of the inverter of FIG. 2 (A) is shown in FIG. 3 (A), and the insulated gate field effect semiconductor device (61), (64) in FIG. 1 (D).
The upper electrodes corresponding to are made independent as two insulated gate type field effect semiconductor devices (19 ″) and (19). Thus, one insulated gate type field effect semiconductor device (64) is provided.
(Road) is an electrode (19), a drain region (15), a channel forming region (9), a source region (13), an electrode (12), that is, an output (66) and another insulated gate type electric field. Effect Semiconductor device (driver) (61) electrode (12 '), drain region (13), channel forming region (9 "), source region (1)
5), it becomes possible to provide as an electrode (68).

As a result, the two insulated gate field effect semiconductor devices are connected to one of the first semiconductor S1 to the third semiconductor S3.
It was possible to make an enhancement type inverter by integrating with the block. 2B shows an equivalent circuit of FIG. 3A, the depletion type inverter
It is a composition of data. That is, FIG. 2B shows a case where the lower electrode is divided into two. One insulated gate field effect semiconductor device B - V _DD (6 in de (64)
5), lower electrode (12), drain region (13), channel forming region (9), source region (15), electrode (19), ie output (66), other insulated gate field effect Semiconductor device (driver), drain region (15) in (61), channel forming region (9), source region (13), electrode (12),
V _SS (68), input (67) to gate electrode (20 ')
The output (66) was extracted from the third semiconductor S3.

As described above, the present invention is a vertical channel type, and enables high-speed operation by forming the channel forming region into a single crystal or a polycrystalline structure in which grain boundaries do not cross the flow of carriers. Furthermore, the second
Since the semiconductor S2 of FIG. 3 is insulative, there is no short circuit even if a large voltage of 30V to 100V is applied between the first semiconductor S1 and the third semiconductor S3. Further, even if either the first semiconductor S1 or the third semiconductor S3 acts as the drain region, the outside thereof is insulated, so it can be said that it is the most ideal insulated gate field effect semiconductor device. Furthermore, since the second semiconductor S2 is also insulating under the channel formation region of the fourth semiconductor S4, two insulated gate field effect semiconductor devices that contribute to the improvement of frequency characteristics can be simultaneously formed as a pair. The number of manufacturing masks required is five, and many features such as no need for mask precision can be provided in addition to the extremely short channel length of 0.2 μm to 1 μm.

In the insulated gate field effect semiconductor device of the present invention, the reverse leak is obtained by changing the first semiconductor S1 or the third semiconductor S3 as shown in FIG. 1 into SixC _CX (0 <x <1.
For example, by setting x = 0.2), the second
By making the semiconductor S2 of the present invention an insulator, the impurities of the first semiconductor S1 and the third semiconductor S3 are less likely to flow into the second semiconductor S2, and this N--I junction or P--I junction The negative value was 10 nA / cm ² or less even when 10 V was applied in the reverse direction. Furthermore, since the metal of the electrode easily mixes into the non-single-crystal first semiconductor S1 and the third semiconductor S3 during operation at a high temperature and is liable to be defective, the side close to this electrode is
SixC _1-X (0 <x <1 For example, x = 0.2).
As a result, the insulated gate field effect semiconductor device of this example was operated at 150 ° C. for 1000 hours, but no malfunction occurred.
It was not seen even after evaluating 1000 elements. This is an extremely high reliability, considering that if the first semiconductor S1 or the third semiconductor S3 is formed only of amorphous silicon in close contact with this electrode, it cannot withstand 10 hours at 150 ° C. .

Further, because of such a stacked type insulated gate field effect semiconductor device, a plurality of insulated gate field effect semiconductor devices are provided on a substrate, particularly on an insulating substrate, without using a highly accurate photolithography technique as in the prior art. It became possible to make resistors and capacitors. Then, it has become possible to develop it into a solid-state display such as a liquid crystal display or a chromic display. The non-single crystal semiconductor in the present invention is silicon, germanium or silicon carbide (Si
xC _1-X 0 <x <1), and silicon carbide or silicon nitride was used as the insulator.

[0032]

According to the present invention, the channel forming region is annealed so as to have a grain boundary in which carriers do not cross the grain boundary, thereby forming a polycrystalline structure. Therefore, the insulated gate field effect semiconductor device of the present invention can improve the characteristics at high frequencies. According to the present invention, when the channel formation region is annealed, it is transformed so that it does not cross the grain boundary in the direction of carrier flow, so that the disappearance of carriers due to recombination centers existing in the grain boundary can be reduced. it can. According to the present invention, the channel formation region is annealed after the insulating gate film is formed on the fourth semiconductor. Therefore, the gate insulation film does not expose the channel formation region to the atmosphere, and thus the crystal structure with good crystallinity is obtained. Can be obtained.

[Brief description of drawings]

1A to 1C are vertical cross-sectional views of a stacked insulated gate field effect semiconductor device of this embodiment.

1D and 1E are vertical cross-sectional views of the stacked insulated gate field effect semiconductor device according to the present embodiment.

2A and 2B are diagrams showing an inverter structure of a stacked insulated gate semiconductor device of this embodiment.

3A and 3B are equivalent circuit diagrams of the inverters shown in FIGS. 2A and 2B.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2, 12 ... First conductive film 3, 13 ... Non-single-crystal semiconductor (first semiconductor S1) 4, 14 ... Semiconductor or insulator (second semiconductor or Insulator S2) 5, 15 ... Third semiconductor S3 6 ... Heat-resistant metal conductor 7 ... Silicon oxide film 9, 9 '... Channel formation region 20, 20' ... Gate electrode 23 ... Conductor 24 ... Insulator 25 ... Fourth semiconductor (S4) 26 ... Gate insulator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M H01L 29/78 618 Z

Claims (1)

[Claims] 1. A first electrode formed on a substrate, a first semiconductor formed on the first electrode, and a second semiconductor or insulator formed on the first semiconductor. And a third semiconductor formed on the second semiconductor or the insulator, a second electrode formed on the third semiconductor, and at least the first to third semiconductors are substantially the same. A laminated body laminated in a shape, and a single crystal semiconductor provided adjacent to a side portion of the laminated body.
Insulated gate type electric field composed of a fourth semiconductor composed of a semi-amorphous semiconductor having a property between a non-single crystal semiconductor and a gate electrode provided on the fourth semiconductor via a gate insulating film. In the effect semiconductor device, the first and third semiconductors form a source region and a drain region, and the channel formation region formed in the fourth semiconductor near the end of the source region or the drain region is the channel formation region. An insulated gate field effect semiconductor device having a polycrystalline structure modified so that carriers moving in a region do not cross the grain boundary.