JPS5828873A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device wherein an evaporation-stack-formed NSCS by a plasma CVD method, etc. is formed on a substrate by utilizing its characteristic and which is more excellent than a conventional insulating gate type field effect semiconductor device in facilitations of manufacture and integration, further in a low voltage and a high speed response. CONSTITUTION:To constitute a channel forming region on the substrate 1, an NSCS53 (I layer) is formed 0.1-1mum thick, a mask 21 is formed on the upper surface thereof, and an N<+> type NSCS45 and a P type NSCS25 are likewise selectively manufactured 0.1-1mum thick. Next, oxygen is implanted into this I layer by an ion implantation resulting in a ban-isolation region 53. Subsequently, after removing the mask 21 by a lift-off method, a field inulator 31 is manufactured. Further, after manufacturing gate insulators 33, 43, an aperture 32 of an electrode, and gate electrodes 35, 45 and a lead 34 are provided.

Description

Detailed Description of the Invention The present invention (amorphous (non-112if type, non-crystalline) on a d-substrate, semi-amorphous (semi-amorphous) having microcrystallinity in the range order of 5 to 200 A) /
Koni 1. A semiconductor having a polycrystalline structure, in particular containing no hydrogen or halogen elements such as fluorine or I'flj.
．． Insulated gate field effect semiconductor device using alkali gold such as lithium, sodium or potassium (N5C8) with a 01 to 10 molar content (N5C8). I
'J method.

In the present invention, N5O8 is deposited on such a substrate by plasma CVR+ method 1, with a ratio of 1/1 to +1'1, and the nli structure is 1.・In terms of its manufacturing method, it is easier to manufacture, easier to process, and has superior low voltage and high-speed response compared to conventional insulated gate field effect semiconductor devices (hereinafter simply referred to as TOFETs).

The present invention has a flat surface and N5 in its manufacturing method.
For example, glass substrates, ceramics, Blame's Y ceramics, stainless steel, etc. are used.

Regarding the N S OS formed on the rough surface, one ridge is also important for control and the necessary channel formation region [~, after forming this l'l S OS, the gate insulating material was f171 ni gate. It has the feature of forming an electrode. Also, impurities that make up the source and drain)
'r is a semiconductor h having a conductivity type of P t i
:I can be achieved by selectively using a lift-off method or a plasma OVD method. In this semiconductor, there is no conductor or metal on the σ1i of the N5O8 which forms the active channel forming region 411, which has a softer dimension than the II-crystal, and here only an insulator, especially silicon oxide, is used. Another feature of the present invention is that the reliability in this area is improved by bringing the two parts into contact with each other.

Tree brother 1y, 1h, ASv: f'knee 'tJ: s
The AS is manufactured by the N5C3 method (both AS and SAS are plasma OV), which is used in iJ's main technology and 17.

Regarding this 5llll/, patent 1+;:[i (semi-amorphous semiconductor patent application 1982
-065826056°4. :', O exit 1j'Jl z
! l”I”j! ! 1975-I20:522S55
11. ing.

In other words, if a semiconductor, for example, f1 element and a half, ... +7 body, J1'l filamentary crystal, is amorphous (
Even if it is a glass substrate of 1.l); ) 1 (, I gained one energy!) 7 points] X 16-3 X 1
．． 6 JyoQ (: l11)' and these ('eJ,
Junior high school 1M, I Shinazuki Saku'' stone rt 1 piece 1. /2~1. /]
The inventor has experimentally found that -0 and extremely low / Kogyu 1 and Enmi are I' 1~! Ilj is brought out/
This is it.

J to the present invention, 1. of such fE AS. ,+j group 1i
' 11 This is an example of a return to T.

In addition, the four wooden brothers are A 3-sun 1 Is AS is the conventionally known 1, Iil model J Q F II: T-no-tome" construction, that is, the vertical turn shown in Figure 1 4'i') clear In this case, it is the original AS well (l-JSAS does not have the thing 1'l and jjj77 is added to the special PI "?:i") 1(, it is empty).

In other words, 11 bodies were used for conventional amorphous materials.
As an IGFET, it is like the one shown in Figure 1. l
Structures having :/l are known. In Fig. 1, a gate electrode (3), (]I1
It is made of heat-resistant material such as molybdenum. Further, a gate insulating film 0]) is formed using silicon oxide at an angle of 0.1 to 0.57+ by the OVD method. Next, AS is formed on this upper surface, and only the channel type gates (5) and (1,0) are selectively etched. Furthermore, the N-type semiconductor layers (6) and (7) in the N-channel TavybT0 are selectively formed using the cut-out etch method, and the P-channel! 1ijj I Glc E
For T(2), aluminum foil [formed by vacuum evaporation method and selectively etched to form source (9) and drain (8)
As shown in Figure 11 (07MO3・FF F, T have been completed).

In this structure, since the gate insulator (11) is formed by the OVD method, it is dense and dense, and as a result, the gate electrode (3) and the semiconductor (5) are easily short-circuited. It must be thicker than 0.3μ. As a result, the gate voltage becomes a large voltage of 20 to 60 V, and low voltage driving of so-called -15 to 5 .mu. is completely impossible.

It is necessary to precisely align both ends of the gate electrode (lυ), both ends of the semiconductor (5), and one end of the source (6) and drain ('7).However, since there are irregularities on the substrate, 'AI!4:
Alignment is impossible at high uj degrees of 71 or more.

As a result, 20-7. Is it possible to create a tolerance for Olz? Therefore, the tunnel voltage becomes as high as 50 to 70 V, and the low pivoting of OV is completely impossible.

Furthermore, at the entrance surface 0 of the semi-i7% body (5) that is in contact with the so-called channel forming region, which has structural sensitivity, P-type or N-type conductivity /li',! The source (6) and drain ('7) will be short-circuited unless it is etched away by photon etching. 1～deshi”・U.

However, since this has the same main component as the lower half-H form (5), selective etching becomes extremely difficult.

Furthermore, even if the back side is completed in the i'f? I
It was completely impractical for T9. Since the use of such a structure results in 'r:1; total sensitivity as a semiconductor, a solution to the structure of a flattened device that eliminates this drawback has been awaited.

The present invention uses NSC! in the channel forming region! S is used, and its lower, upper, and side parts are all insulating or highly impurity-concentrated Jf.
It is covered with a semiconductor having 1.51 and is characterized in that it also controls gates by utilizing the umezuke sensitivity of this semiconductor. Therefore, instead of the conventional 40~SOV drive, it is now possible to drive 5~IOV for both gate '11L voltage and drain voltage, and furthermore, IjC1-, 5
V drive also has the characteristic that it is essentially possible in its lj'/structure.

Furthermore, in Figure 1, the gate electrode (4), the source (6), and the drain (1) are made using photomasks four times.
Eyes, 3! ：3.1・L Old system, if you try to make the lead wiring on the board with a metal with low resistance, you will need two photomasks on the top surface, making it a total of 6 times, but it is still a single layer. It had the disadvantage that only wiring could be done.

The present invention not only eliminates the above-mentioned drawbacks, but also facilitates integration into a semiconductor device, facilitates the integration of other important elements such as a resistor and a capacitor, and furthermore allows the capacitor element to be integrated with a liquid crystal. By doing so, the panel display ξ can be made into a 17-sided cathode ray tube compared to other large 71. ．． It is said to be 9 signs.

Hereinafter, the implementation of the present invention will be explained according to the drawings.

Embodiment" FIG. 2 shows the l0FET of the present invention, 1. − J: Bisono・
FIG. 1 is a vertical sectional view showing the process.

21≧i (A)...The size of the glass that is an insulating and transparent substrate on the substrate (1) side/this←I: ')
, N5 to stainless steel-1- which is a reissue of Ij-Electric 1'1
An O8 film was formed to a thickness of O01 to Lp by a plasma vapor phase method. The structure of N5C8 is made by diluting silane (mono-silane) or silicon fluoride with helium or hydrogen and reacting it in a reactor at 0.01 to 10 torr, e.g. 0°31; It was introduced in moreover]
For example, a DC 4-frequency wave (500 KHz ~
50MHz e.g. 13°56Mnz)-j or microwave (:1~]-0G Hz e.g. 2°4.5 (1,I
- Electromagnetic energy of TZ) is applied with an output of 30 to 200 W to perform glow discharge or arc discharge, and transform these reactive gases and carrier gases into plasma, activate, decompose, and react, and place them on the substrate. An N5C3 film was then formed. Depending on the electromagnetic energy applied to the reactive gas, the N5OS film becomes AS at 5 to 20 W, and SA at 60 to 200 W.
, FJ, and at 20 to 60 W, the mixed state was intermediate between them. Add 60 to 200W and further increase the substrate heating temperature to 4
50 to '1000, it became PO2. 600～
With 'yoo'a, P OS can be achieved without adding electromagnetic energy.
Became.

At the time of producing this N5O8, hydrogen and halogen elements constituting the reactive gas were added at a concentration of 0.01 to ]-0 molar to act as a recombination center neutralizing agent.

``The fact that this SAS has microcrystallinity on the order of a short range of 5 to 200 A is a major crystallographic difference from AS which does not have such crystallinity. Furthermore, 0.01 to 5 mole of a recombination center neutralizing agent is added to these materials using a halogen element such as hydrogen or fluorine, which neutralizes the dangling bonds of silicon, which is a semiconductor material. Furthermore, this 5A
In order to neutralize the unpaired bonds of EI which cannot be offset by these neutralizing agents to a concentration of ], 0 to], OCm, an alkali metal such as lithium, sodium or potassium is added to 10 to 1. The density of recombination centers may be further reduced by a sub-door.

This S A S dark conductivity I
1.0 (xc m) and 1.0 (xc m) of A S. O~
], O(xc m)'. Likelihood conductivity AM] −
Under the conditions of SAS, IX], O~8X]-O
(fLc m)-9-.

experimentally, and A S @ 10-3 X ],
It has O(xc m). The key feature of the present invention is that this value can be used appropriately in practice.

Therefore, this SAS is for high-frequency operation, 17, l~S is for DC-like low-frequency minute signal processing, and 1 is for Sakikawa's N.
It can be used for OFF processing.

Furthermore, in FIG. 2(A), the mask H was selectively formed to have a thickness of 1 to 5/7, and the first mask (1) was used here. This was constructed using the reduced pressure plasma vapor phase method as shown in the drawings.
In the FET region (c), the source region QQ1
A drain region (c) and a channel forming region Q◇ are formed.

After this '-1m again A 8 cm id', SA
SX(+-o) iJ: An N-type semiconductor layer (c) was formed to a thickness of 0.1 to 1 μm in the same manner as the semiconductor layer 00. At this time N''!
, or to make a P-channel I .2
~2% was added at the same time as the film was formed. Thus, Figure 1 (
A) was obtained.

In FIG. 2(B), a mask H having the structure of FIG. 1(A) was immersed in an etching solution with light application of ultrasonic waves to dissolve it.

Then, a pair is formed in the regions QQ and (A), and one conductivity type (
Semiconductor layers (c) and (30) are formed as a source and a drain. Furthermore, field insulator (3) is placed on this top surface.
0,] to 1 to oxidize element or polyimide resin film
FIG. 2 was obtained by forming the film to a thickness of μ.

Next, the field insulator in the area corresponding to the region Q→ and the electrode contact hole (32) was selectively removed using a second photomask (2).

After that, the gate insulator (33) is removed by plasma oxidation method.
It was formed to a thickness of 0 to 200 OA. In other words, oxygen or oxidizing gas is heated at 2°45G, Hz (output 100-500W
) is decomposed and activated by microwaves, and this activation I~
The substrate was placed in an oxidizing gas at a temperature of 300-500'O, and there was a chemical substance on the surface! 11 to 1 year 0
When 0 was silicon, a phosphorus oxide film was fabricated.

A nitriding gas such as ammonia may be used instead of the oxidizing gas. Of course, even if a film of silicon oxide, silicon nitride, etc. is formed to a thickness of 300 to 200 OA using the plasma vapor phase method, it is impossible. It is effective to form a semiconductor layer or a metal cluster 1/co(ゎ1, e,) film and use it as a charge trapping center.

A simple MNO8 structure may also be used. These are this IGFE
The present invention has the freedom 1')1 determined by the application of T.

After forming the gate insulator (33) in this manner, the photomask (3) described later was provided with a "2 resource 1: saw (open to the drain in the drawing)" (:52), and then a back electrode (35). ), (34) The lead (36) is fabricated using the fourth photomask with a metal film (~).

For these electrodes and lead wires, it is effective to use a method using the ``gamma vacuum deposition method'' and photo-etching method of aluminum tongue, or a PP electrolytic plating method and four-etching method of metal such as nickel. .

In order to prevent these metals from seeping into the underlying insulating film and semiconductor layer, it was preferable to use a combination of lift-off method and electroless plating method. That is, in FIG. 2(D), the electrode leads (35) (36
) is not provided, a mask resist is provided in the same manner as in FIG. , is a method of removing.

In the manner described above, IG, F'ET having the +i & structure in the vertical cross-sectional view shown in FIG. 2(D) was obtained. At this time, the pair of impurity regions (c) and (30) function as a source and a drain, and the channel forming region can have a channel length of 0.3 to 20lt, especially 2 to 3μ,
Compared to the structure shown in FIG. 1 using the conventional AS, it was possible to obtain a frequency response as high as 10' to 1-0 times.

Furthermore, the driving voltage is 05 to IOV, typically 5 to 10
■It is possible to lower the gate to 1/2 to 115 times lower than the conventional one and is covered with a gate insulator (33) and formed on a thin substrate (1) with a lower electrode, especially for channel formation. Region d, all of which have an insulating film on the upper surface, lower surface, and side surfaces;
It is covered with semiconductor and will not deteriorate due to exposure to the atmosphere.

Example 2 FIG. 3 is a vertical sectional view showing another embodiment of the present invention.

The drawing shows an O/MO8 (complementary insulated gate ζ11 field effect semiconductor device) with N-channel I O]r F, T
(The 4υ and P channel ■avgT (42) can be combined and integrated on the same substrate (1).

In this example, the parts not specified were manufactured in the same manner as in Example 1.

In drawing (A), in order to form a channel forming region in the soil of the substrate (1), an intrinsic size or substantially intrinsic N5O8 (5
3) A layer (hereinafter simply referred to as one layer) was formed to a thickness of 0°] to 'll-/1. Furthermore, a mask H is formed on these two sides,
N” type N5O8 (45), P+ type NFIO8 (c)
were similarly produced selectively to a thickness of O01 to 1μ.

In the drawing, in order to promote isolation in the first layer of field insulation, oxygen is implanted into the first layer using ion implantation at a concentration of 10 to 0, and this region is exposed to high energy. The insulating film has a band 11''. Thus, an isolation region (5→) was established.

Next, as shown in FIG. 3(B), after removing the mask t21) by a lift-off method, the field insulator (31) is coated with silicon oxide by a plasma CVD method to a thickness of 0° to 211°.
It was manufactured using a coating method using polyimide resin.

Furthermore, gate insulators (33) and (43) were prepared in the same manner as in Example 1, and then electrode openings (32) were formed.
) was I4I.

Furthermore, as shown in FIG. 3(D), the gate electrode is
) (45) and leads (34) were provided to fabricate a composite semiconductor device having an f8 grandchild type inverter structure.

As is clear from the drawing, all steps in FIG. 3(D) are performed in the order of lamination from bottom to top, and there is no problem with multilayer wiring. Two drains (S
O) (39) can be made, and has an extremely convenient structure when an integrated structure is made by laminating them in a plane.

Example 3 FIG. 4(A) shows a vertical sectional view of this embodiment.

In the drawing, in addition to the IGFET (50), a single-layer resistor (5) and a capacitor (52) are provided.

In the drawing, IGFET (50) is connected to ↑ source (2 (J)
, a drain (30), a gate insulator (33), and a gate electrode (35) were manufactured using the same manufacturing process as in Example 1. At the same time, the resistor (51) is provided in one layer (b6) under the field insulator (31) between one electrode (30) and the other electrode (55). In addition, a capacitor (52) I (one electrode (59), a dielectric (57), and an upper 1+111 electrode (5B) are provided, and the dielectric (57) is connected to the gate insulator 03) and the upper electrode (5B).
) is the same as Gate Den/i-Yu (35) 4'' is the same as 71-1 by Sho 1! It is made of.

Thus, a feature of the present invention is that not only the IGFET but also other elements can be formed on the same substrate based on the design specifications of the mask without changing the process.

Example 4 and (7) Examples are the substrate (1) soil LZtlWl f)
IGFET (50) (5Φ) is arranged in a multi-IJ rack, a capacitor using liquid crystal is provided on the source side, and a planar type device is provided.

FIG. 4(B) shows a vertical sectional view of a part of the semiconductor device.

In the drawing, on the substrate (1) are IG, FET (50), its source (c), drain (30), and gate insulator (
33), a gate electrode (35) is provided, and a drain (33) is provided.
0), one capacitor is the lower side voltage* (59), ,
It consists of a dielectric ("") and an upper electrode (58). In parallel, there is another capacitor contact ('72), a lower electrode (6υ), a liquid crystal dielectric (63) and a side electrode (6υ).
2) Consists of a translucent substrate (64).

Light enters from the substrate (64), a part of which is reflected by the liquid crystal part, and other parts are created, and the contrast constitutes brightness and darkness. This is 530X530 or mXn (m, n,
I created an image display device by creating a matrix (arbitrary constant).l01j'ET
(5 to capacitor (5 small is arranged in the product).

The brightness and darkness of this liquid crystal is determined by matrix elements.
E Provided by controlling 'I' to ON and OFF'F. This matrix structure is
, ';:4'',' 4 IGFET shown in Figure (A)
For example, a tag and driver may be provided.

It is clear from the explanation of ``111'' that this redundant work G
Obtained FET and its manufacturing method/ζ.

The present invention has been mainly described with respect to silicon. But S1. Cl-
4(0<x<1), S i,N,-4(0<
Even if x < 4-), the small germanium, l1l
-V compounds may also be used.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a conventional semiconductor device; FIGS. 2 and 3 are vertical cross-sectional views 1r11 showing a semiconductor device 11aJ of the present invention and its manufacturing process. FIG. 4 shows a vertical sectional view of another semiconductor device of the present invention. ″+1'i1'l°out 19 [i person! 5152 Tate 3 Ward ¥ L Prisoner

Claims (1)

[Claims] 1. A non-single crystal semiconductor on a substrate, a pair of impurities spaced apart from each other on the semiconductor, and a gate insulator and the insulator on the channel forming region of the semiconductor and between the impurity regions. A semiconductor device characterized in that a gate electrode is provided on an object. 2. The step of forming a non-single-crystal semiconductor on the substrate includes the step of forming a semiconductor layer of 14-voltage type X on the non-single-crystal semiconductor layer, and removing the mask and the semiconductor layer around the outside of the mask. and a step of forming a gate insulator on the channel forming region and the pair of impurity layers or on the side surfaces, and a gate electrode on the k'k vIJ. A method for manufacturing a semiconductor device.