JPH06250218A - Production of liquid crystal display device - Google Patents
Production of liquid crystal display deviceInfo
- Publication number
- JPH06250218A JPH06250218A JP3628393A JP3628393A JPH06250218A JP H06250218 A JPH06250218 A JP H06250218A JP 3628393 A JP3628393 A JP 3628393A JP 3628393 A JP3628393 A JP 3628393A JP H06250218 A JPH06250218 A JP H06250218A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- array substrate
- tft
- display device
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 238000000576 coating method Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims abstract description 4
- 239000011347 resin Substances 0.000 claims description 13
- 229920005989 resin Polymers 0.000 claims description 13
- 238000004140 cleaning Methods 0.000 claims description 11
- 239000003960 organic solvent Substances 0.000 claims description 11
- 238000005406 washing Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 238000012856 packing Methods 0.000 abstract 2
- 239000003795 chemical substances by application Substances 0.000 abstract 1
- 239000002904 solvent Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 230000014759 maintenance of location Effects 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は液晶表示装置の製造方法
に係り、特にスイッチング機能を呈する LDD構造型薄膜
トランジスタ素子の OFF領域でのリーク電流を低減させ
ることによって、データの保持特性を向上させた液晶表
示装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly to improving data retention characteristics by reducing a leak current in an OFF region of an LDD structure type thin film transistor element exhibiting a switching function. The present invention relates to a method for manufacturing a liquid crystal display device.
【０００２】[0002]
【従来の技術】液晶表示装置の高速化や高品位化の実現
を目指して、表示画素ごとにスイッチング用の薄膜トラ
ンジスタ（以下、 TFTと略称）を設けたいわゆるアクテ
ィブマトリックス型液晶表示装置（以下 LCDと略称）が
開発され、実用化の主流となっている。そして、このス
イッチング用 TFTとしては、一般に、非晶質シリコン
（ａ−Si）、もしくは多結晶シリコン（Poly−Si）を素
材とした TFTが使用されている。特に、Poly−Siはいわ
ゆる移動度が大きく、かつ周辺駆動回路を同一基板上に
一体的に形成し得るため、小形化および高精細な表示が
要求される液晶表示装置に好適視されている。2. Description of the Related Art In order to realize high-speed and high-quality liquid crystal display devices, so-called active matrix liquid crystal display devices (hereinafter referred to as LCDs) in which a switching thin film transistor (hereinafter abbreviated as TFT) is provided for each display pixel. Abbreviation) has been developed and has become the mainstream of practical application. A TFT made of amorphous silicon (a-Si) or polycrystalline silicon (Poly-Si) is generally used as the switching TFT. In particular, since Poly-Si has a large so-called mobility and a peripheral driving circuit can be integrally formed on the same substrate, it is favorably regarded as a liquid crystal display device that requires miniaturization and high-definition display.
【０００３】ところで、前記 TFTを液晶表示装置に応用
する場合、画素中で液晶への電圧印加用の画素部 TFT
と、この画素部 TFTを駆動する駆動回路部のトランジス
タとして使用される。しかしながら、前記使用態様にお
いて、特に表示画素部に使用するPoly−Si系 TFTの場合
は、 OFF領域状態で発生するリーク電流が数100 nA程度
と大きく、この OFF領域でのリーク電流が、画素容量に
書き込まれたデータの保持特性を劣化させるという問題
がある。つまり、アクティブマトリックス型 LCDの場合
は、マトリックス状に、順次データを対応する各表示画
素の駆動素子ごとに書き込んで行くため、 TFTが OFF状
態にある時間は、ON状態にある時間に比べて遥かに長
く、その間データは保持されていなければならない。し
かし、前記画素容量は通常 1pF程度と小さいので、前記
TFTの OFF状態において僅かでもリーク電流が流れる
と、ドレイン電極の電位、すなわち液晶に印加されてい
る電圧が急激にソース電極の電位に近付き、前記書き込
みされたデータの保持ができなくなり、表示する画質の
低下（悪化）を招来する。このリーク電流の問題は、特
に画素部の TFTにおいて重要であり、前記 OFF状態（領
域）でのリーク電流の可及的な低減が望まれる。By the way, when the TFT is applied to a liquid crystal display device, a pixel portion TFT for applying a voltage to a liquid crystal in a pixel is used.
And is used as a transistor in a drive circuit unit that drives this pixel unit TFT. However, in the above usage mode, particularly in the case of a Poly-Si TFT used in the display pixel section, the leak current generated in the OFF region is as large as several 100 nA, and the leak current in this OFF region is There is a problem that the retention characteristic of the data written in is deteriorated. In other words, in the case of the active matrix LCD, since the data is sequentially written in a matrix for each drive element of each corresponding display pixel, the time when the TFT is in the OFF state is far longer than the time when it is in the ON state. The data must be held for a long time. However, since the pixel capacitance is usually as small as about 1 pF,
If even a small leak current flows in the OFF state of the TFT, the potential of the drain electrode, that is, the voltage applied to the liquid crystal, suddenly approaches the potential of the source electrode, and the written data cannot be retained and the displayed image quality is improved. Decrease (deteriorate). The problem of the leak current is particularly important in the TFT of the pixel portion, and it is desired to reduce the leak current in the OFF state (region) as much as possible.
【０００４】そして、前記リーク電流発生の原因として
は、次のような理由によると考えられてきた。第１に
は、ゲート・ドレイン間に電場が集中するために、ドレ
イン近傍で起こる電界集中によって生じるトンネル電流
が挙げられ、第２には、活性層中に存在する未結合手で
ある結晶欠陥を介することで、熱などによって励起され
たホールの流れで生じる電流が挙げられる。このような
原因・考察への対応策として、すなわち画素部の TFTに
おける OFF領域のリーク電流を低減するため、前者につ
いてはドレイン近傍部の電界を緩和する LDD構造化が、
また後者については未結合手のターミネーターとして作
用する水素を添加する水素パッシベーション処理がそれ
ぞれ試みられている。The cause of the leak current has been considered to be as follows. First, there is a tunnel current caused by electric field concentration near the drain because the electric field is concentrated between the gate and drain. Secondly, crystal defects which are dangling bonds existing in the active layer are considered. An electric current generated by the flow of holes excited by heat or the like can be given. As a countermeasure against such causes / considerations, that is, in order to reduce the leak current in the OFF region in the TFT of the pixel part, in the former case, LDD structuring that relaxes the electric field near the drain is
Further, for the latter, hydrogen passivation treatment of adding hydrogen acting as a terminator of unbonded hands has been attempted.
【０００５】[0005]
【発明が解決しようとする課題】前記 LDD構造の採用、
および水素パッシベーションの適用で、たとえば図３
(a)に電気的特性示すごとく、 TFTにおける OFF領域で
発生するリーク電流の絶対値は低減できたが、データ保
持能力が低下しないレベルまで、 OFF領域で発生するリ
ーク電流を低減し得ないのが実情である。つまり、Poly
−Siなどを活性層とした場合は、一般的に知られている
MOS型に準じて（ MOS型の場合と同一視した考察に基づ
いて） LDD構造としても、前記図３ (a),(b)に示すごと
く、なお、リーク電流の十分な低減を達成し得ないのが
実情である。ここで、図３ (a)はPoly−Si系 TFTのゲー
ト電圧に対するドレイン電流値を、図３ (b)はPoly−Si
系 TFTのゲート電圧に対するゲート電流値をそれぞれ示
し、また曲線ａ，ｂ，ｃ，ｄは、ドレイン電圧 Dv を
0.05V， 5.05V，10.05V，15.05Vの場合である。Adopting the LDD structure,
And the application of hydrogen passivation, for example in FIG.
As shown in the electrical characteristics in (a), the absolute value of the leakage current generated in the OFF region of the TFT could be reduced, but the leakage current generated in the OFF region could not be reduced to a level where the data retention capacity did not decrease. Is the reality. That is, Poly
-When using Si as the active layer, it is generally known.
According to the MOS type (based on the same consideration as the MOS type), the LDD structure can still achieve a sufficient reduction of the leakage current as shown in FIGS. 3 (a) and 3 (b). The reality is that there is none. Here, Fig. 3 (a) shows the drain current value with respect to the gate voltage of the Poly-Si TFT, and Fig. 3 (b) shows the Poly-Si TFT.
Shows the gate current value with respect to the gate voltage of the system TFT, and the curves a, b, c and d show the drain voltage D v .
It is the case of 0.05V, 5.05V, 10.05V, 15.05V.
【０００６】前記対応策を採った後においてもなお認め
られるドレインリーク電流の発生は、上記従来考察・想
定されていた原因と異なり、配線形成工程後の組み立て
（製造）過程において、表面に吸着した水分を導電体と
して流れる表面リーク電流と考えられる。このことは、
ゲート電圧に対するゲート電流値の測定・評価におい
て、前記対応策を採ったか否かに拘らず、同程度のリー
ク電流（数10pA程度）が依然と流れていることからも裏
付けられる。The occurrence of the drain leak current, which is still recognized even after the above countermeasure is taken, is different from the cause which has been considered and assumed in the past, and is adsorbed on the surface in the assembly (manufacturing) process after the wiring forming process. It is considered to be a surface leak current that flows water as a conductor. This is
This is supported by the fact that the same level of leakage current (several tens of pA) still flows in the measurement / evaluation of the gate current value with respect to the gate voltage, regardless of whether or not the above countermeasure is taken.
【０００７】本発明は上記事情に対処してなされもの
で、 LDD構造型 TFTの OFF領域におけるドレインリーク
電流を低減し得るばかりでなく、リーク電流をデータ保
持能力が損なわれないレベルまで確実に低減させた LDD
構造型 TFTを具備し、常時良好な画質の表示が可能な液
晶表示装置の製造方法の提供を目的とする。The present invention has been made in consideration of the above circumstances and not only can reduce the drain leakage current in the OFF region of the LDD structure type TFT, but also surely reduce the leakage current to a level at which the data retention capacity is not impaired. Let LDD
An object of the present invention is to provide a manufacturing method of a liquid crystal display device which is provided with a structure type TFT and can always display a good image quality.
【０００８】[0008]
【課題を解決するための手段】本発明の液晶表示装置の
製造方法は、 LDD構造の薄膜トランジスタ素子および前
記薄膜トランジスタ素子に接続された画素電極を備えた
薄膜トランジスタアレイ基板と、前記薄膜トランジスタ
アレイ基板の画素電極に対向する対向電極を備えた対向
基板とを、前記画素電極および対向電極を対向させ、か
つ液晶材料を充填・挟持する液密な空間領域を形成させ
て封止・一体化する工程、および前記薄膜トランジスタ
アレイ基板および対向基板で形成する液密な空間領域に
液晶材料を充填・挟持させる工程を具備して成る液晶表
示装置の製造方法において、前記薄膜トランジスタアレ
イ基板面に、予め感光性樹脂の塗布処理および有機溶剤
による洗浄処理を施しておくことを特徴とする。A method of manufacturing a liquid crystal display device according to the present invention comprises a thin film transistor array substrate having an LDD structure thin film transistor element and a pixel electrode connected to the thin film transistor element, and a pixel electrode of the thin film transistor array substrate. And a counter substrate provided with a counter electrode facing each other, forming a liquid-tight space region in which the pixel electrode and the counter electrode face each other and filling and sandwiching a liquid crystal material, and sealing and unifying the liquid crystal material. In a method of manufacturing a liquid crystal display device, which comprises a step of filling and sandwiching a liquid crystal material in a liquid-tight space area formed by a thin film transistor array substrate and a counter substrate, a process of applying a photosensitive resin in advance to the surface of the thin film transistor array substrate. And a cleaning treatment with an organic solvent.
【０００９】なお、本発明において、薄膜トランジスタ
アレイ基板面に塗布処理する感光性樹脂としては、フォ
トエングレービングプロセス(PEP）で使用されるフォト
レジストなどが挙げられ、一般的に、塗膜も〜 1μm 程
度でよい。一方、感光性樹脂の塗布膜形成後、洗浄処理
する有機溶剤として、たとえばたとえばアセトン，エタ
ノール，レジスト用シンナーなどが挙げられる。そし
て、前記感光性樹脂の塗布膜形成後の洗浄処理は、有機
溶剤による塗布膜の溶解除去と洗浄処理とを同時に行っ
てもよいし、形成した塗布膜を剥離した後、その剥離面
を所要の有機溶剤で洗浄処理するという２段的な処理で
あってもよい。In the present invention, examples of the photosensitive resin applied to the surface of the thin film transistor array substrate include photoresists used in the photoengraving process (PEP). About 1 μm is enough. On the other hand, as the organic solvent to be washed after forming the coating film of the photosensitive resin, for example, acetone, ethanol, thinner for resist and the like can be mentioned. The cleaning treatment after forming the coating film of the photosensitive resin may be carried out by dissolving and removing the coating film with an organic solvent at the same time, or after removing the formed coating film, the peeled surface is required. It may be a two-step process of cleaning with the organic solvent.
【００１０】[0010]
【作用】本発明によれば、液晶表示装置の製造・組み立
てに先立って、予め薄膜トランジスタアレイ基板面に感
光性樹脂を塗布処理し、さらに有機溶剤による洗浄処理
を施しており、前記感光性樹脂塗布膜の剥離、もしくは
溶解除去により薄膜トランジスタアレイ基板面での吸水
性物質が容易に除去されるとともに、有機溶剤の洗浄処
理（ないしリンス処理）によって、表面に吸着している
水分が全面的に置換・除去される。したがって、その後
においては、水分を導電体として表面を流れるリーク電
流の発生が、大幅にないし全面的に解消・防止される。
つまり、各画素電極のスイッチングに関与する LDD構造
の TFTの OFF領域におけるリーク電流が大幅に低減・抑
制され、所要のデータ保持もなされるため、常に高品質
な画質を表示することが可能な液晶表示装置を容易に、
歩留まりよく製造することができる。According to the present invention, prior to the manufacture and assembly of the liquid crystal display device, the thin film transistor array substrate surface is previously coated with a photosensitive resin, and further washed with an organic solvent. By removing or dissolving the film, the water-absorbing substance on the thin film transistor array substrate surface is easily removed, and the water adsorbed on the surface is completely replaced by the washing process (or rinsing process) of the organic solvent. To be removed. Therefore, thereafter, the generation of the leak current flowing on the surface by using water as a conductor is largely or completely eliminated or prevented.
In other words, the leakage current in the OFF area of the TFT of the LDD structure, which is involved in the switching of each pixel electrode, is greatly reduced and suppressed, and the required data retention is also performed, so that a liquid crystal that can always display high-quality image quality. Display device easily,
It can be manufactured with high yield.
【００１１】[0011]
【実施例】以下図１および図２ (a)， (b)を参照して、
本発明の実施例を説明する。EXAMPLE Referring to FIGS. 1 and 2 (a) and (b),
An example of the present invention will be described.
【００１２】図１は、本発明に係る液晶表示装置の製造
方法で製造された液晶表示装置の要部構成、すなわち表
示画素部を断面的に示したもので、次のような手段を経
て製造される。たとえば石英製基板１の一主面上に、活
性層を成す非晶質シリコン膜を減圧 CVD法で成膜し、約
600℃で15時間、固相成長を行い、厚さ 100nm程度の第
１のPoly−Si膜２化した後パターニングした。次に、こ
のパターニングした第１のPoly−Si膜２面を熱酸化させ
てゲート絶縁膜３を形成した後、チャンネル部４形成領
域面上に、減圧 CVD法によって低抵抗化した厚さ 400nm
程度の第２のPoly−Si膜5aおよび WSi膜5bを積層成膜
し、ゲート５を形成する。FIG. 1 is a cross-sectional view showing a main part configuration of a liquid crystal display device manufactured by the method for manufacturing a liquid crystal display device according to the present invention, that is, a display pixel part, which is manufactured by the following means. To be done. For example, an amorphous silicon film forming an active layer is formed on one main surface of the quartz substrate 1 by a low pressure CVD method,
Solid-phase growth was performed at 600 ° C. for 15 hours to form a first Poly-Si film 2 having a thickness of about 100 nm, which was then patterned. Next, after the patterned first Poly-Si film 2 surface is thermally oxidized to form the gate insulating film 3, a resistance of 400 nm is reduced by the low pressure CVD method on the surface of the channel 4 forming region.
A second Poly-Si film 5a and a WSi film 5b are stacked to form a gate 5 to a certain extent.
【００１３】一方。前記チャンネル部形成領域、換言す
るとゲート５下（チャンネル部４）両側に位置する第１
のPoly−Si膜２に、ｎ型のドーバントであるAsをイオン
注入法で選択的に打ち込み、低抵抗化してソース領域
６、ドレイン領域７、およびチャンネル部４との接合部
間で電場緩和に寄与する LDD部（LDD 構造化）6a，7aを
形成する。その後、前記ゲート５形成面上に、たとえば
減圧 CVD法で厚さ 500nm程度の第１の絶縁層８として S
iO2 層を成膜し、選択エッチングによりいわゆるコンタ
クトホールの形成、このコンタクトホールを介してのソ
ース電極９およびドレイン電極10を形成してから、たと
えばAl膜をスパッタにより成膜後、選択エッチングでパ
ターニングして信号線11を形成する。次いで、たとえば
常圧 CVD法によって厚さ 600nm程度の第２の絶縁層12と
して SiO2 層を成膜し、選択エッチングによりいわゆる
コンタクトホールの形成た後、 ITOをスパッタ法により
形成し、この ITO膜をパターニングして画素電極13を形
成し、さらに前記第２の絶縁層12および画素電極13面上
には、たとえば SiNx 層（図示せず）が保護膜として形
成される。なお、この構成においては、いわゆる MOS容
量である蓄積容量は、活性層と一体で画素電極13の一部
およびゲート絶縁膜３を成す層を挟んで配置された蓄積
容量線などによって形成されており、また前記ゲート５
は走査線（図示せず）にそれぞれ接続している。On the other hand, The channel portion forming region, in other words, the first portions located on both sides under the gate 5 (channel portion 4)
As, which is an n-type dopant, is selectively implanted into the Poly-Si film 2 by the ion implantation method to reduce the resistance and relax the electric field between the junctions with the source region 6, the drain region 7 and the channel portion 4. Form the contributing LDD parts (LDD structured) 6a, 7a. After that, as a first insulating layer 8 having a thickness of about 500 nm is formed on the gate 5 formation surface by, for example, a low pressure CVD method.
After forming an iO 2 layer and forming a so-called contact hole by selective etching, forming the source electrode 9 and the drain electrode 10 through this contact hole, for example, forming an Al film by sputtering, and then performing selective etching. The signal line 11 is formed by patterning. Then, for example, an SiO 2 layer is formed as a second insulating layer 12 having a thickness of about 600 nm by atmospheric pressure CVD method, a so-called contact hole is formed by selective etching, and ITO is formed by sputtering method. Is patterned to form the pixel electrode 13, and a SiN x layer (not shown), for example, is formed as a protective film on the surfaces of the second insulating layer 12 and the pixel electrode 13. In this structure, the so-called MOS capacitor, which is a so-called MOS capacitor, is formed by the storage capacitor line and the like which are arranged integrally with the active layer so as to sandwich a part of the pixel electrode 13 and the layer forming the gate insulating film 3. , Again the gate 5
Are connected to scanning lines (not shown), respectively.
【００１４】前記によって製造した TFTアレイ基板14
を、回転数 500 rpmで30秒間、4000 rpmで 180秒間回転
させながら、感光性樹脂を塗布してから、 110℃で 180
秒間加熱して成膜化し、この成膜を剥離除去した後、ア
セトンで 5分間洗浄し、さらに15分間水洗後、乾燥処理
した。次いで、この TFTアレイ基板14、および TFTアレ
イ基板14に対応する対向基板の互いに対向させる面に、
ポリイミド樹脂膜を被着形成し、ラビング処理を施して
配向膜をそれぞれ設けた。その後、前記対向基板の対向
電極形成面に、液晶材料の充填領域側壁を成すスペーサ
を配置し、液晶材料の注入口を除いて各引き出し配線部
分など液密にシールしながら、 TFTアレイ基板14の配向
膜面を対向させて接合一体化した。TFT array substrate 14 manufactured as described above
While rotating at 500 rpm for 30 seconds and 4000 rpm for 180 seconds, apply the photosensitive resin and then rotate at 110 ℃ for 180 seconds.
After heating for 2 seconds to form a film, the film was peeled off, washed with acetone for 5 minutes, further washed with water for 15 minutes, and then dried. Next, on the surfaces of the TFT array substrate 14 and the counter substrate corresponding to the TFT array substrate 14 facing each other,
A polyimide resin film was adhered and rubbed, and an alignment film was provided. After that, spacers that form the side wall of the filling area of the liquid crystal material are arranged on the counter electrode forming surface of the counter substrate. The surfaces of the alignment films were made to face each other and joined together.
【００１５】このようにして、 TFTアレイ基板14の配向
膜面および対向基板の配向膜面を対向させ、かつスペー
サを介して接合一体化し、液晶材料の充填・挟持領域を
液密に形成してから、前記液晶材料の注入口から所要の
液晶材料を注入・充填した後、前記液晶材料の注入口
を、たとえば紫外線硬化性樹脂で封止することにより、
所要の液晶表示装置が得られた。In this way, the alignment film surface of the TFT array substrate 14 and the alignment film surface of the counter substrate are opposed to each other, and they are joined and integrated with each other through the spacer to form the liquid crystal material filling / holding region in a liquid-tight manner. From, after injecting and filling the required liquid crystal material from the injection port of the liquid crystal material, by sealing the injection port of the liquid crystal material with, for example, an ultraviolet curable resin,
The required liquid crystal display device was obtained.
【００１６】上記製造した液晶表示装置について、表示
駆動行いそのときの表示画像の画質、ないし各画素の駆
動・制御に関与する TFTのリーク電流に基づく画質の劣
化を評価したところ、表示画質など大幅に改善・向上さ
れた液晶表示装置として機能することが確認された。た
とえば、前記液晶表示装置を構成する TFTアレイ基板14
が具備する TFTの電気的特性を測定・評価したところ、
図２ (a)および (b)にそれぞれ示すごとくであった。こ
こで、図２ (a)はPoly−Si系 TFTのゲート電圧に対する
ドレイン電流値、図２ (b)はPoly−Si系 TFTのゲート電
圧に対するゲート電流値であり、また曲線Ａ，Ｂ，Ｃ，
Ｄは、ドレイン電圧 Dv を 0.05V， 5.05V，10.05V，1
5.05Vの場合である。この電流特性図から分かるよう
に、換言すると前記図３との対比から明らかのように、
上記感光性樹脂の塗布処理および有機溶媒による洗浄処
理を施した場合は、ゲート電圧に対するドレイン電流お
よびゲート電流ともリーク電流が大幅に低減・防止され
て、各 TFTの OFF領域でのデータ保持能力を十分に確保
できる。そして、このゲートリーク電流の大幅な低減・
防止に伴い、常に良好な画質表示が容易、かつ確実に達
成されることになる。With respect to the liquid crystal display device manufactured as described above, the image quality of the display image at the time of driving the display, or the deterioration of the image quality due to the leak current of the TFT involved in the drive / control of each pixel was evaluated. It was confirmed that it could function as an improved and improved liquid crystal display device. For example, the TFT array substrate 14 that constitutes the liquid crystal display device
When we measured and evaluated the electrical characteristics of the TFT of
It was as shown in Fig. 2 (a) and (b) respectively. Here, FIG. 2 (a) is a drain current value with respect to the gate voltage of the Poly-Si TFT, FIG. 2 (b) is a gate current value with respect to the gate voltage of the Poly-Si TFT, and the curves A, B, and C are shown. ，
D is the drain voltage D v is 0.05V, 5.05V, 10.05V, 1
This is the case of 5.05V. As can be seen from this current characteristic diagram, in other words, as is clear from the comparison with FIG. 3,
When the photosensitive resin coating process and the organic solvent cleaning process are performed, the drain current and the gate current with respect to the gate voltage are greatly reduced and prevented, and the data retention capacity in the OFF area of each TFT is improved. You can secure enough. And this gate leakage current is greatly reduced.
Along with the prevention, a good image quality display can always be achieved easily and surely.
【００１７】なお、上記実施例では TFTの活性層がｎ型
のPoly−Siの場合について例示したが、活性層はｐ型の
Poly−Siであってもよいし、さらにPoly−Siに限らず非
晶質シリコン（ａ−Si）であっても勿論よい。さらに、
感光性樹脂の塗布処理および有機溶媒による洗浄処理
も、前記では塗布成膜し剥離後、アセトン洗浄・水洗を
行ったが、感光性樹脂の塗布，アセトン洗浄による塗膜
の除去，エタノールによるリンス処理の態様であっても
よい。また、この感光性樹脂の塗布処理および有機溶媒
による洗浄処理は、前記例示に限定されるものでなく、
むしろ SiNx 保護膜形成前、たとえば信号線11を形成し
た段階で行うのが好ましい。In the above embodiment, the TFT active layer is an n-type Poly-Si, but the active layer is a p-type.
Poly-Si may be used, or amorphous silicon (a-Si) may be used as well as Poly-Si. further,
Regarding the photosensitive resin coating treatment and the organic solvent cleaning treatment as well, in the above, the coating film formation and peeling followed by acetone cleaning / water cleaning are performed. However, the photosensitive resin coating, the acetone cleaning / removal of the coating film, and the ethanol rinsing processing. The aspect may be. Further, the coating process of the photosensitive resin and the cleaning process with the organic solvent are not limited to the above examples,
Rather, it is preferably performed before the formation of the SiN x protective film, for example, at the stage of forming the signal line 11.
【００１８】[0018]
【発明の効果】以上詳細な説明で明らかなように、本発
明によれば、液晶表示装置の製造・組み立てに先立っ
て、一方の構成部材を成す TFTアレイ基板の少なくとも
能動面側が、感光性樹脂の塗布処理および有機溶媒によ
る洗浄処理を施される。そして、この一連の処理によ
り、前記 TFTアレイ基板の能動面側に吸着している水分
が効率的に除去・脱水される。したがって、 TFTアレイ
基板の能動面側、特に各 LDD構造の TFT領域における水
を導電体とする電流の流れが全面的に解消・防止され
る。つまり、 LDD構造の TFTの OFF時におけるリーク電
流がデータの保持能力を低下させないレベルまで、容易
かつ大幅に低減されため、 LDD構造の TFTの OFF領域で
保持データが損傷される恐れも確実に回避されることに
なり、常に良好な画質を表示する機能を保持・発揮する
信頼性の高い液晶表示装置の提供が可能である。As is apparent from the above detailed description, according to the present invention, at least the active surface side of the TFT array substrate, which constitutes one of the constituent members, is made of a photosensitive resin prior to the manufacture and assembly of the liquid crystal display device. Coating treatment and cleaning treatment with an organic solvent. By this series of processing, the water adsorbed on the active surface side of the TFT array substrate is efficiently removed and dehydrated. Therefore, the flow of current using water as a conductor on the active surface side of the TFT array substrate, particularly on the TFT area of each LDD structure, is completely eliminated or prevented. In other words, the leakage current when the LDD structure TFT is turned off can be easily and significantly reduced to a level that does not reduce the data retention capacity, so it is possible to reliably avoid the possibility that the retention data will be damaged in the LDD structure TFT OFF region. As a result, it is possible to provide a highly reliable liquid crystal display device that maintains and exhibits the function of always displaying good image quality.
【図１】本発明に係る製造方法で製造した液晶表示装置
の要部構造例を示す断面図。FIG. 1 is a sectional view showing a structural example of a main part of a liquid crystal display device manufactured by a manufacturing method according to the present invention.
【図２】本発明に係る製造方法で製造した液晶表示装置
の TFTアレイ基板が具備する LDD構造の TFTの電気特性
例を示すもので、 (a)はゲート電圧に対するドレイン電
流値の曲線図、 (b)はゲート電圧に対するゲート電流値
の曲線図。FIG. 2 shows an example of electrical characteristics of an LDD structure TFT provided in a TFT array substrate of a liquid crystal display device manufactured by the manufacturing method according to the present invention, (a) is a curve diagram of a drain current value with respect to a gate voltage, (b) is a curve diagram of the gate current value with respect to the gate voltage.
【図３】従来の液晶表示装置の TFTアレイ基板が具備す
る LDD構造の TFTの電気特性例を示すもので、 (a)はゲ
ート電圧に対するドレイン電流値の曲線図、 (b)はゲ
ート電圧に対するゲート電流値の曲線図。3A and 3B show an example of electrical characteristics of an LDD structure TFT provided in a TFT array substrate of a conventional liquid crystal display device, in which (a) is a curve diagram of drain current value with respect to gate voltage, and (b) is with respect to gate voltage. Curve diagram of gate current value.
１…石英製基板、２…第１のPoly−Si膜（活性層）、３
…ゲート絶縁膜 ４…チャンネル形成部 ５…ゲー
ト 5a…第２のPoly−Si膜 5b… WSi層 ６…ソース領域 ７…ドレイン領域 ８…第１の絶
縁層 ９…ソース電極 10…ドレイン電極 11…
信号線 12…第２の絶縁層 13…画素電極 14… TFTアレイ基板1 ... Quartz substrate, 2 ... First Poly-Si film (active layer), 3
... Gate insulating film 4 ... Channel forming part 5 ... Gate 5a ... Second Poly-Si film 5b ... WSi layer 6 ... Source region 7 ... Drain region 8 ... First insulating layer 9 ... Source electrode 10 ... Drain electrode 11 ...
Signal line 12 ... Second insulating layer 13 ... Pixel electrode 14 ... TFT array substrate
Claims (1)
び前記薄膜トランジスタ素子に接続された画素電極を備
えた薄膜トランジスタアレイ基板と、前記薄膜トランジ
スタアレイ基板の画素電極に対向する対向電極を備えた
対向基板とを、前記画素電極および対向電極を対向さ
せ、かつ液晶材料を充填・挟持する液密な空間領域を形
成させて封止・一体化する工程、および前記薄膜トラン
ジスタアレイ基板および対向基板で形成する液密な空間
領域に液晶材料を充填・挟持させる工程を具備して成る
液晶表示装置の製造方法において、 前記薄膜トランジスタアレイ基板面に、予め感光性樹脂
の塗布処理および有機溶剤による洗浄処理を施しておく
ことを特徴とする液晶表示装置の製造方法。1. A thin film transistor array substrate having an LDD-structured thin film transistor element and a pixel electrode connected to the thin film transistor element; and a counter substrate having a counter electrode facing the pixel electrode of the thin film transistor array substrate, A step of forming a liquid-tight space area in which the pixel electrode and the counter electrode are opposed to each other and filling and sandwiching a liquid crystal material, and sealing and unifying, and a liquid-tight space area formed by the thin film transistor array substrate and the counter substrate. In the method for manufacturing a liquid crystal display device, which comprises a step of filling and sandwiching a liquid crystal material with the above, the thin film transistor array substrate surface is previously subjected to a photosensitive resin coating treatment and an organic solvent cleaning treatment. Method for manufacturing liquid crystal display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3628393A JPH06250218A (en) | 1993-02-25 | 1993-02-25 | Production of liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3628393A JPH06250218A (en) | 1993-02-25 | 1993-02-25 | Production of liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06250218A true JPH06250218A (en) | 1994-09-09 |
Family
ID=12465465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3628393A Withdrawn JPH06250218A (en) | 1993-02-25 | 1993-02-25 | Production of liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06250218A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999039241A1 (en) * | 1998-01-30 | 1999-08-05 | Hitachi, Ltd. | Liquid crystal display device |
| US6781646B2 (en) | 2000-07-28 | 2004-08-24 | Hitachi, Ltd. | Liquid crystal display device having gate electrode with two conducting layers, one used for self-aligned formation of the TFT semiconductor regions |
-
1993
- 1993-02-25 JP JP3628393A patent/JPH06250218A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999039241A1 (en) * | 1998-01-30 | 1999-08-05 | Hitachi, Ltd. | Liquid crystal display device |
| US6559906B1 (en) * | 1998-01-30 | 2003-05-06 | Hitachi, Ltd. | Liquid crystal display device having gate electrode with two conducting layers, one used for self-aligned formation of the TFT semiconductor regions |
| US6781646B2 (en) | 2000-07-28 | 2004-08-24 | Hitachi, Ltd. | Liquid crystal display device having gate electrode with two conducting layers, one used for self-aligned formation of the TFT semiconductor regions |
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