JPH06232266A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06232266A
JPH06232266A JP5016017A JP1601793A JPH06232266A JP H06232266 A JPH06232266 A JP H06232266A JP 5016017 A JP5016017 A JP 5016017A JP 1601793 A JP1601793 A JP 1601793A JP H06232266 A JPH06232266 A JP H06232266A
Authority
JP
Japan
Prior art keywords
semiconductor device
power supply
potential
bonding pads
supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5016017A
Other languages
Japanese (ja)
Other versions
JP2972473B2 (en
Inventor
Nobuko Nakanishi
信子 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP5016017A priority Critical patent/JP2972473B2/en
Publication of JPH06232266A publication Critical patent/JPH06232266A/en
Application granted granted Critical
Publication of JP2972473B2 publication Critical patent/JP2972473B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To easily supply potential from the outside and to easily analyze a fault caused by opening a package when the fault is analyzed in a semiconductor device provided with a plurality of bonding pads used to supply a power- supply potential. CONSTITUTION:Aluminum interconnections 17a, 17b are connected, via a resistance 16a, to bonding pads 13a, 13b used to supply a power-supply potential, and all interconnections used to supply the power-supply potential are connected. Thereby, when the potential is supplied to one out of the bonding pads 13a, 13b, a trouble can be analyzed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
半導体集積回路チップ内の電源供給用配線に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a power supply wiring in a semiconductor integrated circuit chip.

【０００２】[0002]

【従来の技術】半導体装置に不具合が発生した場合、そ
の解析法には種々の方法があるが、その一つの方法とし
て、不具合の発生した半導体装置のパッケージを開封し
て、不良箇所を同定する方法がある。2. Description of the Related Art When a defect occurs in a semiconductor device, there are various methods for analyzing the defect. One of the methods is to open the package of the defective semiconductor device and identify the defective portion. There is a way.

【０００３】最近多く用いられている樹脂封止のパッケ
ージの場合、発煙硝酸中に入れて、樹脂を溶かすこと
で、開封を行っている。In the case of a resin-sealed package which has been widely used recently, the package is opened by placing it in fuming nitric acid to dissolve the resin.

【０００４】図４は、従来の樹脂封止された半導体装置
を示した断面図である。図４に於て、半導体ペレット１
は、アイランド２の上に固定、保持されており、半導体
ペレット１上に設けられたボンディングパッド３と、リ
ード４との間は、ボンディングワイヤ５により、電気的
に接続され、樹脂６で封止されている。FIG. 4 is a sectional view showing a conventional resin-sealed semiconductor device. In FIG. 4, semiconductor pellet 1
Are fixed and held on the island 2, and the bonding pad 3 provided on the semiconductor pellet 1 and the lead 4 are electrically connected by a bonding wire 5 and sealed with a resin 6. Has been done.

【０００５】このような従来の半導体装置では、解析中
に、ボンディングワイヤ５が、取れてしまったり、銅に
より作られたリード４が、溶けてしまったりする。この
ため、不具合箇所を同定するため、外部から電位を供給
する場合には、探針により、半導体ペレット１上の電源
電位供給用ボンディングパッド３に、電位を供給しなけ
ればならない。In such a conventional semiconductor device, the bonding wire 5 is removed during the analysis, or the lead 4 made of copper is melted. Therefore, in order to identify the defective portion, when the potential is supplied from the outside, the potential must be supplied to the power supply potential supply bonding pad 3 on the semiconductor pellet 1 by the probe.

【０００６】[0006]

【発明が解決しようとする課題】しかるに、近年の半導
体装置では、半導体ペレット上に、電源電位供給用ボン
ディングパッドを複数個設け、機能の異なる回路に別々
に電源電位を供給することが行われており、このような
半導体装置に前述した解析を行う場合は新たな問題が生
じる。However, in recent semiconductor devices, a plurality of power source potential bonding pads are provided on a semiconductor pellet, and power source potentials are separately supplied to circuits having different functions. However, a new problem arises when the above-described analysis is performed on such a semiconductor device.

【０００７】以下にこの点について述べる。図５は、こ
のような半導体装置の半導体ペレット上の配置を示した
平面図である。This point will be described below. FIG. 5 is a plan view showing the arrangement of such a semiconductor device on a semiconductor pellet.

【０００８】図５に於て、２つの回路ブロック１２ａ，
１２ｂに供給される電源電位，接地電位は、別々のボン
ディングパッド１３ａ，１３ｂ、およびボンディングパ
ッド１４ａ，１４ｂにより供給されるようになってい
る。そして、各ボンディングパッドは、それぞれ異なる
リード４に、ボンディングワイヤによって、接続されて
いる。このように、半導体ペレット１上に、電源電位供
給用パッドを複数個設け、機能の異なる回路に別々に電
源電位，接地電位を供給するのは一方の回路が動作する
ことによる電源電位，接地電位の変動の影響が他方の回
路に及ぶのを防ぐことを目的としている。In FIG. 5, two circuit blocks 12a,
The power supply potential and the ground potential supplied to 12b are supplied by separate bonding pads 13a and 13b and bonding pads 14a and 14b. Each bonding pad is connected to a different lead 4 by a bonding wire. As described above, a plurality of power supply potential supply pads are provided on the semiconductor pellet 1, and the power supply potential and the ground potential are separately supplied to the circuits having different functions by the operation of one circuit. The purpose of this is to prevent the influence of fluctuations in the other circuit from reaching the other circuit.

【０００９】このような半導体装置に対し、前述したパ
ッケージ開封による解析を行う場合、その内容によって
は、すべての電源電位供給用ボンディングパッドに、電
位を供給しないと解析できないことがある。たとえば、
リーク箇所を同定しようとする場合、電位を供給されな
いボンディングパッドがあると、それに接続された回路
がフローティング状態となり、予期せぬ貫通電流が流
れ、真のリーク箇所の同定ができなくなってしまう。When such a semiconductor device is analyzed by opening the package as described above, depending on the contents, it may not be possible to analyze unless the potential is supplied to all the bonding pads for supplying the power supply potential. For example,
When attempting to identify a leak location, if there is a bonding pad to which a potential is not supplied, the circuit connected to it becomes a floating state, an unexpected through current flows, and the true leak location cannot be identified.

【００１０】このような解析の場合、半導体ペレット１
上に設けられた、複数個の電源電位供給用ボンディング
パッドすべてに、探針によって、電位を供給しなければ
ならず、解析が難しくなるという問題がある。更に、最
近では、半導体ペレット上に設けられる複数の電源電位
供給用ボンディングパッドも、２個，３個にとどまら
ず、５個，６個と設けられて、その数も増加する傾向に
あり、このような半導体装置では、前記問題はより大き
なものとなる。In the case of such an analysis, the semiconductor pellet 1
There is a problem that the potential must be supplied to all of the plurality of power supply potential supply bonding pads provided above by the probe, which makes analysis difficult. Furthermore, recently, a plurality of power supply potential supply bonding pads provided on a semiconductor pellet are not limited to two and three, but are provided with five and six, and the number thereof tends to increase. In such a semiconductor device, the above problem becomes more serious.

【００１１】[0011]

【課題を解決するための手段】本発明の構成は、ｎ個
（ｎ≧２）の同一電位供給用の電源パッドを有する半導
体装置に於て、前記ｎ個の電源パッドよりチップの内部
に電源を供給するｎ本の電源供給用配線のいずれもが、
残りのｎ−１本の電源配線のうちの少なくとも１本に抵
抗を介して接続したことを特徴とする。According to the structure of the present invention, in a semiconductor device having n (n ≧ 2) power supply pads for supplying the same potential, a power supply is provided inside the chip from the n power supply pads. Each of the n power supply wirings for supplying
It is characterized in that at least one of the remaining n-1 power supply lines is connected via a resistor.

【００１２】[0012]

【実施例】次に、図面を用いて、本発明について説明す
る。図１は本発明の第１の実施例の半導体装置を示す平
面図である。図１に於て、従来技術の説明で用いた図５
と同一機能を有する部分については同一番号を付してい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, FIG. 5 used in the description of the prior art.
The parts having the same functions as are given the same numbers.

【００１３】図１において、本実施例の従来技術（図
５）との相違点は、半導体（基板）ペレット１上に分離
して設けられた電源電位供給用のアルミニウム配線１７
ａ，１７ｂおよびアルミニウム配線１８ａ，１８ｂが、
それぞれ抵抗１６ａ，１６ｂを介して接続されているこ
とである。その他の部分は、図５と同様である。なお、
抵抗１６ａ，１６ｂの抵抗値は、１ｋΩ〜１０ｋΩ程度
に設定している。In FIG. 1, the difference from the prior art of this embodiment (FIG. 5) is that aluminum wirings 17 are separately provided on the semiconductor (substrate) pellet 1 for supplying a power supply potential.
a, 17b and aluminum wirings 18a, 18b are
That is, they are connected via resistors 16a and 16b, respectively. Other parts are the same as in FIG. In addition,
The resistance values of the resistors 16a and 16b are set to about 1 kΩ to 10 kΩ.

【００１４】本実施例によれば、パッケージ開封によ
り、リード４やボンディングワイヤがはずれても、ボン
ディングパッド１４ａ，１４ｂのいずれか一方と、１３
ａ，１３ｂのいずれか一方とに電位を供給すれば、不具
合の解析を行うことができる。According to this embodiment, even if the lead 4 or the bonding wire is detached by opening the package, either one of the bonding pads 14a and 14b and 13
By supplying a potential to either one of a and 13b, it is possible to analyze the defect.

【００１５】図２は、図１で示した半導体装置の抵抗部
分１６ａ（又は１６ｂ）の実際のパターンを示した平面
図である。図２に於て、抵抗１６ａは、多結晶シリコン
により形成され、分離された２つのアルミニウム配線１
７ａ，１７ｂの間に、挿入されて、コンタクト１９で接
続されている。FIG. 2 is a plan view showing an actual pattern of the resistance portion 16a (or 16b) of the semiconductor device shown in FIG. In FIG. 2, the resistor 16a is made of polycrystalline silicon and is separated into two aluminum wirings 1
It is inserted between 7a and 17b and connected by a contact 19.

【００１６】図３は、図１で示した半導体装置とは別の
構成の半導体装置に、本発明を適用した場合の平面図で
あり、本発明の第２の実施例が示されている。本実施例
の半導体装置に於ては、半導体ペレット１上に設けられ
た、２個の電源電位供給用ボンディングパッド１３ａ，
１３ｂが、同一のリード４に、接続されている。同様
に、２個の接地電位供給用ボンディングパッド１４ａ，
１４ｂも同一のリード４に、接続されている。FIG. 3 is a plan view when the present invention is applied to a semiconductor device having a structure different from that of the semiconductor device shown in FIG. 1, and shows a second embodiment of the present invention. In the semiconductor device of the present embodiment, two power supply potential supply bonding pads 13a, which are provided on the semiconductor pellet 1,
13b are connected to the same lead 4. Similarly, two ground potential supply bonding pads 14a,
14b is also connected to the same lead 4.

【００１７】このような、半導体装置で、パッケージ開
封により、ボンディングワイヤが切れてしまうと、前記
２つのボンディングパッド１３ａ，１３ｂ、およびボン
ディングパッド１４ａ，１４ｂは、半導体チップ上で、
分離されてしまう。このため、２本のアルミニウム配線
１７ａ，１７ｂおよびアルミニウム配線１８ａ，１８ｂ
それぞれを抵抗１６ａ，１６ｂを介して接続している。In such a semiconductor device, when the bonding wire is cut by opening the package, the two bonding pads 13a and 13b and the bonding pads 14a and 14b are formed on the semiconductor chip.
It will be separated. Therefore, the two aluminum wirings 17a and 17b and the two aluminum wirings 18a and 18b are provided.
Each of them is connected via resistors 16a and 16b.

【００１８】[0018]

【発明の効果】以上説明したように、本発明は、半導体
基板上に分離して設けた複数の電源電位供給用配線を、
異なるボンディングパッドに接続した半導体装置に於
て、前記複数に分離した電源電位供給用配線すべてを抵
抗素子を介して接続することで、パッケージ開封による
不具合解析時の電源電位の供給を容易に行うことができ
るという効果を有する。As described above, according to the present invention, a plurality of wirings for supplying power source potential, which are separately provided on the semiconductor substrate, are provided.
In a semiconductor device connected to different bonding pads, by connecting all of the above-mentioned multiple power supply potential supply wirings through a resistance element, it is possible to easily supply the power supply potential during failure analysis by opening the package. It has the effect that

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の半導体装置を示した平
面図である。FIG. 1 is a plan view showing a semiconductor device of a first exemplary embodiment of the present invention.

【図２】図１の抵抗部の実際の形状を示した平面図であ
る。FIG. 2 is a plan view showing an actual shape of a resistance portion of FIG.

【図３】本発明の第２の実施例を示した平面図である。FIG. 3 is a plan view showing a second embodiment of the present invention.

【図４】従来の樹脂封止された半導体装置の断面図であ
る。FIG. 4 is a cross-sectional view of a conventional resin-sealed semiconductor device.

【図５】機能の異なる２つの回路ブロックに供給される
電源電位供給用ボンディングパッドの従来の配置を示し
た平面図である。FIG. 5 is a plan view showing a conventional arrangement of power supply potential supply bonding pads supplied to two circuit blocks having different functions.

【符号の説明】[Explanation of symbols]

１ 半導体ペレット ２ アイランド ３，１３ａ，１３ｂ，１４ａ，１４ｂ ボンディング
パッド ４ リード ５ ボンディングワイヤ ６ 樹脂 １２ａ，１２ｂ 回路ブロック １６ａ，１６ｂ 抵抗（多結晶シリコン） １７ａ，１７ｂ，１８ａ，１８ｂ アルミニウム配線 １９ コンタクト1 Semiconductor Pellet 2 Island 3, 13a, 13b, 14a, 14b Bonding Pad 4 Lead 5 Bonding Wire 6 Resin 12a, 12b Circuit Block 16a, 16b Resistor (Polycrystalline Silicon) 17a, 17b, 18a, 18b Aluminum Wiring 19 Contact

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 一チップ上に、ｎ個（ｎ≧２）の同一電
位供給用の電源パッドを備える半導体装置に於て、前記
ｎ個の電源パッドより前記一チップの内部に電源を供給
するｎ本の電源供給用配線のいずれもが、残りのｎ−１
本の電源配線のうちの少なくとも１本に、抵抗を介して
接続されていることを特徴とする半導体装置。1. In a semiconductor device having n (n ≧ 2) power supply pads for supplying the same potential on one chip, power is supplied from the n power supply pads to the inside of the one chip. Any of the n power supply wirings has the remaining n-1.
A semiconductor device, which is connected to at least one of power supply wirings of a book via a resistor. 【請求項２】 ｎ個の同一電位供給用の電源パッドが、
ボンディングワイヤを介して、同一のリードに電気的に
接続されている請求項１に記載の半導体装置。2. N power supply pads for supplying the same potential,
The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to the same lead via a bonding wire.
JP5016017A 1993-02-03 1993-02-03 Semiconductor device Expired - Fee Related JP2972473B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5016017A JP2972473B2 (en) 1993-02-03 1993-02-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5016017A JP2972473B2 (en) 1993-02-03 1993-02-03 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06232266A true JPH06232266A (en) 1994-08-19
JP2972473B2 JP2972473B2 (en) 1999-11-08

Family

ID=11904809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5016017A Expired - Fee Related JP2972473B2 (en) 1993-02-03 1993-02-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2972473B2 (en)

Also Published As

Publication number Publication date
JP2972473B2 (en) 1999-11-08

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