JPH06222012A - Image processor, image processing method and outer view inspection system for semiconductor package - Google Patents

Abstract

PURPOSE:To allow high speed inspection of many types and many items by imaging an object to be inspected, storing same images in a plurality of image memories, and performing different types of inspection in parallel using a plurality of processing units corresponding to respective memories. CONSTITUTION:A semiconductor package to be inspected is transferred sequentially to first to third inspecting sections 13a-13c through a mechanism section 3. In the inspection sections 13a-13c, camera controller boards 23a-23c control cameras 9a-9c to image the side face, the top surface and the bottom surface of the package, respectively. Outputs from the cameras 9a-9c are stored in the image memories within DSP boards 24a and 24b1, 24b2, 24b3 and 24c1, 24c2. Consequently, same output images from the cameras 9a, 9c are stored in a plurality of memories. Each board has a processing unit as well as the image memory and in the inspection section 13b, for example, inspection processing can be executed simultaneously in parallel by the processing units in the boards 24b1, 24b2 and 24b3. Increase/decrease of inspection items can be dealt with by increasing/decreasing the number of the boards 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an image for performing inspection such as lead shape inspection of semiconductor IC packages or other electronic parts, mold shape inspection, lead surface inspection, mold surface inspection, mark inspection, inter-lead foreign substance inspection and the like. The present invention relates to a processing device, an image processing method, and a semiconductor package appearance inspection device, and particularly when there are many inspection items and it is necessary to perform inspection at high speed, and when multiple types of inspected objects are subjected to the same image processing device or semiconductor package appearance inspection device. Effective when it is necessary to inspect by the device, or when detecting by checking whether there is a defect such as a burr protruding from the lead or a conductive foreign substance adhering to the lead between the leads of the semiconductor package The present invention relates to an image processing apparatus, an image processing method, and a semiconductor package appearance inspection apparatus, which are effective for

[0002]

2. Description of the Related Art Japanese Patent Laid-Open No. 3-204085 discloses a technique for visual recognition by taking in an image for product inspection or the like.
An image storage device described in Japanese Patent Laid-Open Publication No. 2003-242242 can be given. The method according to this prior application distributes images obtained from a high-resolution camera to a plurality of image memories to store high-resolution images, but aims at high-mix inspection with a wide variety of items and at high speed. Not a thing.

Further, as an apparatus for inspecting the leads themselves of the semiconductor package, that is, an apparatus for inspecting the lead bending and the lead floating amount, "IC lead inspecting apparatus" described in JP-A-2-269905 and JP-A-4-29007. The "optical inspection device" described in the publication, the "lead inspection device" described in JP-A-2-103404, and the like can be mentioned. But,
In the prior art disclosed in these prior applications, it was detected whether or not there was a defect such as a burr protruding from the lead or a conductive foreign substance adhering to the lead between the leads of the semiconductor package, and it was inspected. , There is no description about the semiconductor package visual inspection device. That is, at present, the above-mentioned inspection of foreign matter defects between leads of a semiconductor package is generally performed by an operator visually inspecting between the leads using a loupe or a microscope. And
In this visual inspection, a standard of a defect between the leads of the semiconductor package is created, and the defect is determined based on this standard. As a criterion for such a defect determination, for example, the size of a burr protruding from the lead or the size of a foreign substance attached to the lead is
If the space between the adjacent leads is more than half, it may be determined as defective.

[0004]

In the manufacture of semiconductor IC packages or other electronic components, lead shape inspection, mold shape inspection,
Appearance inspection such as lead surface inspection, mold surface inspection, mark inspection, inter-lead foreign material inspection is required. These inspections are carried out by installing a visual inspection device for each product type and each inspection item because there are many product types such as semiconductor IC packages and other electronic parts and many inspection items. However, in this case, the number of appearance inspection devices is large, so that the cost is high and the space needs to be wide. Therefore, many kinds,
It was also considered to perform multi-item inspection with the same device,
Due to the large number of inspection items, there was a problem that the inspection time was long.

Further, in the method of visually inspecting the inter-lead foreign matter defect inspection of the semiconductor package as described above, there is a problem in terms of inspection reliability such as inspection variation and oversight by an operator. In addition, there is a problem that long-time visual inspection is a very tiring work for the operator.

The present invention has been made in view of the above points,
It is an object of the present invention to provide an apparatus or method capable of performing high-speed inspections of a wide variety of items and a large number of items.
Another object of the present invention is to make it possible to automatically perform a foreign matter defect inspection between leads of a semiconductor package at high speed.

[0007]

To achieve the above object, an image capturing means for capturing an image of an inspection object and a plurality of images for simultaneously storing the same image of the inspection object captured by the image capturing means A memory and a plurality of processing units corresponding to the plurality of image memories in a one-to-one correspondence are provided, and different kinds of inspections are performed by using images in the image memories corresponding to the plurality of processing units. I decided to do it in parallel.

Further, there are provided means for capturing an image of the semiconductor package, an image memory for storing the image captured by the image capturing means, and image processing means for performing various image processing using the image stored in the image memory. In a semiconductor package visual inspection device having, by detecting the lead position of the semiconductor package by the image processing means, setting an inspection line between adjacent leads, whether the brightness density on this inspection line is brighter than the set brightness density, Alternatively, when a dark pixel is included, it is detected as a foreign matter defect between leads.

[0009]

Operation: The image capturing means captures the image of the inspection object,
The images of the object to be inspected are simultaneously stored in a plurality of image memories. Therefore, the same image of the inspection object is stored in the plurality of image memories. Since each of the plurality of processing units corresponds to each of the plurality of image memories, it becomes possible for each processing unit to perform different kinds of inspections in parallel. In addition, the appearance inspection can be speeded up.

Further, the image processing means accesses the image memory storing the image of the semiconductor package to utilize the fact that the brightness density of the lead becomes brighter or darker than the brightness density of the background. All lead positions of the package are detected, and an inspection line for inspecting the presence or absence of foreign matter between the leads is set between adjacent leads based on the lead positions. On this inspection line, if there is no burr or foreign matter in more than half of the space between adjacent leads, it is the background brightness density, but if there is a burr or foreign matter on the inspection line, it is brighter than the background brightness density ( Or it becomes a dark image. Therefore, set a brightness density that is lighter (or darker) than the background, and lighter (or darker) than this set brightness density.
If there is a pixel, it is possible to detect and inspect defects due to burrs or foreign matter between the leads, and thus it is possible to automate detection and inspection of foreign matter defects between leads of the semiconductor package.

[0011]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing the configuration of a semiconductor package visual inspection apparatus according to an embodiment of the present invention. This semiconductor package visual inspection apparatus is an image processing apparatus 2 that performs visual inspection of a semiconductor package 1 (see FIG. 3) by image processing, a mechanical unit 3 that carries, inverts, and positions the semiconductor package 1, and drives the mechanical unit 3. An operation display that has a mechanism control unit 4 for controlling parts and has operation switches such as an operation start switch and an operation stop switch, and outputs operation commands to the mechanism control unit 4 and displays the states of the mechanism unit 3 and the mechanism control unit 4. 5, an input / output terminal 6 for inputting inspection conditions and outputting inspection results, an illuminating device 7 for appropriately illuminating an image of the semiconductor package 1, and an image capturing for capturing an image of the semiconductor package 1 to be inspected Means 2
It is mainly composed of a 048 camera 9 and a monitor TV 10 for displaying an inspection state and an inspection defective portion in order to allow visual observation by an operator.

In the image processing apparatus 2, a system bus 21 which is a common transmission path for a plurality of boards, a CPU board 22 which is inserted into the system bus 21 and controls the entire image processing apparatus 2, and a CPU board 22. Commanded by 2048
The 2048 camera controller board 23 that controls the operation of the camera 9, the 2048 DSP board 24 that is an image processing board that stores and processes the image of the semiconductor package 1, and the light amount adjustment of the lighting device 7 and communication with the mechanism control unit 4 are performed. Lighting controller & I / O board 25, hard disk device 26 and floppy disk device 2 which are external storage devices
7 and a DC constant voltage power supply 28.

As shown in FIG. 1, the semiconductor package visual inspection apparatus of this embodiment has a first inspection section 13a (St. 1) for inspecting the side surface of the semiconductor package 1 and a second inspection section 13 for inspecting the upper surface of the semiconductor package 1. Inspection unit 13b (St. 2),
And a third inspection unit 1 for inspecting the lower surface of the semiconductor package 1.
It has three inspection units 13 of 3c (St. 3). Each of the inspection units 13a to 13c includes one 2048 camera 9 (S
t. 1 is a 2048 camera 9a, St. 2 is a 2048 camera 9b, St. 3 is a 2048 camera 9c), one 2048 camera controller board 23 (St. 1 is 2048 camera)
The camera controller board 23a, St. 2 is a 2048 camera controller board 23b, St. 3 is a 2048 camera controller board 23c), a 2048 DSP board 24
1 to several (St. 1 is 2048 DSP board 24
a sheet of St. 2 is a 2048 DSP board 24b1, 24b2
4b2 and 24b3, St. 3 is two 2048 DSP boards 24c1 and 24c2) and one monitor TV 10 (St. 1 is monitor TV 10a, St. 2 is monitor TV).
10b, St. 3 is a monitor TV 10c), and a lighting device 1
Or several (St. 1 is 2 of 7a1 and 7a2, S.
t. 2 is 2 of 7b1 and 7b2, and St. 3 is 1 of 7c
Individual). Also, 2048D
In the SP substrate 24 (see FIG. 9), an image memory 62 for storing the image of the semiconductor package 1 captured by the 2048 camera 9, a processing unit 63 for performing a semiconductor package appearance inspection using the image memory 62, and a processing unit 63. Program memory 64 for storing the above program, and data memory 6 for storing constants and variables used for appearance inspection
5 etc. are arranged.

The semiconductor package 1, which is the object to be inspected, is successively conveyed and positioned by the mechanical section 3 to the three inspection sections 13. After the semiconductor package 1 is conveyed and positioned, the CPU board 22 is connected to the inspection board 13 of the inspection unit 13 via the system bus 21.
048 camera controller boards 23a, 23b, 23c
The image input command is output to. The first inspection unit 13a (St.
In 1), the 2048 camera controller board 23
a controls the 2048 camera 9a to control the semiconductor package 1
2048 DSP board 24
The address of the image memory 62a in a is output and side image data is sequentially stored in the image memory 62a. Second
In the inspection unit 13b (St. 2), the 2048 camera controller board 23b controls the 2048 camera 9b to capture the top surface image of the semiconductor package 1, and 2
The addresses of the image memories 62b1, 62b2, 62b3 in the 048 DSP board 24b1, 24b2, 24b3 are output to output the upper surface image data to the 2048 DSP board 24b.
Image memories 62b1, 62 in 1, 24b2, 24b3
It is stored in b2 and 62b3 at the same time. Third inspection unit 13c
Similarly in (St. 3), the 2048 camera controller board 23c controls the 2048 camera 9c to capture the lower surface image of the semiconductor package 1, and
Image memory 62c in the DSP boards 24c1 and 24c2
The addresses 1 and 62c2 are output to store the lower surface image data in the image memories 62c1 and 62c2 in the 2048 DSP boards 24c1 and 24c2 at the same time.

The CPU board 22 is provided in each of the inspection parts 13a to 13a.
c 2048 camera controller boards 23a, 23b,
23c is monitored, and the inspection unit 13a that has finished image capturing
An inspection start command is output to the 2048 DSP board 24 with respect to 13c. 2048 that received the inspection start command
The DSP board 24 starts the inspection by the internal processing unit 63 using the image data in the image memory 62. Therefore, in the second inspection unit 13b (St. 2), 2
The same upper surface image data is simultaneously stored in the image memories 62b1, 62b2, 62b3 in the 048 DSP boards 24b1, 24b2, 24b3, and the processing units 63 in the 2048 DSP boards 24b1, 24b2, 24b3.
The inspection processing can be performed in parallel by b1, 63b2, and 63b3. Also, the third inspection unit 13c (St. 3)
In addition, the same upper surface image data is simultaneously stored in the image memories 62c1 and 62c2 in the 2048 DSP boards 24c1 and 24c2.
The inspection processing can be performed in parallel by the processing units 63c1 and 63c2 in the c1 and 24c2. That is,
Parallel processing of appearance inspection of the semiconductor package 1 is 2048
As many DSP boards 24 as the number of boards can be provided, and inspection items can be added and deleted by increasing or decreasing the number of 2048 DSP boards 24.

FIG. 2 is a block diagram showing a procedure for moving the semiconductor package 1 in the mechanism section 3 of the semiconductor package visual inspection apparatus. As shown in FIG. 2, the mechanism unit 3 is
A loader 11, a lead correction unit 12, three inspection units 13a,
It is composed of an inspection unit 13 having 13b and 13c, an unloader 14, a rotation moving unit 15, a conveyance reversing unit 16, and the like.

The semiconductor package 1 which is the object to be inspected, which is supplied from the loader 11 of the mechanism section 3 and whose lead is corrected in advance by the lead correcting section 12, includes the first inspection section 13a and the second inspection section 13a of the inspection section 13.
Positioning is performed in the inspection unit 13b and the third inspection unit 13c, and a predetermined visual inspection is performed on each. Conveyance of the semiconductor package 1 from the loader 11 to the lead correction unit 12, conveyance from the lead correction unit 12 to the first inspection unit 13a, conveyance from the first inspection unit 13a to the second inspection unit 13b, and from the second inspection unit 13b. The transportation to the third inspection unit 13c and the transportation from the third inspection unit 13c to the unloader 14 are performed by the transportation unit. In addition, the second inspection unit 13b
And the third inspection unit 13c, and between the third inspection unit 13c and the unloader 14, there are inverting units for inverting the semiconductor package 1. The movement of the semiconductor package 1 is performed, for example, by a conveyer such as a conveyor and a reversing unit such as a motor, and these are controlled by the mechanism controller 4. Further, the mechanism control unit 4 and the image processing apparatus 2 communicate with each other for synchronization.

FIG. 3 shows a semiconductor package 1 to be inspected.
3 is an external view showing an example of FIG. Semiconductor package 1 of FIG.
Is a semiconductor package 1 whose package name is called a flat package. The semiconductor package 1 is composed of a plurality of leads 91 and a mold 92. When the type of the semiconductor package 1 is different, the number of leads 91 is different and the length of the leads 91 is different.

4A, 4B, and 4C show the first inspection unit 13a and the second inspection unit 13 of the inspection unit 13 of FIGS. 1 and 2, respectively.
It is a perspective view which shows the semiconductor package 1 of the to-be-inspected object and the positional relationship with the 2048 camera 9 in the inspection part 13b and the 3rd inspection part 13c. 4, in the positional relationship of the first inspection unit 13a shown in FIG. 4A, the camera 9 is arranged in the lateral direction of the semiconductor package 1, and the rotation moving unit 15 mounts the semiconductor package 1 on the θY. Rotate the table to inspect lead shape such as flatness of leads.
Mold surface inspection such as voids on the side surface of the package, lead surface inspection such as solder attachment at the root of the lead, and inter-lead foreign substance inspection for inspecting burrs protruding from the leads between leads and conductive foreign substances attached to the leads are performed. In the positional relationship of the second inspection unit 13b shown in FIG. 4B, the 2048 camera 9 is arranged above the semiconductor package 1, and mainly voids on the package surface, foreign matter adhesion, package chipping / dimples, and package cracks. Etc., mold surface inspection to inspect for major chip defects, mark inspection to inspect marking state, lead shape inspection to inspect lead pitch and bending, lead surface inspection to inspect lead dents, etc. An inter-lead foreign substance inspection is performed to inspect burrs protruding between the leads and conductive foreign substances attached to the leads. In the positional relationship of the third inspection unit 13c shown in FIG. 4C, the 2048 camera 9 is arranged above the inverted semiconductor package 1, and the mark inspection is performed from the rear surface side of the semiconductor package 1 except for the mark inspection. The same inspection items (excluding the mark inspection) as those of the second inspection unit 13b shown in (b) are performed.

FIG. 5 is a structural diagram of an image input method and its optical system. In FIG. 5, a semiconductor package 1 to be inspected
A 2048 camera 9 as an image pickup unit and an illuminating device 7 as an illuminating unit for irradiating the light are installed at a position above which the reflected light can be received. An inspection stage 17 forming a conical background having a taper of a certain angle so as not to return to the camera 9 is installed, and the semiconductor package 1 appropriately illuminated by the illumination device 7 is imaged by the 2048 camera 9, and this imaging is performed. The image is the image input of the 2048 camera controller board 23. At this time, the operation of the 2048 camera 9 is controlled by the mirror control signal 82 from the 2048 camera controller board 23.
The image signal 83 is output in synchronization with the output clock 81.

FIG. 6 is an explanatory view showing a reflection state of the optical system of FIG. In FIG. 6, the inspection stage 17 has an inclination angle of 45.
When the surface of this cone is a mirror surface, even if the illumination light from above is totally reflected, the reflected light does not return to the 2048 camera 9, so the background of the captured image becomes dark. Good contrast can be obtained with respect to the image of the semiconductor package 1.

FIG. 7 is an explanatory view showing the structure of the 2048 camera 9. The 2048 camera 9 includes a lens 30, a galvanometer mirror 32, a galvanometer motor 31, a linear sensor 33, and the like. The linear sensor 33 has a maximum field-of-view size of the semiconductor package 1, which is the inspection object, of 51.2.
Assuming x51.2 mm ² , a 2048 x 1 pixel linear sensor is used to obtain a resolution of 25 μm. The light reflected by the semiconductor package 1 passes through the lens 30, is reflected by the galvanometer mirror 32, and is coupled to the linear sensor 33. The angle of the galvano mirror 32 placed on the optical axis of the linear sensor 33 is changed by giving a mirror control signal 82 to the galvano motor 31, and the linear sensor 33 scans the semiconductor package 1 in the Y-axis direction. Take an image. In this way, the linear sensor 33 captures an image in the X-axis direction, and the galvano mirror 3 is programmable.
Scanning in the Y-axis direction is performed by changing the angle of 2. Thereby, the linear image of the semiconductor package 1 is captured by the linear sensor 33. Since the 2048 camera controller board 23 outputs the clock 81 to the 2048 camera 9 in synchronization with the angle change of the galvano mirror 32, if the image signal 83 is taken in in synchronization with this clock 81, the angle change of the galvano mirror 32 will occur. An image synchronized with can be captured in the camera controller board 23.

FIG. 8 is a block diagram of the 2048 camera controller board 23. The 2048 camera controller board 23 controls the angle of the galvano mirror 32 by giving a mirror control signal 82 to the galvano motor 31 of the 2048 camera 9, and the image signal 83 output from the linear sensor 33 of the 2048 camera 9 is sent to the galvano mirror. A clock (synchronization signal) 81 synchronized with the mirror control signal 82 is output to the linear sensor 33 so as to be captured in synchronization with the angle of 32. Further, the 2048 camera controller board 23, after A / D converting the image signal 83 output from the linear sensor 33, outputs a plurality of 2048D signals to be described later.
This is a board for the purpose of outputting image data 84 to the SP board 24 through the image bus 29.

The 2048 camera controller board 23
Is a clock generating circuit 41, a frequency dividing circuit 42, a galvano data memory address generating circuit 4 as shown in FIG.
3, selector 45, galvano data memory 46, selector 47, D / A conversion circuit 48, galvano amplifier 49, camera I / F 50, A / D conversion circuit 51, image bus I / F
52, an image memory address generation circuit 53, and a system bus I / F 44.

This 2048 camera controller board 23
The operation of will be described. The clock 81 generated by the clock generating circuit 41 is divided into the frequency dividing circuits 42, 2 in order to synchronize the galvano mirror angle, the image output timing of the linear sensor, and the image storage address to the 2048 DSP board.
It is output to the 048 camera 9 and the image memory address generation circuit 53. The clock 81 applied to the frequency dividing circuit 42 is 16
The frequency is divided by a factor of 1 and added to the galvano data memory address generation circuit 43. The galvano data memory address generation circuit 43 is composed of a counter, and counts up by 1 each time a clock output from the frequency dividing circuit 42 is applied. The output of the galvano data memory address generation circuit 43 becomes the address of the galvano data memory 46. Therefore, the galvano data memory address is incremented by 1 for every 16 pulses of the clock 81 generated by the clock generation circuit 41.

Galvano data memory address generation circuit 4
The output of 3 is not directly connected to the galvano data memory 46, but is connected to one input of the selector 45. The other input of the selector 45 is connected to the system bus I / F 44. This is because the CPU board 22 is the system bus 2
The output of the galvano data memory address generation circuit 43 and the system bus I / F 44 can be selected by the selector 45 so that the galvano data memory address can be directly controlled via 1.

The galvano data memory 46 is composed of RAM or ROM and stores the angle of the galvano mirror 32 in the 2048 camera 9. Therefore, the angle of the galvano mirror 32 can be freely changed by rewriting this RAM or ROM. Particularly in the case of a RAM, the contents of the RAM are changed every time the type of the semiconductor package 1 changes, and the galvano mirror 32 is adapted to the dimensional change depending on the type.
You can change the maximum swing angle of. The galvanometer mirror angle data output of the galvanometer data memory 46 is connected to one input of the selector 47. The system bus I / F 44 is connected to the other input of the selector 47. This is so that the selector 47 can select the output of the galvano data memory 46 and the signal of the system bus I / F 44 so that the CPU board 22 can directly control the galvanometer mirror angle via the system bus 21. . The galvanometer mirror angle data is converted into an analog signal by the D / A conversion circuit 48, power-amplified by the galvano amplifier 49, and output to the 2048 camera 9.

On the other hand, the clock 81 generated by the clock generation circuit 41 is directly applied to the 2048 camera 9. As for this clock 81, the image signal 83 output from the linear sensor 33 in the 2048 camera 9 is the galvano mirror 32.
It is a clock applied to the linear sensor 33 so that it can be captured in synchronization with the angle of.

Further, the clock 81 generated by the clock generation circuit 41 is output to the image memory address generation circuit 53. The image memory address generation circuit 53 is composed of a counter, and counts up by 1 each time the clock 81 output from the clock generation circuit 41 is applied. Therefore, 2
The image memory address 85 is generated one by one in synchronization with the clock 81 applied to the linear sensor 33 in the 048 camera 9. The image signal 83 output from the linear sensor 33 of the 2048 camera 9 is
After the signal level is changed at F50, the image data 84 is quantized by the A / D conversion circuit 51. The image data 84 and the image memory address 85 output from the image memory address generation circuit 53 are output to the image bus 29 via the image bus I / F 52. In this way, the galvanometer mirror 32 of the 2048 camera 9 operates in synchronization with the clock 81 generated by the clock generation circuit 41, and the image data 8
4 and the image memory address 85 are output to the image bus 29 in synchronization. The image data 84 at this time is
It is data of 2048 pixels × 2048 pixels × 8 bits.

FIG. 9 is a block diagram of the 2048 DSP board 24. The 2048 DSP board 24 receives the image memory address 85 and the image data 84 output from the 2048 camera controller board 23 to the image bus 29, stores them in the image memory 62, and uses the image data 84 in the processing unit 63 to use the image data 84 in the semiconductor memory. This is a substrate for the purpose of inspecting the package 1.

The 2048 DSP board 24 has an image bus 29.
The image bus I / F 68 for receiving the image data 84 and the image address 85 from the board, the local bus 61 inside the substrate, the image memory 62 for storing the image data 84 of the semiconductor package 1, the DSP (Digital Signal Pro) which is a processing unit.
cessor) 63, system bus I / F 67, program memory 64 for storing programs of DSP 63, DSP 6
3, a data memory 65 for storing variables and constants, a dual port memory 66 for communicating with the CPU board 22 using the system bus 21, a video RAM 69 for displaying the contents of the image memory 62, and a monitor bus I / F ( The video RAM I / F) 70.

The operation of the 2048 DSP board 24 will be described. The image data 84 of the semiconductor package 1 transferred from the 2048 camera controller board 23 to the 2048 DSP board 24 via the image bus 29 is stored in the image memory 62 at the address indicated by the image address 85. C
The PU board 22 stores the image data 84 of the semiconductor package 1 of the object to be inspected in the image memory 62 of the 2048 DSP board 24, and then writes the inspection start instruction flag in the dual port memory 66 to start the inspection to the DSP (processing unit) 63. Give instructions. When the DSP 63 reads the start command from the dual port memory 66, the image data 8 of the semiconductor package 1 stored in the image memory 62 is read.
4, the inspection (image processing) is started. 2048D
Since the SP board 24 has a pair of the image memory 62 and the processing unit (DSP) 63 for each board, the inspection of the semiconductor package 1 can be performed for each 2048 DSP board 24. Therefore, the 2048 camera controller board 23
20 using the same image data 84 transmitted from
Separate inspection items can be inspected in parallel for each 48 DSP board 24.

When the inspection (image processing) in the 2048 DSP board 24 is completed, the DSP 63 writes the inspection result and the inspection end flag in the dual port memory 66. The CPU board 22 includes, for example, three 2048 boards in the second inspection unit 13b.
It is assumed that the inspection of all the DSP boards 24b1, 24b2, 24b3 is completed, and when the inspection of all the DSP boards 24b1, 24b2, 24b3 is completed, the inspection of the second inspection unit 13b for the semiconductor package 1 is completed. Note that this is the first and third inspection unit 13
The same applies to a and c.

The 2048 DSP board 24 has a function of displaying the inspection state on the monitor TV 10. DS
P63 writes the image to be displayed in the video RAM 69, and the content is sent out to the monitor TV 10 outside the board through the monitor bus I / F 70 and displayed. At this time, the image memory 62 has a semiconductor package image of 2048 pixels × 2048 pixels, but a normal monitor TV
Since 10 can display only 512 pixels x 512 pixels,
When displaying the whole image of the semiconductor package 1, the image data 84 in the image memory 62 is thinned out and the video RAM
It must be written and displayed in 69. When the partial image of the semiconductor package 1 is displayed as it is, the image data 84 in the image memory 62 is written in the video RAM 69 without being thinned out. At this time, only 512 pixels × 512 pixels in the image data 84 of 2048 pixels × 2048 pixels can be displayed. Whether to display the whole image or the partial image,
It can be determined by the program of the DSP 63, and the entire image is displayed during normal state display, and the partial image at the defect detection point is displayed during defect detection.

FIG. 10 is an explanatory diagram showing the sharing of processing by each part of the second inspection part 13b. The same time chart applies to the first inspection unit 13a and the third inspection unit 13c. The inspection order is as follows.

The CPU in the CPU board 22 outputs an image capture command to the 2048 camera controller board 23b of the second inspection section 13b.

The 2048 camera controller board 23b of the second inspection section 13b controls the 2048 camera 9b,
Captures the image of the upper surface of the semiconductor package 1 and further A / D
After conversion, the three 2048 DSPs of the second inspection unit 13b
The image data 84 is transferred to the boards 24b1, 24b2, 24b3. Three 2048 DSP boards 24b1 and 24b
2, 24b3 image memories 62b1, 62b2, 62b
The same image of the upper surface of the semiconductor package 1 is simultaneously input to 3.

The CPU is 2048 of the second inspection section 13b.
After monitoring the camera controller board 23b and confirming that the 2048 camera 9b has finished capturing images, the three 2048D
An inspection start command is issued to the SP boards 24b1, 24b2, 24b3.

Three 2048 DSP boards 24b1 and 24b2
4b2 and 24b3 perform inspections of different inspection items on the image data 84 of the same semiconductor package 1. For example, the first 2048 DSP board 24b1 is used for mark inspection, and the second 24b2 is used for mold surface inspection.
The sheet 24b3 is in charge of lead shape, lead surface inspection, and inter-lead foreign substance inspection. That is, one or a plurality of inspection items are assigned to each 2048 DSP board 24. These shares are assigned to the 2048 DSP boards 24b1 and 2b, respectively.
It is preferable that the total inspection time of 4b2 and 24b3 be substantially the same. Since these three 2048 DSP boards 24b1, 24b2, 24b3 can be inspected in parallel, respectively, many items can be inspected at high speed.

The CPU is three 2048 DSP boards 2
The completion of the inspection of each of 4b1, 24b2, and 24b3 is monitored, and when all the 2048 DSP boards 24 have completed the inspection, it is considered that the inspection of the second inspection unit 13b is completed.

When all the inspection units 13 of the first inspection unit 13a, the second inspection unit 13b, and the third inspection unit 13c have completed the inspection, the CPU communicates with the mechanism control unit 4 to transfer and invert the semiconductor package 1. Let it be done. Further, the inspection result is output to the input / output terminal 6.

From the mechanism control unit 4, the semiconductor package 1
When the conveyance and reversal of is completed and the inspection start command is received, the image processing apparatus 2 re-executes to and continues the inspection.

Next, the inter-lead foreign matter defect detection method and inspection method will be described. FIG. 11 is a top view image 9 of a gull wing type semiconductor package 1 which is an inspection object.
3 is a side view image 94, and a brightness density distribution on a scanning line drawn on these images. FIG.

FIG. 11A shows an upper surface image 93 of the semiconductor package 1, and FIG. 11F shows a side image 94 of the semiconductor package 1. FIGS. Each scan line a illustrated in FIG.
b, cd, ef, gh, and each scanning line ij, kl, m
The brightness density distributions on n and op are shown in FIG.
(C), (d), (e), and (g) of FIG.
(H), (i), and (j), respectively.

11B and 11G show the brightness density distributions on the scanning lines ab and ij drawn on one lead 91, respectively. In the top surface image 93 viewed from the top surface side of the semiconductor package 1, the lead tip 9 that is nearly perpendicular to the optical axis is shown.
Brightness Density 104 of 5 and Brightness Density of Lead Root 97 1
06 becomes higher (brighter), and the brightness density 105 of the lead center 96 near the optical axis becomes lower (darker). Therefore, the lead background (inspection stage) 1 like the scanning line ab
When a scan line is drawn from 7 in the direction of the mold 92, first the background 1
The brightness density 115 of 7 is the darkest, and then the lead tip 95
Brightness density of 104 becomes the brightest, and lead center 96
, The brightness density 106 of the lead root 97 becomes the brightest again, and the brightness density 113 of the mold 92 becomes dark. Therefore, by setting an appropriate brightness density threshold value 116, the lead tip 95 and the lead root 97 can be detected.

Further, in the side surface image 94 viewed from the side surface side of the semiconductor package 1, the brightness density 108 of the lead tip 99 and the brightness density 110 of the lead center 101, which are nearly perpendicular to the optical axis, are high, and other than that. Lead curve section 100
Brightness Density 109 and Lead Root 102 Brightness Density 1
11 will be low. Therefore, when a scanning line is drawn from the lead background (inspection stage) 17 in the direction of the mold 92 like the scanning line ij, the brightness density 115 of the background 17 is the darkest first, and then the brightness density 108 of the lead tip 99 is the darkest. The brightness density 109 of the lead curve portion 100 becomes darker, the brightness density of the lead center portion 101 becomes the brightest brightness density 110 again, and the lead root portion 102 becomes brighter.
Of the mold 92 becomes darker, and the brightness density 113 of the mold 92 becomes darker. Therefore, by setting an appropriate brightness density threshold value 116, the lead tip portion 99 and the lead center portion 101 can be detected.

11C and 11H show the brightness density distributions on the scanning lines cd and kl drawn on the leads 91 on one side, respectively. (C) and (h) of FIG.
As is clear from this, also in this case, FIG.
If the threshold 116 of the appropriate brightness density used in (g) is used, the lead tip 95 (top image) and the lead tip 99 (side image) can be detected separately from the background 17. This means that the positions (coordinates) of all the leads 91 can be detected. Therefore, all the detected leads 9 can be detected.
It is also possible to draw scanning lines ef, gh, mn, op, etc. for inspecting inter-lead foreign matter defects from the position 1 (coordinate) between the adjacent leads 91.

11D and 11I show the adjacent lead 9
The brightness density distributions on the scanning lines ef and mn drawn in 1 are shown. Since the brightness density distribution on these scanning lines is composed of the brightness density 115 of the background 17 and the brightness density 113 of the mold 92, (d) and (i) of FIG.
As shown in, the density distribution has a low brightness density.

11E and 11J respectively show the brightness density distributions on the scanning lines gh and op drawn between the adjacent leads 91, respectively. The situation is shown respectively. In this case,
Unlike (d) and (i), the brightness density 107 of the inter-lead foreign matter defect 98 of high brightness density is high in the low brightness density 115 or 113 of the background 17 or the mold 92.
Exists. Therefore, an appropriate brightness density threshold 1
If 17 is set, the inter-lead foreign matter defect 98 can be detected.

The inter-lead foreign matter defect 98 detected as described above is caused by all the leads 91 on the four sides of the top image 93.
If there is at least one between all the leads 91 on the four sides of the side image 94, it is determined that there is no inter-lead foreign matter defect 98, and if there is no such inter-lead foreign substance defect 98, the lead is determined. The foreign matter defect inspection can be automatically executed.

FIG. 12 is an explanatory diagram showing a processing flow for detecting foreign matter defects between leads in the second inspection portion 13b (upper surface inspection portion). Hereinafter, according to the flow of FIG.
A processing procedure for detecting foreign matter defects between leads by the second inspection unit 13b (upper surface inspection unit) will be described.

First, in step 1, the top image 93 of the semiconductor package 1 is captured by the 2048 camera 9, and the captured top image 93 is stored in the image memory 62.

In step 2, the position (coordinates) of the upper left end 121 of the left end lead 120 on the upper side of the upper surface image 93 of the semiconductor package 1 stored in the image memory 62 is detected (see FIG. 13 for this detection method). See below).

In step 3, based on the position (coordinates) of the upper left end 121 of the upper left end lead 120 obtained in step 2,
Left / right / upper / lower edge lead 1 of each of the top, left, bottom, and right sides
25, and the boundary coordinates 126 between each end lead 125 and the mold 92 are detected (this detection method will be described later with reference to FIG. 14).

In step 4, the boundary line 130 between the lead and the mold on each of the upper side, the left side, the lower side, and the right side is detected based on the boundary coordinates 126 obtained in step 3.

In step 5, the lead detection line 131 is set parallel to the boundary line 130 obtained in step 4 for each side based on the lead length data for each type obtained from teaching or manual input or CAD data. Draw a book or a few.

At step 6, the coordinates of the intersection 132 of the lead detection line 131 and the lead 91 drawn at step 5 are obtained for all the leads 91 on each of the upper side, the left side, the lower side and the right side, and the position of all the leads 91 ( Coordinate).

In step 7, based on the lead coordinates detected in step 6, an inter-lead foreign matter defect inspection line 133 is set in the center between adjacent leads.

In step 8, it is checked whether or not the brightness densities of all the pixels on each inter-lead foreign matter defect inspection line 133 are brighter than the set brightness density (brightness density threshold) 117. Then, when there is a pixel brighter than the brightness density 117 set on the inter-lead foreign matter defect inspection line 133, it is detected that the inter-lead foreign matter defect 98 exists at the coordinate position.

FIG. 13 shows the result of the step 2 in the inter-lead foreign matter defect detection flow by the upper surface inspection shown in FIG.
The position (coordinates) of the upper left end 121 of the upper left end lead 120
It is explanatory drawing which shows the method of detecting. As shown in FIG. 13, in order to detect the position (coordinates) of the upper left end 121 of the left end lead 120 on the upper side, first, the lead detection area 122 is set based on the positioning accuracy of the semiconductor package 1 of the second inspection unit 13b. ((A) of FIG. 13). Next, in order to detect a lead in the lead detection area 122,
An appropriate brightness density threshold value 116 is set, and scanning is sequentially performed in the x direction of the image until a pixel 124 having a brightness density of the threshold value 116 or higher is found ((b) in FIG. 13).
Next, starting from the detected pixel 124, the boundary between the background 17 and the leftmost lead 120 is sequentially tracked, and one round is made around the lead until returning to the first pixel. This tracking is called tracking, and a method of determining the boundary pixels of pixels having a threshold value of 116 or more and storing the coordinates of the boundary pixels is adopted.
Then, the minimum of the x coordinate and the minimum of the y coordinate are selected from the stored coordinates of the boundary pixel, and the set of the x coordinate and the y coordinate is used as the position (coordinate) of the upper left end 121 of the left end lead 120 of the upper side. It is detected ((c) of FIG. 13).

FIG. 14 shows the step 3 of the inter-lead foreign matter defect detection flow by the upper surface inspection shown in FIG.
Left / right / upper / lower edge lead 1 of each of the top, left, bottom, and right sides
25, and each end lead 125 and mold 92
It is explanatory drawing which shows the method of detecting the coordinate of the boundary 126 with. First, from the coordinates of the upper left edge 121 of the left edge lead 120 of the upper edge detected in step 2 of the flow of FIG.
The positions of the left / right / upper / lower ends leads 125 on the left side, the lower side, and the right side are calculated, and the end lead detection area 127 is set ((a) in FIG. 12). Next, the lead detection area 12 at each end
In FIG. 7, a threshold 116 of an appropriate brightness density is set in order to detect the end lead 125.
Scanning is sequentially performed from the outer side to the inner side of the lead row until a pixel having a brightness density of 16 or more is found ((b) in FIG. 14). Next, from the detected pixel 128 to the lead 125
By tracking the circumference of the lead width direction, the maximum and minimum values in the lead width direction and the maximum and minimum values in the lead longitudinal direction are obtained, and the coordinates of the boundary 126 between the end lead 125 and the mold 92 are obtained from these ((( c)). As a method of obtaining the coordinates of the boundary 126, the coordinate in the lead width direction is obtained by the coordinate of the lead median value, that is, ((maximum value in lead width direction) + (minimum value in lead width direction)) / 2. The coordinates of the lead longitudinal direction are the mold 92.
The coordinate in the longitudinal direction of the lead closest to is obtained.

FIG. 15 is an explanatory diagram showing a processing flow for detecting foreign matter defects between leads in the first inspection section 13a (side surface inspection section). Below, according to the flow of FIG.
A processing procedure for detecting foreign matter defects between leads by the first inspection unit 13a (side surface inspection unit) will be described.

First, in step 11, the semiconductor package 1
The side images 94 are sequentially captured by the 2048 camera 9 one by one and stored in the image memory 62, and the four side images 94 are stored in the image memory 62.

In step 12, the positions of the left and right side leads 136 of the side surface image 94 of the semiconductor package 1 stored in the image memory 62 are detected. Although only one side face is drawn in the drawings after step 12, the same detection is performed for the other three side faces.

In step 13, the periphery of the side lead 136 is tracked from the position of the side lead 136 obtained in step 12, and the boundary coordinates between the lead 136 and the background 17 are detected. After that, the coordinates of the lead end 137 of the side lead 136 are obtained by performing edge detection.

In step 14, the scanning start position of the scanning line 138 for detecting the mold upper surface 92a is determined based on the coordinates of the lead end 137 of the side lead 136 obtained in step 13, and scanning is performed in the mold 92 direction. , Background 17
Brightness Density 115 and Mold 92 Brightness Density 113
The boundary line 139 of the upper surface 92a of the mold is detected from the difference between and.

In step 15, the coordinates of the lead end 137 of the side lead 136 obtained in step 13 and step 1
From the boundary line 139 of the mold upper surface 92a obtained in 4,
The position of the side surface lead is calculated, each scanning line 140 for detecting the lower end of the side surface lead is set, and the lower end 141 of each side surface lead is tracked and edge-detected to detect the center of the lower end.

In step 16, based on the coordinates of the side surface leads obtained in step 15, two mold lower surface search lines 142 are scanned between the adjacent leads to detect the boundary line of the mold lower surface 92b.

In step 17, the inter-lead foreign matter defect inspection line 143 is set between the adjacent leads based on the coordinates of the center positions of the lower ends of the side leads detected in step 15.

In step 18, it is checked whether or not the brightness densities of all the pixels on the inter-lead foreign matter defect inspection line 143 are brighter than the set brightness density (brightness density threshold value) 117. If there is a pixel brighter than the brightness density 117 set on the inter-lead foreign matter defect inspection line 143, the inter-lead foreign matter defect 98 is detected at the coordinate position.

Next, referring to FIGS. 16 and 17, CAD
An example in which the inter-lead foreign matter defect 98 is inspected using data will be described.

FIG. 16 is an explanatory diagram showing a processing flow for detecting foreign matter defects between leads in the second inspection section 13b (upper surface inspection section). The processing from step 21 to step 24 in FIG. 16 is the same as the processing from step 1 to step 4 in FIG.

In step 25, each corner 134 of the mold 92 is obtained from the lead-mold boundary line 130 obtained in step 24, and the center 135 (P) of the semiconductor package 1 is obtained from the intersection of the diagonal lines. Also, step 2
The inclination θ of the semiconductor package 1 is obtained from the lead-mold boundary line 130 and the reference line obtained in step 4.

In step 26, the center of the semiconductor package of the CAD data is overlapped with the center 135 (P) of the semiconductor package of the top image 93, and the CAD data is tilted by the inclination θ of the semiconductor package of the top image 93. CAD data coordinate conversion is performed and CAD is performed on the data.
The data is overlaid on the semiconductor package of top image 93. Therefore, the mold and the lead of the CAD data correspond to the mold and the lead data of the semiconductor package of the top image 93, respectively.

In step 27, an inter-lead foreign matter defect inspection line 133 is set between the adjacent leads of the top image 93 based on the lead coordinates of the CAD data.

In step 28, it is checked whether or not the brightness densities of all the pixels on the inter-lead foreign matter defect inspection line 133 are brighter than the set brightness density (brightness density threshold) 117. Then, when there is a pixel brighter than the brightness density 117 set on the inter-lead foreign matter defect inspection line 133,
It is detected that there is an inter-lead foreign matter defect 98 at that coordinate position.

FIG. 17 is an explanatory view showing a processing flow for detecting foreign matter defects between leads in the first inspection section 13a (side surface inspection section). The processing from step 31 to step 34 in FIG. 17 is the same as the processing from step 11 to step 14 in FIG.

In step 35, 2 obtained in step 33
The lead tip center 144 (P) is determined as the midpoint of the coordinates of the lead ends 137 of the two side leads, and the inclination θ of the semiconductor package 1 is determined from the boundary line 139 of the mold upper surface 92 a obtained in step 24 and the reference line.

In step 36, the coordinates of the lead tip center of the CAD data are set to the lead tip center 144 of the side image 94.
(P) C so that the CAD data is overlapped with P and the CAD data is tilted by the tilt θ of the semiconductor package of the side surface image 94.
The coordinate conversion of the AD data is performed, and the CAD data is superposed on the data on the semiconductor package of the side surface image 94. Therefore, the mold and the lead of the CAD data correspond to the mold and the lead data of the semiconductor package of the side surface image 94, respectively.

In step 37, the inter-lead foreign matter defect inspection line 143 is set between the adjacent leads of the side image 94 based on the lead coordinates of the CAD data.

In step 38, it is checked whether or not the brightness densities of all the pixels on the inter-lead foreign matter defect inspection line 143 are brighter than the set brightness density (brightness density threshold value) 117. Then, when there is a pixel brighter than the brightness density set on the inter-lead foreign matter defect inspection line 143, it is detected that the inter-lead foreign matter defect 98 exists at the coordinate position.

FIG. 18 is a bottom view image 150 of a semiconductor package 1 of a type different from that of FIG. 11 called a J lead type.
FIG. 6 is an explanatory diagram showing a side surface image 151 and a brightness density distribution on a scanning line drawn on these images.

FIG. 18A shows a bottom image 150 of the semiconductor package 1, and FIG. 18F shows the semiconductor package 1.
18A shows a side image 151 of each of the scanning lines ab, cd, ef, gh, and the scanning lines ij, kl, m illustrated in FIGS. 18A and 18F, respectively.
The brightness density distribution on n and op is (b) in FIG.
(C), (d), (e), and (g) of FIG.
(H), (i), and (j), respectively.

18B and 18G show the brightness density distributions on the scanning lines ab and ij drawn on one lead 91, respectively. J-lead type semiconductor package 1
Indicates that the lead 91 bends into the lower surface of the semiconductor package 1 like the curved portion of the letter “J” in the alphabet, so the lower surface image 15 viewed from the lower surface side of the semiconductor package 1 is shown.
At 0, the curved portion of the lead 91 is visible. In the curved portion of the lead 91 in the bottom image 150,
Since more reflected light from the lead central portion 153 perpendicular to the optical axis is incident on the 2048 camera 9, the brightness density 159 of the lead central portion 153 increases, and the brightness of the lead root portion 152 other than the lead central portion 153 increases. Concentration 15
8, and the brightness density 160 of the lead tip portion 154 becomes low. Therefore, when a scan line is drawn from the lead background (inspection stage) 17 toward the mold 92 like the scan line ab, the brightness density 164 of the background 17 is first darkest, and then the brightness density 158 of the lead root portion 152 is It becomes brighter than the background, and the brightness density 159 of the lead center portion 153
Is the brightest, the brightness density 160 of the lead tip portion 154 is dark, and the brightness density 161 of the mold 92 is darker. Therefore, an appropriate brightness density threshold 1
If 65 is set, the lead central portion 153 can be detected.

Further, in the side surface image 151 viewed from the side surface side of the semiconductor package 1, the alphabetical character "J" is displayed.
The portion 156 corresponding to the straight line portion is substantially perpendicular to the optical axis to increase the brightness density, and the other portions, the brightness density 162 of the lead curve portion 155 and the lead root portion 157.
The brightness density of 165 becomes low. Therefore, like the scanning line ij, the lead 9
When scanning lines are drawn in two directions, the brightness density of the background 17 is 1
64 is the darkest, then the brightness density 162 of the lead curve part 155 is brighter than the brightness density 164 of the background 17, the brightness density 165 of the lead straight line part 156 is the brightest, and the brightness density of the lead root part 157. 164 becomes darker, and the brightness density 161 of the mold 92 becomes darker. Therefore, the lead straight line portion 156 can be detected by setting an appropriate brightness density threshold value 166.

18C and 18H show the brightness density distributions on the scanning lines cd and kl drawn on the leads 91 on one side, respectively. 18C and 18H of FIG.
As is clear from this, also in this case, FIG.
If the threshold value 166 of the appropriate brightness density used in (g) is used, the lead central portion 153 (bottom image) and the lead straight portion 156 (side image) can be detected separately from the mold 92. This is the position (coordinates) of all leads 91
Therefore, from the positions (coordinates) of all the leads 91, scanning lines ef, gh, mn, o for inspecting inter-lead foreign matter defects are detected between adjacent leads 91.
It is also possible to draw p and so on.

18D and 18I show the adjacent lead 9
The brightness density distributions on the scanning lines ef and mn drawn in 1 are shown. Since the brightness density distribution on these scanning lines is composed of the brightness density 164 of the background 17 and the brightness density 161 of the mold 92, (d) and (i) of FIG.
As shown in, the density distribution has a low brightness density.

18 (e) and 18 (j) respectively show the brightness density distributions on the scanning lines gh and op drawn between the adjacent leads 91, respectively. The situation is shown respectively. In this case,
Unlike (d) and (i), the brightness density 107 of the inter-lead foreign matter defect 98 of high brightness density is in the low brightness density 164 or 161 of the background 17 or the mold 92.
Exists. Therefore, an appropriate brightness density threshold 16
If 7 is set, the inter-lead foreign matter defect 98 can be detected.

The inter-lead foreign matter defect 98 detected as described above is caused by all the leads 9 on the four sides of the lower surface image 150.
If there is at least one space between the leads 91 and between all the leads 91 on the four sides of the side surface image 151, it is determined that there is an inter-lead foreign substance defect 98,
If it does not exist at all, it is possible to automatically perform the inter-lead foreign matter defect inspection by determining that there is no inter-lead foreign matter defect 98.

As described above, the positions (coordinates) of all the leads 91 can be detected even in the J-lead type semiconductor package 1, and therefore, like the gull-wing type semiconductor package 1, the defect between the leads 91 between the leads 91 is detected. It is possible to draw an inspection line (scanning line) for performing. Also,
In the J-lead type semiconductor package 1, as in the gull-wing type semiconductor package 1, the brightness density 107 of the inter-lead defect 98 is higher than the brightness density 164 of the background 17 and the brightness density 161 of the mold 92. When there is a pixel brighter than the threshold value 167 of the brightness density set on the inspection line (scanning line) for defect inspection, it is possible to detect that there is a foreign matter defect between leads 98 at the coordinate position. is there.

FIG. 19 is an explanatory diagram showing a method for detecting foreign matter defects between leads when the image input method using transmitted illumination is used. FIG. 19A shows an image input method using transmitted illumination. In the image input method described so far, the 2048 camera 9 is installed in the same direction as the illumination device 7 with respect to the semiconductor package 1, and captures the reflected light image of the semiconductor package 1. On the other hand, in the image input method using transmitted illumination shown in FIG. 19A, the 2048 camera 9 is installed in the direction opposite to the illumination device 7 with the semiconductor package 1 in between and images the shadow of the semiconductor package 1. That is, in the image input method using transmitted illumination in FIG. 19A, the semi-opaque body 170, the illumination device 7 installed on the semi-opaque body 170, and the 2048 camera 9 installed on the lower portion of the semi-opaque body 170. Is used, the semiconductor package 1 positioned on the semi-opaque body 170 is illuminated from above by the illumination device 7, and the shadow of the semiconductor package 1 dropped on the semi-opaque body 170 is imaged by the 2048 camera 9.

Therefore, the image 171 of the shadow of the semiconductor package 1 picked up by the 2048 camera 9 is shown in FIG.
As shown in, the shadow 1 of the lead 91 of the semiconductor package 1
The brightness density of 72 and the shadow density 173 of the mold 92 are low, and the brightness density 180 of the background 175 is high. Therefore, in the entire image 171, each lead 9
It is possible to detect the position 1 (coordinate), and it is also possible to draw an inspection line (inter-lead foreign matter defect inspection line) 176 for detecting the inter-lead foreign matter defect between adjacent leads. Further, the inter-lead foreign matter defect 98 of the semiconductor package 1
Also casts a shadow on the semi-opaque body 170, and the brightness density 179 of the shadow 174 of the inter-lead foreign matter defect 98 is lower than the brightness density 180 of the background 175.

Therefore, if the inter-lead foreign matter defect inspection line 176 is set between the adjacent leads 91, the inter-lead foreign matter defect 9
The brightness density distribution on the inspection line 176 (ab) between adjacent leads without 8 is the background 17 as shown in (c) of FIG.
The brightness density distribution has a constant value consisting of only the brightness density 180 of 5. On the other hand, the brightness density distribution on the inspection line 176 (cd) between the adjacent leads having the inter-lead foreign substance defect 98 is as shown in FIG. The shadow density 174 of the inter-lead foreign matter defect 98 has a low brightness density 179, which is the brightness density distribution. Therefore, an intermediate brightness density between the brightness density 180 of the background 175 and the brightness density 179 of the shadow 174 of the inter-lead foreign matter defect 98 is set to the threshold 1 for the inter-lead foreign matter defect determination.
If set as 81, the inter-lead foreign matter defect inspection line 176
If even one pixel has a pixel lower (darker) than the set threshold value 181 it is possible to detect that there is a foreign matter defect between leads 98 at that coordinate position.

As described above, in the image input method for picking up the image of the shadow of the semiconductor package 1 shown in FIG. 19, as in the image input method for picking up the reflected light image of the semiconductor package 1 shown in FIG. It is possible to detect the defect 98.

[0095]

As described above, according to the present invention, the semiconductor I
When conducting inspections such as lead shape inspections, mold shape inspections, lead surface inspections, mold surface inspections, mark inspections, inter-lead foreign material inspections, etc. on C packages or other electronic parts, especially when there are many inspection items, from the 2048 camera Images of semiconductor IC packages or other electronic components that have been taken in can be simultaneously stored in an image memory for each of a plurality of image processing boards, and a DSP that is a processing unit can be provided for each of a plurality of image processing boards so that each DSP can have the same image. Since it is possible to perform parallel inspections, it is possible to perform different types of inspections in parallel, such as changing the inspection items for each image processing board, making it possible to perform high-speed image processing and semiconductor package appearance inspections for the entire device. Can be done at.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a semiconductor package visual inspection device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a procedure of moving a semiconductor package in a mechanism section of the semiconductor package visual inspection device of FIG.

FIG. 3 is an explanatory diagram showing an example of a semiconductor package that is an object to be inspected.

FIG. 4 is a perspective view showing a positional relationship between an object to be inspected and a 2048 camera according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of an image input method according to an embodiment of the present invention and the structure of an optical system thereof.

6 is an explanatory diagram showing a reflection state of a background (inspection stage) in the optical system of FIG.

FIG. 7 is an explanatory diagram showing a configuration of a 2048 camera according to an embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a 2048 camera controller board according to an embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a 2048 DSP substrate according to an embodiment of the present invention.

FIG. 10 is an explanatory diagram showing process sharing and the like of each unit of the second inspection unit according to the embodiment of the present invention.

FIG. 11 is an explanatory diagram showing an upper surface image and a side surface image of a gull wing type semiconductor package which is an example of an object to be inspected in the embodiment of the present invention, and a brightness density distribution on a scanning line drawn on these images. Is.

FIG. 12 is an explanatory diagram showing an example of a processing flow for detecting foreign matter defects between leads in the second inspection unit (upper surface inspection unit) according to the embodiment of the present invention.

13 is an explanatory diagram showing details of a detection method in step 2 in the processing flow of FIG.

FIG. 14 is an explanatory diagram showing details of the detection method in step 3 in the processing flow of FIG. 12;

FIG. 15 is an explanatory diagram showing an example of a processing flow for detecting foreign matter defects between leads in the first inspection unit (side surface inspection unit) according to the embodiment of the present invention.

FIG. 16 is an explanatory diagram showing another example of a processing flow for detecting foreign matter defects between leads in the second inspection unit (upper surface inspection unit) according to the embodiment of the present invention.

FIG. 17 is an explanatory diagram showing another example of a processing flow for detecting foreign matter defects between leads in the first inspection unit (side surface inspection unit) according to the embodiment of the present invention.

FIG. 18 shows top and side images of a J-lead type semiconductor package which is another example of the object to be inspected in the embodiment of the present invention, and the brightness density distribution on the scanning line drawn on these images. It is an explanatory view shown.

FIG. 19 is an explanatory diagram showing another example of the image input method and the structure of the optical system according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor package (inspection object) 2 Image processing device 3 Mechanism part 4 Mechanism control part 5 Operation display part 6 Input / output terminal 7 Lighting device 9 Image capturing means (2048 camera) 10 Monitor TV 11 Loader 12 Lead correction part 13 Inspection part 14 Unloader 15 Rotational Moving Unit 16 Conveyance Reversing Unit 17 Inspection Stage (Background) 21 System Bus 22 CPU Board 23 2048 Camera Controller Board 24 2048 DSP Board 25 Lighting Controller & I / O Board 26 Hard Disk Device 27 Floppy Disk Device 28 DC Stabilization Power Supply 29 Image bus 30 Lens 31 Galvano motor 32 Galvano mirror 33 Linear sensor 41 Clock generation circuit 42 Frequency division circuit 43 Galvano data memory address generation circuit 44 System bus I / F 45 Selector 46 Gal Data memory 47 Selector 48 D / A conversion circuit 49 Galvano amplifier 50 Camera I / F 51 A / D conversion circuit 52 Image bus I / F 53 Image memory address generation circuit 61 Local bus 62 Image memory 63 Processing unit (DSP) 64 Program memory 65 Data memory 66 Dual port memory 67 System bus I / F 68 Image bus I / F 69 Video RAM 70 Monitor bus I / F 72 Monitor bus 81 Clock 82 Mirror control signal 83 Image signal 84 Image data 91 Read 92 Mold 98 Foreign matter between leads

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Shirakawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Production Engineering Laboratory, Hitachi, Ltd. (72) Inventor Tetsuji Yokouchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Incorporated company Hitachi, Ltd., Production Engineering Laboratory (72) Inventor Hiroshi Takahashi 3247, 3 Yagibashi Higashi, Hanazawa, Yonezawa City, Yamagata Prefecture Inside Hitachi Yonezawa Electronics Co., Ltd. (72) Inventor Sadao Yoshida, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture 292, Machi Co., Ltd., Production Engineering Research Laboratory, Hitachi, Ltd. (72) Inventor, Tatsuo Sugimoto, 5-20-1, Kamimizumotocho, Kodaira-shi, Tokyo Inside Hitachi, Ltd. Musashi Factory

Claims (11)

[Claims] 1. An image capturing means for capturing an image of an inspection object, a plurality of image memories for storing the same image of the inspection object captured by the image capturing means, and one-to-one correspondence with the plurality of image memories. And a plurality of processing units for
An image processing apparatus, wherein different kinds of inspections are performed in parallel by using images in the image memory corresponding to each of the plurality of processing units. 2. The image processing board according to claim 1, wherein the one image memory and one processing unit corresponding to the image memory in a one-to-one correspondence are arranged on the same image processing board. A bus that can have multiple units,
An image processing apparatus comprising a CPU board on the bus. 3. The image processing board according to claim 1, wherein a program memory is provided, and an external storage device that can be controlled by a CPU is provided, and the external storage device stores inspection programs for a plurality of types of inspected objects. ,
An image processing apparatus, wherein an inspection program of one kind is downloaded from the external storage device to the program memory. 4. An image capturing means capable of setting an image capturing range of an object to be inspected, an image memory for storing an image captured by the image capturing means, and a CPU for controlling inspection.
And a memory controllable by the CPU, the correspondence between the type of the inspection object and the image capturing range is stored in advance in the memory, and the image capturing range corresponding when the type of the inspection object is designated is stored. CPU to capture the image of the inspection object
An image processing apparatus, characterized in that the image control means controls the image capturing means. 5. An image of an object to be inspected is captured by the image capturing means, and the same image of the object to be inspected captured by the image capturing means is stored in a plurality of image memories, respectively, and one-to-one with the plurality of image memories. In the image processing method, different types of inspections are performed in parallel for each of a plurality of corresponding processing units using the images in the corresponding image memory. 6. The image processing board according to claim 5, wherein the one image memory and one processing unit corresponding to the image memory in a one-to-one correspondence are arranged on the same image processing board. A bus that can have multiple units,
An image processing method characterized in that a CPU substrate is provided on the bus. 7. The program memory according to claim 6, wherein a program memory is provided in the image processing board, and an external storage device controllable by a CPU is provided, and the external storage device stores inspection programs for a plurality of types of inspection objects. ,
An image processing method, wherein an inspection program of one kind is downloaded from the external storage device to the program memory. 8. An image capturing means capable of setting an image capturing range of an object to be inspected, an image memory for storing an image captured by the image capturing means, and a CPU for controlling inspection.
Is provided with a controllable memory, the correspondence between the inspected product type and the image capturing range is stored in advance in this CPU controllable memory, and when the inspected product type is designated, the corresponding image is displayed. An image processing method, wherein the CPU controls the image capturing means so as to capture an image of an inspection object within a capturing range. 9. The image processing apparatus according to claim 1, 2, 3 or 4 or the image processing method according to claim 5, 6, 7 or 8 is used to capture an external image of a semiconductor package as an inspection object. A semiconductor package visual inspection device characterized by parallel processing. 10. A means for capturing an image of a semiconductor package, an image memory for storing the image captured by the image capturing means, and an image processing means for performing various image processing using the image stored in the image memory. A semiconductor package visual inspection device having, wherein the lead position of the semiconductor package is detected by the image processing means, an inspection line is set between adjacent leads, and the brightness density on the inspection line is less than the set brightness density. A semiconductor package visual inspection device characterized in that when a pixel is bright or dark, it is detected as a foreign matter defect between leads. 11. A means for capturing an image of a semiconductor package, an image memory for storing the image captured by the image capturing means, and an image processing means for performing various image processing using the image stored in the image memory. A semiconductor package visual inspection device having, wherein the image processing means detects the entire position and inclination of the semiconductor package, and sets inspection lines between the leads of the semiconductor package stored in the image memory from CAD data of the semiconductor package, A semiconductor package visual inspection device characterized in that when the brightness density on the inspection line is brighter or darker than a set brightness density, it is detected as an inter-lead foreign matter defect.