JPH0399251A - Mounted state recognizing apparatus - Google Patents
Mounted state recognizing apparatusInfo
- Publication number
- JPH0399251A JPH0399251A JP1235784A JP23578489A JPH0399251A JP H0399251 A JPH0399251 A JP H0399251A JP 1235784 A JP1235784 A JP 1235784A JP 23578489 A JP23578489 A JP 23578489A JP H0399251 A JPH0399251 A JP H0399251A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- image
- lighting
- substrate
- image data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract 7
- 238000003384 imaging method Methods 0.000 claims description 6
- 230000015654 memory Effects 0.000 abstract description 11
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 7
- 238000007689 inspection Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- 239000000284 extract Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 208000003464 asthenopia Diseases 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012733 comparative method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は、例えば回路基板に実装されるチップ部品の脱
落や位置ずれなどの実装状態を認識する実装状態認識装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a mounting state recognition device that recognizes a mounting state such as dropping or misalignment of a chip component mounted on a circuit board, for example.
(従来の技術)
家電機器やオフィスオートメーション(OA)機器など
の電子機器は小型化が進んでおり、これに伴い各電子機
器に用いられる回路基板も小型化されている。例えば、
リード線付き回路基板に代わってチップ化された小型の
抵抗やコンデンサなどが実装可能な回路基板が用いられ
ている。そして、現在ではこのような実装部品の小型化
により回路基板への高密度実装が要求されている。(Prior Art) Electronic devices such as home appliances and office automation (OA) devices are becoming smaller and smaller, and along with this, the circuit boards used in each electronic device are also becoming smaller. for example,
Instead of a circuit board with lead wires, a circuit board on which small chipped resistors, capacitors, etc. can be mounted is used. Nowadays, due to the miniaturization of such mounted components, there is a demand for high-density mounting on circuit boards.
チップ部品などの回路基板への実装は、先ず予め所定の
配線パターンが形戊された回路基板にチップ部品を実装
装置により自動的に仮実装し、次にはんだ付け装置など
ではんだ付けを行って終了する。ところが、かかる実装
では、チップ部品にしばしば脱落や位置ずれなどが生じ
ており、これがはんだ付け終了の後に検出された場合、
その修.正に多大な労力を費さなければならない。そこ
で、チップ部品の脱落や位置ずれなどの検査が行われて
いる。When mounting chip components on a circuit board, the chip components are first automatically temporarily mounted on a circuit board on which a predetermined wiring pattern has been formed using a mounting device, and then soldered using a soldering device. finish. However, in such mounting, chip components often fall off or become misaligned, and if this is detected after soldering is completed,
That repair. You really have to put in a lot of effort. Therefore, inspections are conducted to check for chip components falling off, misalignment, etc.
この検査は作業員の目視により行われており、このため
検査に多くの人員が必要であり、そのうえ複雑な回路基
板上に複数のチップ部品が実装されているので検査ミス
が多くなる。さらに検査作業は細かくかつ一日中行うの
で眼球疲労が生じて健康管理の面にも問題が生じている
。This inspection is performed visually by a worker, which requires a large number of personnel.Furthermore, since a plurality of chip components are mounted on a complex circuit board, there are many inspection errors. Furthermore, the detailed examination work is done all day long, which causes eye fatigue and poses health management problems.
このようなことから実装状態の検査を画像処理技術を用
いる方法が行われている。この方法には、光切断法、パ
ターン比較法及び斜光陰影法があり、このうち光切断法
は切断光を回路基板に対して斜め方向からスキャンさせ
、このとき回路基板の上方から見たときにチップ部品の
高さにより切断光に段差が生じることを利用する技術で
ある。又、パターン比較法は予め記憶された良品の回路
基板の画像を用意し、この画像に対して検査する回路基
板の画像情報例えば濃淡レベルや色を画素ごとに比較す
る技術である。さらに、斜光陰影法は回路基板の斜め上
方でこの回路基板を介して対向する各方向からそれぞれ
光を照射し、これら光を照射したときの各画像データの
差からチ・ンプ部品の影情報を抽出してチップ部品の状
態を検査する技術である。例えば第8図はA方向から光
を回路基板に対して照射したときの画像データを示して
おり、この画像データにおいてx−x ”部分の濃淡レ
ベルは第9図に示すように回路基板上でチ・ノブ部品の
影の無い部分が最も明かるく、次に回路基板上で影のあ
る部分、そして配線パターン上で影のある部分が最も暗
くなっている。又、図示しないがB方向から光を回路基
板上に照射したときの画像データが求められ、これら画
像データの差からチップ部品の影のデータが抽出される
。For this reason, a method using image processing technology is being used to inspect the mounting state. This method includes the light cutting method, the pattern comparison method, and the oblique light shadow method. Among these methods, the light cutting method scans the cutting light obliquely with respect to the circuit board, and at this time, when viewed from above the circuit board, This technology takes advantage of the fact that there are steps in the cutting light depending on the height of the chip component. The pattern comparison method is a technique in which a pre-stored image of a good circuit board is prepared and image information of the circuit board to be inspected, such as gradation level and color, is compared for each pixel with this image. Furthermore, in the oblique light shading method, light is irradiated diagonally above the circuit board from each direction facing each other through the circuit board, and shadow information of the chip components is obtained from the difference in image data when these lights are irradiated. This is a technology that extracts and inspects the condition of chip components. For example, Fig. 8 shows image data when the circuit board is irradiated with light from direction A, and in this image data, the gray level of the section x-x'' is as shown in Fig. 9. The part with no shadow on the knob part is the brightest, followed by the part with a shadow on the circuit board, and the part with a shadow on the wiring pattern is the darkest.Also, although not shown, the light from direction B is the brightest. Image data is obtained when the light is irradiated onto the circuit board, and data on the shadow of the chip component is extracted from the difference between these image data.
しかしながら、上記各方法のうち光切断法では切断光を
回路基板全面或いは一部にスキャンさせなければならな
いので、例えば角型のチップ部品の回転ずれを検出する
ためには1部品当たり2回以上照射方向を変えなければ
ならず検査に時間がかかる。又、パターン比較法では各
画素の比較を多数行わなければならず検査に時間がかか
る。さらに、この比較法では回路基板上の配線パターン
,レジストの塗布状態,チップ部品の表面状態の影響を
受けて検査精度及び信頼性が低下する。さらに、斜光陰
影法ではチップ部品の影情報を利用することで高速に検
査ができるが、チップ部品が隣接して実装されていたり
、又回路基板の表面状態によりチップ部品の影情報が欠
落することがある。However, among the above methods, the optical cutting method requires the cutting light to scan the entire surface or part of the circuit board, so in order to detect rotational deviation of a square chip component, for example, it is necessary to irradiate each component two or more times. The inspection takes time because the direction has to be changed. Furthermore, in the pattern comparison method, each pixel must be compared many times, and inspection takes time. Furthermore, in this comparative method, the inspection accuracy and reliability are affected by the wiring pattern on the circuit board, the coating state of the resist, and the surface state of the chip component. Furthermore, although the oblique shading method enables high-speed inspection by using the shadow information of chip components, the shadow information of the chip components may be missing due to the chip components being mounted adjacent to each other or the surface condition of the circuit board. There is.
例えば、第10図に示すように回路基板1上に各チップ
部品2,3が隣接して実装されている場合、各方向C,
Dから光を照射すると、第11図に示すように各チップ
部品2,3との間の影情報が欠落する。又、上記第8図
及び第9図に示すように回路基板上の影のある部分と無
い部分との明かるさの差が僅しか無い場合に影の情報を
抽出できずに欠落することがある。For example, when the chip components 2 and 3 are mounted adjacent to each other on the circuit board 1 as shown in FIG.
When light is irradiated from D, shadow information between each chip component 2 and 3 is lost as shown in FIG. In addition, as shown in Figures 8 and 9 above, when there is only a slight difference in brightness between areas with and without shadows on the circuit board, shadow information may not be extracted and may be missing. be.
(発明が解決しようとする課題)
以上のように光切断法及びパターン比較法では検査に時
間がかかり、又斜光陰影法ではチップ部品が隣接して実
装されていたり、又回路基板の表面状態によりチップ部
品の影情報が欠落することがある。(Problems to be Solved by the Invention) As described above, the light cutting method and the pattern comparison method take a long time to inspect, and the oblique light and shadow method requires chip parts to be mounted adjacent to each other, or the surface condition of the circuit board. Shadow information of chip parts may be missing.
そこで本発明は、チップ部品が隣接して実装されていた
り、又回路基板の表面状態の影響を受けずに高速でチッ
プ部品の実装状態を認識できる実装状態認識装置を提供
することを目的とする。SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a mounting state recognition device that can recognize the mounting state of chip components at high speed without being affected by the fact that chip components are mounted adjacent to each other or the surface condition of a circuit board. .
[発明の構成】
(課題を解決するための手段)
本発明は、基板上に実装された被検査部品の実装状態を
認識する実装状態認識装置において、基板の斜め上方で
互いに基板を介して対向する位置に配置された第1及び
第2照明装置と、基板の下方に配置された第3照明装置
と、これら第1乃至第3照明装置をそれぞれ別々に点灯
させる照明切換手段と、基板の上方に配置されてこの基
板を撮像する撮像装置と、照明切換手段により第1及び
第2照明装置がそれぞれ点灯されたときの撮像装置から
の斜光陰影像の各画像信号及び第3照明もチップ部品1
1の実装状態を認識できる。すなわち、斜光陰影画像デ
ータD+,DIでは配線パターン上での影の部分が良く
現われ、又透過画像データD,ではチップ部品11及び
配線パターンの部分で光が透過せず回路基板12の部分
で光が透過する。従って、これら斜光陰影画像データD
,,D,及び透過画像データDkの各欠点を互いに打消
すように画像処理することになり、これにより各チップ
部品11.11が隣接していても各チップ部品11.1
1の輪郭像を確実に抽出できるとともに回路基板12の
配線パターン等の表面状態に影響されずにチップ部品1
1の実装状態を認識できる。[Structure of the Invention] (Means for Solving the Problems) The present invention provides a mounting state recognition device that recognizes the mounting state of parts to be inspected mounted on a board. a third lighting device located below the board; a lighting switching means for separately lighting the first to third lighting devices; and a lighting switch located above the board. An imaging device disposed in the chip component 1 to take an image of this board, image signals of oblique light and shadow images from the imaging device when the first and second lighting devices are respectively turned on by the lighting switching means, and a third lighting device are also connected to the chip component 1.
The implementation status of 1 can be recognized. That is, in the oblique light shadow image data D+ and DI, the shadow portion on the wiring pattern clearly appears, and in the transparent image data D, light does not pass through the chip component 11 and the wiring pattern portion, but light does not pass through the circuit board 12 portion. is transmitted. Therefore, these oblique light and shadow image data D
.
It is possible to reliably extract the outline image of the chip component 1 and to extract the outline image of the chip component 1 without being affected by the surface condition of the wiring pattern of the circuit board 12.
The implementation status of 1 can be recognized.
なお、本発明は上記一実施例に限定されるものでなくそ
の主旨を逸脱しない範囲で変形しても良い。例えば、上
記一実施例では各画像メモリ21,22にそれぞれ画像
データが記憶されてから減算処理を行っているが、一方
の画像メモリに画像データを記憶してこの画像データを
順次読み出しながら他方のディジタル画像信号と減算処
理を行ってもよく、又斜光陰影画像データと透過画像デ
ータとを加算してから2値化処理しているが、斜光陰影
画像データと透過画像データとをそれぞれ2値化処理し
てから加算処理しても良い。さらに、減算回路25の出
力端子に画像メモリを接続して減算画像データを一旦記
憶し、この後に減算画像データを加算回路26に送るよ
うにしても良い。Note that the present invention is not limited to the above-mentioned embodiment, and may be modified without departing from the spirit thereof. For example, in the embodiment described above, subtraction processing is performed after image data is stored in each of the image memories 21 and 22, but while image data is stored in one image memory and sequentially read out, the image data is Subtraction processing may be performed on the digital image signal, or the oblique light and shadow image data and the transmission image data are added and then binarized, but the oblique light and shadow image data and the transmission image data are each binarized. The addition process may be performed after processing. Furthermore, an image memory may be connected to the output terminal of the subtraction circuit 25 to temporarily store the subtraction image data, and then the subtraction image data may be sent to the addition circuit 26.
又、投影回路に送る画像データは2値化処理しているが
、この画像データは多値化のままでもよい。Further, although the image data sent to the projection circuit is subjected to binarization processing, this image data may remain multivalued.
[発明の効果]
以上詳記したように本発明によれば、チップ部品が隣接
して実装されていたり、又回路基板の表面状態の影響を
受けずに高速でチップ部品の実装状態を認識できる実装
状態認識装置を提供できる。[Effects of the Invention] As detailed above, according to the present invention, it is possible to recognize the mounting state of chip components at high speed without being affected by the surface condition of a circuit board or when chip components are mounted adjacent to each other. A mounting state recognition device can be provided.
第1図乃至第7図は本発明に係わる実装状態認識装置の
一実施例を説明するための図であって、第1図は構威図
、第2図及び第3図は斜光陰影画像データの模式図、第
4図は透過画像データの模式図、第5図は減算画像デー
タの模式図、第6図は加算画像データの模式図、第7図
は投影処理を説明するための図、第8図乃至第11図は
従来技術を説明するための図である。
10・・・XYテーブル、11・・・チップ部品、12
・・・回路基板、13・・・XYテーブル駆動回路、1
4・・・第1照明装置、15・・・第2照明装置、16
・・・第3照明装置、17・・・照明切換え回路、18
・・・撮像装置、19・・・A/D変換回路、20・・
・認識部、21,22.23・・・画像メモリ、24・
・・タイミング回路、25・・・減算回路、26・・・
加算回路、27・・・2値化回路、28・・・画像メモ
リ、2つ・・・投影回路、30・・・演算制御回路、3
1・・・表示回路。1 to 7 are diagrams for explaining an embodiment of the mounting state recognition device according to the present invention, in which FIG. 1 is a composition diagram, and FIGS. 2 and 3 are oblique light and shadow image data. 4 is a schematic diagram of transparent image data, FIG. 5 is a schematic diagram of subtraction image data, FIG. 6 is a schematic diagram of addition image data, and FIG. 7 is a diagram for explaining projection processing. FIG. 8 to FIG. 11 are diagrams for explaining the prior art. 10...XY table, 11...chip parts, 12
...Circuit board, 13...XY table drive circuit, 1
4... First lighting device, 15... Second lighting device, 16
...Third lighting device, 17...Lighting switching circuit, 18
...Imaging device, 19...A/D conversion circuit, 20...
・Recognition unit, 21, 22. 23... Image memory, 24.
...Timing circuit, 25...Subtraction circuit, 26...
Addition circuit, 27... Binarization circuit, 28... Image memory, two... Projection circuit, 30... Arithmetic control circuit, 3
1...Display circuit.
Claims (1)
実装状態認識装置において、前記基板の斜め上方で互い
に前記基板を介して対向する位置に配置された第1及び
第2照明装置と、前記基板の下方に配置された第3照明
装置と、これら第1乃至第3照明装置をそれぞれ別々に
点灯させる照明切換手段と、前記基板の上方に配置され
てこの基板を撮像する撮像装置と、前記照明切換手段に
より前記第1及び第2照明装置がそれぞれ点灯されたと
きの前記撮像装置からの斜光陰影像の各画像信号及び前
記第3照明装置が点灯されたときの前記撮像装置からの
透過像の画像信号を受けてこれら斜光陰影画像データ及
び透過像の各画像信号を画像処理して前記被検査部品の
実装状態を認識する認識手段とを具備したことを特徴と
する実装状態認識装置。A mounting state recognition device that recognizes a mounting state of a component to be inspected mounted on a board, comprising: first and second lighting devices disposed diagonally above the board and facing each other with the board interposed therebetween; a third lighting device disposed below the substrate; a lighting switching device for turning on each of the first to third lighting devices separately; an imaging device disposed above the substrate for capturing an image of the substrate; Each image signal of an oblique light shadow image from the imaging device when the first and second lighting devices are each turned on by the lighting switching means, and a transmitted image from the imaging device when the third lighting device is turned on. 1. A mounting state recognition apparatus, comprising: recognition means for receiving the image signals of the oblique light and shadow image data and the transmission image and performing image processing to recognize the mounting state of the component to be inspected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1235784A JPH0399251A (en) | 1989-09-13 | 1989-09-13 | Mounted state recognizing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1235784A JPH0399251A (en) | 1989-09-13 | 1989-09-13 | Mounted state recognizing apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0399251A true JPH0399251A (en) | 1991-04-24 |
Family
ID=16991198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1235784A Pending JPH0399251A (en) | 1989-09-13 | 1989-09-13 | Mounted state recognizing apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0399251A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5667205A (en) * | 1995-03-22 | 1997-09-16 | Yamashita Rubber Kabushiki Kaisha | Fluid-sealed type anti-vibration rubber device |
EP1154227A1 (en) * | 2000-05-10 | 2001-11-14 | FUJI MACHINE Mfg. Co., Ltd. | Edge detecting method and edge detecting apparatus |
US7416173B2 (en) | 2004-05-24 | 2008-08-26 | Tokai Rubber Industries, Ltd. | Pneumatically switchable type fluid-filled engine mount |
JP2018124075A (en) * | 2017-01-30 | 2018-08-09 | 名古屋電機工業株式会社 | Inspection information display device, inspection information display method and inspection information display program |
-
1989
- 1989-09-13 JP JP1235784A patent/JPH0399251A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5667205A (en) * | 1995-03-22 | 1997-09-16 | Yamashita Rubber Kabushiki Kaisha | Fluid-sealed type anti-vibration rubber device |
EP1154227A1 (en) * | 2000-05-10 | 2001-11-14 | FUJI MACHINE Mfg. Co., Ltd. | Edge detecting method and edge detecting apparatus |
US6617602B2 (en) | 2000-05-10 | 2003-09-09 | Fuji Machine Mfg. Co., Ltd. | Edge detecting apparatus having a control device which selectively operates the light emitting elements |
US7416173B2 (en) | 2004-05-24 | 2008-08-26 | Tokai Rubber Industries, Ltd. | Pneumatically switchable type fluid-filled engine mount |
JP2018124075A (en) * | 2017-01-30 | 2018-08-09 | 名古屋電機工業株式会社 | Inspection information display device, inspection information display method and inspection information display program |
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