JPH0619703A - Data processor - Google Patents

Abstract

PURPOSE:To inhibit a stack operation to a storage area except for a stack area which can be used so as to prevent the destruction of the stored content of the stack area except for that of the stack area which can be used. CONSTITUTION:A minimum address value (a) showing the upper limit of a stack area 201 is held in a limit point register 13, and a maximum address value (a+x) showing the lower limit in a base register 16. At the time of writing by the stack operation, the holding value of a stack pointer register 11 whose value is reduced and updated as data is written is compared with the holding value of the limit point register 13 in a comparator 14. At the time of reading, the holding value of the stack pointer register 11 is compared with the holding value of the base register 16 in a comparator 17. When the compared results of the comparators 14 and 17 coincide, a signal to a control circuit 15 becomes active and the control circuit 15 executes an error processing by interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device capable of reading / writing data by stack operation.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a main configuration of a conventional data processing device capable of reading / writing data by stack operation. In the figure, 10B is a data processing unit that executes program instructions including reading / writing of data by stack operation, and 20 is a data processing unit 10.
B is a storage area that can be used. In the storage area 20, the address spaces of the addresses “a” to “a + x” are allocated as the stack area 201, and the address space 202 below the address “a” and the address space 203 above the address “a + x” are other than the stack. This is the area used for the purpose. In the stack area 201, the address "a +
The stack area 201A in use is from x-b "to" a + x "
Indicates.

The stack pointer register 11 holds a stack pointer value indicating the address of the stack area 201, and the adder / subtractor circuit 12 reads the held value of the stack pointer register 11 and sets the held value to "1" depending on whether reading or writing. "Is added or subtracted to update the value held in the stack pointer register 11. The stack limit point register 13 holds the minimum address value (= a) indicating the upper limit of the address space of the stack area 201, and the comparator 14 compares the hold value of the stack pointer register 11 and the hold value of the limit point register 13. The comparison is made, and when the comparison results match, the signal to the control circuit 15 is activated. When the signal from the comparator 14 becomes active, the control circuit 15 outputs an interrupt signal through a path (not shown) and executes error processing.

Next, the operation will be described. For example, when the data processing unit 10B executes a program stored in the storage area 202 and the program includes a read / write instruction of data by stack operation,
The data processing unit 10B has a control circuit 15 via a path (not shown).
The following stack operations are performed under the control of. When writing data by stack operation, the stack pointer value held by the stack pointer register 11 is read to the adder / subtractor circuit 12, the value is decremented and updated, and the data is written to the address position specified by the updated stack pointer value. .

On the contrary, when reading data by stack operation, data is read by using the stack pointer value held by the stack pointer register 11 as an address, the value held in the stack pointer register 11 is read by the adder / subtractor circuit 12, and the value is incremented. Then, the value held in the stack pointer register 11 is updated.

That is, as shown in FIG. 4, every time data is written by a stack operation, the stack area in use is in use.
201A expands toward an area having a smaller address value and the value held in the stack pointer register 11 becomes smaller. Also, each time data is read by the stack operation, the stack area 201A in use is shortened toward the area with a larger address and the value held in the stack pointer register 11 increases.

Therefore, when writing data, if there is more write data than expected, the stack area 201A in use is in use.
May exceed the stack area 201 and reach the address space 202, and there is a risk of destroying the storage contents of the address space 202 used for other purposes. Therefore, in order to prevent this, the minimum address value (= a) of the stack area 201 indicating the limit of the address space that can be used as a stack is held in the stack limit point register 13, and every time data is written by the stack operation, The comparator 14 compares the updated holding value of the stack pointer register 11 (address value of data to be written) with the holding value of the stack limit point register 13, and as a result of the comparison, the holding value of the stack pointer register 11 and the stack limit. Point register
If the held value of 13 matches, the output signal of the comparator 14 is immediately activated, and the control circuit 15 receiving this signal performs error processing by interruption.

Incidentally, a data processing apparatus for executing a plurality of programs in parallel while switching them in a time division manner may have a plurality of stack pointer registers for independently managing stack operations for each program.

FIG. 5 is a block diagram showing a main structure of a conventional data processing apparatus having a plurality of stack pointer registers. In the figure, 11B and 21B are 8-bit stack pointer registers, 12B is an add / subtract circuit that updates all 8 bits of the value held in the stack pointer register 11B, and 22B is an add / subtract circuit that updates all 8 bits of the value held in the stack pointer register 21B. In the storage area 20, the address space of the addresses “a” to “a + x” is the stack area 201.
The address space other than the stack area 201 is an area used for purposes other than the stack.

In this case, an address space for writing / reading the stack area 201 by stack operation using the stack pointer register 11B and the addition / subtraction circuit 12B,
The stack pointer register 21B and the add / subtract circuit 22B are separated into an address space for writing / reading by stack operation, and the stack pointer register 11B
Set different initial values to and 21B. In FIG.
The initial value of stack pointer register 21B is larger than the initial value of stack pointer register 11B.

S1-1 to S1-5 are data written by stack operation using the stack pointer register 11B,
S2-1 to S2-4 indicate data written by the stack operation using the stack pointer register 21B.

Next, the operation will be described. Execute the program assigned to the storage area 20 other than the stack area 201, and add the stack pointer register 11 to this program.
When the write instruction by the stack operation using B is included, all 8 bits of the value held in the stack pointer register 11B are read into the adder / subtractor circuit 12B and the value is set to "1".
Only decrement and update, and write the data to the address position specified by the updated stack pointer value.

As shown in FIG. 5, the stack pointer register
Stack area 51 has a smaller address each time data is written from the one with a larger address to "S1-1", "S1-2", "S1-3", ... by stack operation using 11B and adder / subtractor circuit 12B. Stack pointer register 11
The retention value of B becomes smaller.

On the contrary, when reading data by stack operation, the data is read by using all 8 bits of the value held in the stack pointer register 11B as an address, and the addition / subtraction circuit 12B reads all 8 values held by the stack pointer register 11B.
The bit is read and the value is incremented by "1" to update the value held in the stack pointer register 11B.

When all 8 bits of the value held in the stack pointer register 11B is the address of the data "S1-5", the data is read each time the stack pointer register 11B and the adder / subtractor circuit 12B are used to read the data. Are sequentially read as "S1-5", "S1-4", "S1-3", ..., and the value held in the stack pointer register 11B increases.

The operation during stack operation using the stack pointer register 21B and the addition / subtraction circuit 22B is the same as the operation during stack operation using the stack pointer register 11B and the addition / subtraction circuit 12B.

[0017]

Since the conventional data processing device has the above-mentioned configuration, the above-mentioned data processing device has a stack point limit so as not to write data beyond the minimum address of the stack area at the time of writing. Although a register is provided, when data is read beyond the stack area due to a program mistake, etc., when reading, the operation progresses toward the direction where the address becomes larger than when writing. However, there is a risk that the data read from other than the stack area is updated and written to the original address, and the stored contents are destroyed.

Further, even if writing is not performed beyond the stack area, in the case of a data processing device having a plurality of stack pointer registers, one stack pointer register assigned to the side with the larger address is used.
If the data to be written by stack operation using 21B increases more than expected, the value held in stack pointer register 21B becomes smaller than the initial value of the other stack pointer register 11B, and the data is written by stack operation using stack pointer register 11B. There is a risk of destroying the stored data.

The present invention has been made in order to solve such a problem, and is used for the purpose other than the stack beyond the stack area at any time of writing / reading data by the stack operation. It is an object of the present invention to provide a data processing device that prevents the destruction of the storage contents of other stacks when operating the storage area or a plurality of stacks.

[0020]

A data processing apparatus according to a first aspect of the present invention is provided with a register for storing an address value indicating an upper limit and a lower limit of a stack area usable as a stack, and the address value and the stack pointer value are provided. It is characterized in that a stack operation exceeding the upper limit or the lower limit of the stack area is prohibited by comparing with.

In the data processor according to the second aspect of the present invention, some bits of the stack pointer values corresponding to the plurality of stacks are fixed to different values so that the stack pointer values do not match between the plurality of stacks. The feature is that the storage areas used for multiple stack operations are not overlapped.

In the data processor according to the third invention, the stack pointer values indicating the starting points of the areas where a plurality of stacks can be used are set to consecutive address values, and the stack pointer is used to indicate the next operation address. Set a predetermined value to add / subtract to the value to n so that each stack area has n
N addresses are allocated in a distributed manner, and n
The feature is that the storage areas used for individual stack operations are not overlapped.

[0023]

The data processing apparatus according to the first aspect of the present invention, when reading / writing data by stack operation,
The stack pointer value is compared with the address value that indicates the upper or lower limit of the stack area that can be used as a stack, and if the stack pointer value indicates that it is within the range of the stack area, read / write is executed. When specifying an address other than the stack area, read / write is prohibited.

A data processing device according to a second aspect of the present invention is a stack pointer in which when a plurality of stacks are selectively operated to read / write data in parallel, the value of some bits is fixed. The value does not match the stack pointer value of the other stack, and reading / writing is not performed on the other stack area.

In the data processor according to the third aspect of the present invention, when n stacks are selectively operated to read / write data in parallel, continuous address values are used as starting points of the stack area and read. Each time / write is performed, addition / subtraction is performed by n, and the next operation of read / write in each stack operation is performed at address positions with an address interval of n.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a block diagram showing the configuration of a first embodiment of a data processing device according to the present invention (hereinafter referred to as the present invention device). In the figure, the same parts as those of the conventional data processing apparatus shown in FIG.

In this embodiment, in addition to the conventional limit point register 13 that holds the minimum address value (= a) indicating the upper limit of the address space of the stack area 201, the stack area
Maximum address value (= a
+ X) is provided with a base register 16 for holding,
Stack pointer register 11 holding value and base register
A second comparator 17 for comparing the held value of 16 is provided, and an OR gate 18 is provided between the outputs of the first and second comparators 14 and 17 and the control circuit 15.

Next, the operation will be described. The stack area 201A that is in use when reading / writing data by the stack operation and writing data is the stack area.
The operation to prevent the memory contents of the address space 202 used for other purposes from being exceeded beyond the upper limit of 201 is
Since the operation is the same as that of the conventional data processing device shown in FIG. 4, description thereof will be omitted.

The base register 16 holds the maximum address value indicating the lower limit of the stack area 201, that is, the initial value of the stack pointer register 11. The second comparator 17 compares the value held in the stack pointer register 11 before updating (the address value of the data to be read) with the value held in the base register 16 each time data is read by stack operation.
If the comparison results match, the output of the second comparator 17 becomes active immediately. This indicates that the lower limit of the stack area 201 has been exceeded and the storage contents of another address space 203 used for another purpose have been read.

When the output of the second comparator 17 becomes active, the output of the OR gate 18 becomes active, and the control circuit 15 receiving this output performs error processing by interruption. When performing error processing, the control circuit 15 refers to the value held in the stack pointer register 11 to determine which of the output of the first comparator 14 and the output of the second comparator 17 has become active. And perform the corresponding error handling.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the device of the present invention having a plurality of stack pointer registers. 5, those parts that are the same as those in the conventional data processing device shown in FIG. 5 are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, 8-bit stack pointer registers 11A and 21A
The least significant bit of each is fixed to "0" and "1", respectively, and the adder / subtractor circuit 12A uses the stack pointer register 11A.
The upper 7 bits of the value held in the stack pointer register 21A are updated, and the addition / subtraction circuit 22A updates the upper 7 bits of the value held in the stack pointer register 21A.

In this case, the upper 7 bits of the initial values ("a + x-1" and "a + x") set in the stack pointer registers 11A and 21A at the time of writing data are the same value. Since the lowest is "0" and "1", all 8
The bits never match. That is, when there are two stack registers, the even address of the stack area 201 is used for stack operation using the stack pointer register 11A, and the odd address is used for stack operation using the stack pointer register 21A.

Next, the operation will be described. First, the stack operation using the stack pointer register 11A and the addition / subtraction circuit 12A will be described. When writing data by stack operation, the upper 7 bits of the stack pointer register 11A are read into the adder / subtractor circuit 12A, "1" is subtracted from the value, and the upper 7 bits of the value held in the stack pointer register 11A is updated and updated. Data is written with all 8 bits of the value held in the stack pointer register 11A including 7 bits as an address.

On the contrary, when reading data by stack operation, data is read by using all 8 bits of the stack pointer register 11A as an address, the upper 7 bits of the stack pointer register 11A is read by the adder / subtractor circuit 12A, and the value is set to "1". Add and update the upper 7 bits of stack pointer register 11A.

The operation at the time of stack operation using the stack pointer register 21A and the addition / subtraction circuit 22A is the same as that at the time of stack operation using the stack pointer register 11A and the addition / subtraction circuit 12A.

As shown in FIG. 2, at the time of writing data by stack operation using the stack pointer register 11A and the addition / subtraction circuit 12A, "S1-1", "S1-2", "S1-"
The data of 3 ", ... Is" a + x-1 "," a + x-3 ",
“A + x−5”, ... Are sequentially written in every other address, and the stack area in use extends above the stack area, and the value held in the stack pointer register 11A becomes smaller by “2”.

When reading data by stack operation using the stack pointer register 11A and the addition / subtraction circuit 12A, the data of "S1-5", "S1-4", "S1-3", ... Is "a + x-9". , "A + x-7", "a + x-"
The stack area in use, which is sequentially read from every other address such as 5 ", ... Is reduced to the lower part of the stack area, and the value held in the stack pointer register 11A increases by" 2 ".

Although the stack operation using two stack pointer registers has been described in the present embodiment, even if the number of stack pointer registers is three or more, a plurality of stacks can be obtained by increasing the number of bits of a fixed value. Can not overlap each other. For example, when four stack pointer registers are provided, the lower 2 bits are "00", "01", "10", "11".
You can fix each to.

In this embodiment, the case has been described in which only one storage area specified by one address value can be read and written at a time, but a plurality of storage areas specified by one address value can be read and written. This is also applicable to the case of reading and writing at once, and in that case, the position of the fixed bit may be set to a position other than the lower order for distinguishing a plurality of storage areas. For example, when two stack pointer registers are provided and four storage areas specified by one address value are read / written at once, the lower 2 bits of each stack pointer register are read / written at once.
Since the value cannot be fixed because it is a bit indicating the distinction between the two storage areas, the bits at positions higher than the third bit from the least significant are set to fixed values.

FIG. 3 is a block diagram showing a main configuration of a third embodiment of the device of the present invention having n stack pointer registers. The same parts as those of the conventional data processing apparatus and the second embodiment shown in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the initial values of the 8-bit stack pointer registers 11A, 21A, ..., N1A are consecutive address values "a + x-n + 1", "a + x-n + 2", ..., "a". is set to + x ”, and the adder / subtractor circuits 12A, 22A, n2A read all 8 bits of the value held in the stack pointer registers 11A, 21A, n1A, add / subtract“ n ”to this value, and add / subtract“ n ”to the stack pointer register 11A. Update the held value of, 21A, n1A.

That is, each stack pointer register 11A, 21
Since A and n1A are set to use every "n" address space of the stack area 201, stack areas used for n stack operations do not overlap each other.

Next, the operation will be described. The operation of reading / writing data by the stack operation is the same as the operation of the conventional data processing device shown in FIG. 5 except that the value to be added / subtracted at the time of updating is “n”, and therefore the description thereof is omitted.

As shown in FIG. 3, when writing data by stack operation using the stack pointer register 11A and the adder / subtractor circuit 12A, "S1-1", "S1-2", ...,
The data of "S1-n" is "a + x-n + 1", "a + x-2n + 1", ...,
The stack area in use, which is sequentially written in the addresses of every "a" and "n", extends above the stack area.
The value held in the stack pointer register 11A becomes smaller by "n".

When data is read by stack operation using the stack pointer register 11A and the addition / subtraction circuit 12A, the data of "S1-n", ..., "S1-2", "S1-1" are "a", ... , "A + x-2n + 1", "a + x-n + 1", ..., and the stack area in use, which is sequentially read from the address every "n", is reduced below the stack area. The value held in the stack pointer register 11A increases by "n".

Other stack pointer registers 21A, ..., n1A
, And the addition / subtraction circuit 22A, ..., N2A, the stack pointer register 11A and the addition / subtraction circuit 12
It is similar to the stack operation using A.

[0046]

As described above, the first device of the present invention compares the address value indicating not only the upper limit but also the lower limit of the stack area with the stack pointer value every time data is read / written by the stack operation. If they match with each other, read / write is prohibited, so that an excellent effect of preventing destruction of stored contents due to data reading from a storage area other than the stack area is achieved.

Further, the second device of the present invention fixes the same value even when some bits of the stack pointer values used for a plurality of stack operations are fixed to different values and the stack pointer value is increased or decreased. This prevents the storage areas used by a plurality of stack operations from overlapping and prevents the memory contents from being destroyed by another stack operation.

Furthermore, the third device of the present invention sets n stack pointer values used for n stack operations to consecutive address values, and sets the stack pointer value to "next" to indicate the next operation address. Since "n" is added and subtracted, the storage areas used by n stack operations do not overlap, and the excellent effect of preventing the destruction of storage contents by other stack operations is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a first embodiment of a device of the present invention.

FIG. 2 is a block diagram showing a main configuration of a second embodiment of the device of the present invention.

FIG. 3 is a block diagram showing a main configuration of a third embodiment of the device of the present invention.

FIG. 4 is a block diagram showing a main configuration of an example of a conventional data processing device.

FIG. 5 is a block diagram showing a main part configuration of another example of a conventional data processing device.

[Explanation of symbols]

 10A Data processing unit 11A, 21A, ..., n1A Stack pointer register 12A, 22A, ..., n2A Adder / subtractor circuit 16 Base register 17 Comparator 18 OR gate 20 Storage area 200 Stack area

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 4, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

As shown in FIG. 5, the stack pointer register
Each time data is written from the one with a larger address to "S1-1", "S1-2", "S1-3", ... by stack operation using 11B and adder / subtractor circuit 12B, the stack area is Extend to area Stack pointer register 11B
The holding value of becomes smaller.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

[0017]

Since the conventional data processing device has the above-mentioned configuration, the above-mentioned data processing device has a stack point limit so as not to write data beyond the minimum address of the stack area at the time of writing. Although a register is provided, when data is read beyond the stack area due to a program mistake, etc., when reading, the operation progresses toward the direction where the address becomes larger than when writing. , There is a risk that the data read from other than the stack area is updated and written to the original address, and the stored contents are destroyed.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

In this embodiment, the case has been described in which only one storage area specified by one address value can be read and written at a time, but a plurality of storage areas specified by one address value can be read and written. This is also applicable to the case of reading and writing at once, and in that case the position of the fixed bit may be set to a position other than the lower bit for distinguishing a plurality of storage areas. For example, when two stack pointer registers are provided and four storage areas specified by one address value are read / written at one time, the lower two bits of each stack pointer register are four storage areas to be read / written at one time. The value cannot be fixed because it is a bit indicating the distinction between the two. Therefore, the bits at positions higher than the third bit from the least significant bit are set to fixed values.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

[0046]

As described above, the first device of the present invention compares the address value indicating not only the upper limit but also the lower limit of the stack area with the stack pointer value every time data is read / written by the stack operation. If they match with each other, reading / writing is prohibited, so that an excellent effect of preventing destruction of stored contents by reading / writing data from a storage area other than the stack area is achieved.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction content]

Further, the third device of the present invention sets the starting points of the n stack pointer values used for n stack operations to consecutive address values and indicates the next operation address. Since "n" is added / subtracted to / from the stack pointer value as appropriate, the storage areas used for n stack operations do not overlap with each other, and the excellent effect of preventing the destruction of the storage contents by other stack operations is achieved.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of symbols] 10A Data processing unit 11A, 21A, ..., n1A Stack pointer register 12A, 22A, ..., n2A Adder / subtractor circuit 16 Base register 17 Comparator 18 OR gate 20 Storage area 201 Stack area

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masayuki Hata 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corp. Kita Itami Works

Claims (3)

[Claims] 1. Data reading / reading by stack operation
A first register that holds an address value that indicates the upper limit of the address space that can be used as a stack in a data processing device that adds and subtracts a predetermined value to and from a stack pointer value when writing, and indicates an address to be operated next A second register for holding an address value indicating the lower limit of the address space, a means for comparing the stack pointer value and the held value of the first or second register depending on whether reading or writing, A data processing device comprising: means for prohibiting reading / writing of data according to a result. 2. A data processing device for reading / writing data by selectively operating a plurality of stacks, and adding / subtracting a predetermined value to / from a stack pointer value corresponding to each stack to indicate an address to be operated next. A data processing device, wherein some bits of the stack pointer value are fixed to values different from each other. 3. Data reading / writing is performed by selective operation of n (n is a natural number of 2 or more) stacks, and a predetermined value is added / subtracted to / from a stack pointer value corresponding to each stack to be operated next. In the data processing device that indicates the address to be used, the stack pointer value indicating the start point of the usable area of each stack is set to consecutive address values, and the predetermined value is set to n. Data processing device.