JPH01188946A - Instruction fetching system - Google Patents

Abstract

PURPOSE:To realize a dynamic program loading action and also to increase the copy processing speed of data by producing 2 read or write addresses to a single input data that gives an access to a program memory. CONSTITUTION:The access data supplied to a data holding means 400 is divided into a 1st word including a read or write address and a 2nd word including the operand data serving as the arithmetic processing result preceding by one step and to be given to the next instruction or the write program data. When an instruction is fetched, the address information included in the 1st and 2nd words are sent to a selector 102 of an address generating means 10. Then a timing control means 103 detects the 1st or 2nd word and the selector 102 is selected and delivered based on the detection of the means 103. While the 1st word is sent to a data holding means 401 and a key holding means 402, and the 2nd word is transferred to the data holding means 501 and 502. These words are also sent to the means 501 from a data holding means 500 and copied.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an instruction fetch method in a data flow computer.

<Prior art> When executing a program written in a data flow graph, if a data dependency relationship as shown in FIG. 3(a) is established, the execution result data for 31 addition instructions is as follows. It is the right input data for the multiplication instruction No. 32 and the left input data for the division instruction No. 33, so that two or more instructions may be fetched for a single result data. (This data dependency relationship is hereinafter referred to as "data copy.") Conventionally, as an instruction fetch method for realizing data copy, Japanese Patent Application No. 61-55960 (Japanese Patent Application Laid-Open No. 62-211749), the information regarding the copy of data stored in the program data is read from the memory and determined, and it is determined whether or not to access the program memory again based on the determination result. . In other words, after it is determined that data needs to be copied, memory address manipulation (
In the conventional example, the address register/counter was incremented.

<Problems to be solved by the invention> In the conventional example shown in Fig. 4, the program size is significantly limited by the address capacity of the memory used, and like a so-called cache memory, the program size is There were problems with scalability, such as the ability to dynamically update program content and effectively utilize a wider address space.

Measures to Solve the Problems In order to dynamically update program contents, the program memory area is divided into a key area and a tag area containing instruction information, and the program memory is divided into a single input data area that accesses the program memory. means for generating two or more read or write addresses for the input data; and first comparison determination means for comparing and determining the read key included in the input data for instruction fetch and the key read from the program memory. , a second comparison and determination means for decoding a flag regarding data copy included in the tag information read from the program size, and two or more comparison and determination means based on the determination results of the first and second comparison and determination means. and means for controlling the transfer of output of read command data.

Effect> By means of generating two or more read or write addresses for a single input data that accesses the program memory, two or more addresses are always generated for each input of access data, and the plurality of Update or refer to memory cells one by one for each address. When referring to a memory cell, based on the determination result of the second comparison determination means,
By determining whether or not to transfer reference data and input operand data to the output stage, it is determined whether or not to perform data copy processing. FIG. 2 is a block configuration diagram. In the figure, lO is address generation means, I
I is an address decoder, 12 is a sense amplifier and read/write control means, 13 is a memory cell array, 14 is a first comparison/judgment means, 15 is a second comparison/judgment means, 200 to 2
04 and 300 to 304 are transfer control means for controlling handshake data transfer; 400 to 406 and 500;
Reference numerals 504 to 504 are data holding means, and the data transfer timing is determined by the transfer control means 200 to 204 and 30, respectively.
Controlled by 0 to 304. Address generation means l
O is an incrementer +01 with a data retention function,
Selector 1 that selectively outputs transfer data from data holding means 400 and output data of incrementer 101
02. and timing control means tOa that determines the timing at which data output from the incrementer is permitted.

Referring to FIG. 1, the operation of an instruction switch and the operation of dynamic loading of program data will be explained. In the present invention, memory references corresponding to instruction fetches and memory updates corresponding to dynamic loading of program data can be executed in the same access time, and references and updates can be executed in any sequence. Therefore, referencing and updating will be explained separately. However, the access data to the program memory section is separated into a first word containing the read or write address and a second word that is the result of the previous operation and contains operand data for the next instruction or write program data, for example. It is assumed that the data is applied to the data holding means 400 and 500 at the input timing shown in FIG. Second
In the figure, 01 and C2 represent the transmission signal outputs of the transfer control means 200 and 300, respectively, and the change to the "Low" level corresponding to the logic "0" state indicates reception and holding of the transfer data. The transfer control to the stage is
Although not shown in FIG. 2, permission, prohibition, or transfer completion is determined based on a transfer permission signal from the next stage.

First, when performing an instruction fetch, the address information included in the first word of the packet is sent from the data holding means 400 to the selector 102 of the address generating means IO, and also to the incrementer 101. The timing control means +03 detects that the first word has been input, and outputs the data to the data holding means 400 as the data output of the selector +02.
selectively outputs the transfer data from the incrementer +
Deselect the output of 01. Next, when the second word of the instruction fetch packet is input to the data holding means 500, the timing control means 103 enables the output of the incrementer +01 and sends it to the selector 102.
1 is selectively output, and the transfer data from the data holding means 400 is deselected. For simplicity, two different methods are used for single operand data as data copy processing.
The case where one instruction is fetched will be explained. In FIG. 2, the first word of the instruction fetch packet input at time To is transferred to data holding means 401 at time T1, and further transferred to decoder and read key holding means 402 at time T2. Also, at the same time, incrementer +0
The output result of 1 is transferred to the data holding means 401 via the selector 102.

On the other hand, as shown in FIG. 2, the second word of the instruction fetch packet input at time Tl, that is, the operand data for the next instruction, is transferred to the data holding means 501 at time T2, and the data is further transferred at time T3. It is transferred to the holding means 502 and also transferred from the data holding means 500 to 501, thus making one copy of the same operand data.

Eventually, for the same operand data held in the data holding means 501 and 502 at time T3, the reference data read from the memory cell array 13 of the program memory via the sense amplifier 12 is transferred to the data holding means 403, and the reference data is transferred to the data holding means 403. Upon completion of the first instruction fetch, the second instruction fetch is subsequently started according to the address information and key information input to the decoder I+ and the key data holding means 402.

In the above example, the timing control means 103 detects the timing of data input to the data holding means 400 and 500, and functions to double the amount of data transferred in each data transfer path.

Although not shown as an example, it is obvious that as the transfer capacity of the data transfer path and the access speed of the memory cell array improve, the number of instructions that can be fetched in data copy processing can be increased.

Also, at time T3, the reference tag among the program data held in the data holding means 403 is the data holding means 403.
04, and the reference key is input to the first comparison/judgment means 14 together with the read key.

A flag indicating whether copy processing of data included in the reference tag is necessary is input to the second comparison/determination means 15.

The first comparison and determination means 14 compares the two keys, and if the determination result is a mismatch, the data holding means 400
The read address and read key input to the data holding means 404 and 406 are transferred to the data holding means 404 and 406, respectively. On the other hand, if the judgment result is a match, the judgment result of the second comparison and judgment means 15 is referred to and the following processing is performed based on the judgment result.

That is, when data copy processing is not required, the reference data of the program memory is transferred from the data holding means 403 to 405, and the result of the fetch of the second instruction being executed is transferred from the data holding means 403 to 405. prohibited. On the other hand, if data copy processing is required, the above-mentioned 1. The second instruction fetch results are both transferred from data holding means 403 to 405. Data output from the data holding means 405 or 406 is performed based on the judgment result of the first comparison judgment means I4,
If the keys do not match, the data holding means 406 is selectively enabled for output, and when the keys match, the data holding means 405 is selectively enabled for output.

Next, when dynamically loading program data, the write address and program data are input to the data holding means 400 and 500, respectively, similarly to when fetching instructions. In the case of program loading, write information is input as information corresponding to the read key, and according to the information, the address generation means 10 can write the same update data to two different addresses.

<Effects of the Invention> According to the present invention, dynamic program loading becomes possible, and data copy processing becomes possible at high speed. Furthermore, as shown in FIG. 3(b) K, when the right input data of the addition instruction 80 is given by a constant C, by loading this constant into the program memory, the right input data fetching the addition instruction 30 is given by the program memory. When referring to
By using the copy processing function described above, constant references can be performed along with instruction fetches. Therefore, a useful instruction fetching method is provided that can be used not only as a memory for storing programs but also as a data memory.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a program memory according to the present invention, FIG. 2 is a diagram showing address generation timing of the program memory, and FIG. 3(a) is a diagram showing an example of a data flow program showing data copying. FIG. 4B is a diagram showing an example of a data flow program showing access to constant data, and FIGS. 4 and 5 are diagrams showing conventional examples. 10' is an address generation means, 11 is a decoder, +2 is a sense amplifier and read/write control means, 13 is a memory cell array, 14 and 15 are comparison/judgment means, 101 is an incrementer, 102 is a data selector, 103 is a timing control means, 200 204 to 204 and 300 to 304 are transfer control means, and 400 to 406 and 500 to 504 are data holding means. Agent: Patent Attorney Takeshi Sugiyama (and 1 other person), °62 Figure L゛・1・J″1 [-・-Hashi 5L] (b) Figure 3 Procedural Amendment (Method) May 17, 1988 Day 1, Indication of the case Patent application 1983-12790 2. Name of the invention Order fetch method 3, Person making the amendment Relationship with the case Patent applicant address 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 8545 Name (504) Sharp Corporation Representative Haru Tsuji 4Kon4, Agent April 26, 1986

Claims (1)

[Scope of Claims] 1. A data flow program storage device comprising a plurality of data holding means, a means for generating an address between two adjacent data holding means, a storage means, and a comparison and determination means, address generation means,
It is composed of an address calculation means, a timing control means, and an address data selection means. By configuring the system with a second comparison/judgment means for determining whether or not to refer to the data (hereinafter referred to as "data copy processing"), both the dynamic loading of program data and the data copy processing can be performed in parallel with good efficiency. This is an instruction fetch method that is characterized by being able to execute instructions with ease.