JP5145659B2 - Vector renaming method and vector computer - Google Patents

Description

  The present invention relates to a vector computer, and more particularly, to a register renaming method that enables register renaming to improve calculation throughput, and a vector computer that employs such a register renaming method.

  In order to improve the performance of a computer system, it is necessary to increase the number of instructions that can be executed per unit time. In particular, in order to improve sustained performance, it is necessary to improve the rate at which instructions are issued (Issue rate).

  In computer systems, arithmetic processing is generally performed between registers. However, when pipeline processing is used, after issuing an instruction for one register, the same register can execute another instruction. Need machine cycles. The hardware has more registers than the program assumes, and when there are multiple instructions that are for the same register in the program, By using a register different from the defined register, the operation speed can be increased. Register renaming (renaming of registers) is a method for speeding up operations by such a method.

  In register renaming that is generally performed, an alias is given to a register to which a certain operation result is written, and resource dependency is relaxed. For example, regarding the subsequent instruction B that writes to the same logical resource X while the instruction A is reading data from the logical resource X, the physical resources X1 and X2 are changed to A and B for the logical resource X, respectively. By allocating, it becomes possible to prevent data from being overwritten by B execution. This means that the issue limit of the instruction B is relaxed, and an increase in the issue rate can be expected.

  However, if register renaming is to be applied to a vector computer, the vector computer is provided with a mask function that can switch the presence / absence of calculation for each element, thus realizing a simple renaming mechanism. There is a problem that it is not possible. For example, when the above-described instruction B is masked, it is necessary to store the original value of the operation result, that is, the corresponding element of the execution result of the instruction A, in the masked element. This is because data already written in a certain register may be referred to by an instruction to be executed later as long as the operation is masked. The mask function in the vector computer is described in Patent Documents 1 and 2, for example.

For this reason, it is not sufficient to simply assign a plurality of independent resources to A and B, and it is necessary to pass values between the resources, and it is not possible to simply introduce an existing register renaming technique. A configuration in which a value is transferred between resources is described in Patent Document 3, for example.
JP 60-150473 A JP-A-1-284970 JP 2000-172505 A

  As described above, the conventional register renaming technique is widely used as a technique for improving the arithmetic processing performance by improving the instruction issue rate, but has a problem that it cannot be applied to a vector computer as it is. . When adopting a configuration in which a value can be transferred between resources as described in Patent Document 3, there is a problem that the hardware configuration becomes complicated.

  Therefore, an object of the present invention is to adopt a vector renaming method and a vector renaming method that can simultaneously realize mask operation and register renaming in a vector computer using simple hardware. It is to provide a vector type computer.

Baie transfected Ruri naming scheme of the present invention is a vector renaming scheme that enables left register renaming to achieve a mask operation function in vector computer, a plurality of forming a pair with each other while corresponding to the logical vector register Each renaming register has a cell that holds 1-bit data and a selector provided for each cell, and the selector holds the write data or other cells in the set . The value is supplied to the corresponding cell according to the mask signal. When the mask is set, the cell value is copied between the cells. When the mask is not set, the write data is written to any cell. It is what I did.

Vector type computer of the present invention includes a control unit for controlling the register renaming, a plurality of renaming register constituting a pair mutually with corresponding logical vector registers, and the arithmetic unit is controlled by the control means more A first selector that supplies an output of one of the renaming registers to the arithmetic unit, and a write control unit that inputs an operation result of the arithmetic unit and stores it in any of the plurality of renaming registers, Each renaming register has a cell that holds 1-bit data, and a second selector provided for each cell. The second selector can select either write data from the write control means or other data in the set . Is supplied to the corresponding cell according to the mask signal, and if the mask is set, the cell value is copied between cells and When the but not set is obtained so as to write the write data into one of the cells.

  The present invention allows a plurality of renaming registers mapped to a logical vector register to copy values necessary for mask operation by combining these renaming registers, thereby enabling a simple cell configuration. There is an effect that register renaming can be realized while the mask operation is realized. In particular, according to the present invention, since the mask operation and the register renaming are made compatible without requiring a large-scale hardware, the issue rate of vector instructions can be greatly improved at low cost.

  Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a cell set (cell set) used in the vector renaming method according to the embodiment of the present invention.

  The cell set shown in FIG. 1 includes 1-bit RAM (Random Access Memory) cells C0 and C1, and each bit corresponds to two physical registers mapped to the same logical register. Here, one logical vector register is renamed to one of two physical vector registers, and has cells for 2 bits. However, actually, three or more cells are used depending on the form of renaming. One cell set may be configured using cells.

  These cells are preferably laid out in close proximity on the hardware. A unit in which cells are gathered in this way is read as a cell set.

  Selectors S0 and S1 are provided in the paths for writing data to the cells C0 and C1, respectively. Write data WD for the cell is input to the cell set, and this data WD becomes input data when writing to one or both of the cells C0 and C1. The output RD1 of the cell C1 is also connected to the selector S0, and the output RD0 of the cell C0 is also connected to the selector S1. Eventually, the cells C0 and C1 are connected through the selectors S0 and S1 so as to be opened. The selectors S0 and S1 are supplied with a mask signal MASK. If the mask signal MASK is active (“1”), the selectors S0 and S1 supply the outputs of the counterpart cell (the outputs of the cells C1 and C0) as write data to the cells C0 and C1, respectively. If the MASK signal is not active (ie, “0”), the ride data WD is supplied. Read data RD0 and RD1 are read from the cells C0 and C1, respectively. Note that the selection signal 42 from the resource management unit 4 controls which of the leads RD0 and RD1 is supplied to each computing unit (FMAC 70, 73, FDV 71, 74, FLOGIC 72, 75 described later) in the vector computer. This is selected by a selector 80 described later. The selector is provided for selecting one mapped to the logical register from the physical vector registers provided in pairs and supplying the output to each arithmetic unit.

  Write enable signals WE0 and WE1 are supplied to the cells C0 and C1, respectively. WE0 is a write enable for C0. If this signal is active, the signal selected by the selector C0 is written to the cell C0. That is, if WE0 is active, data WD or the output value of cell C1 is written into cell C0. For example, when the signal WE0 becomes active (“1”) when the mask signal MASK is “1”, the contents of the cell C1 are written into the cell C0, that is, the value is copied. When the signal WE0 becomes active when the signal MASK is “0”, the value of the write data WD is written in the cell C0. Similarly, the signal WE1 is a write enable signal for the cell C1, and when this signal WE1 becomes active, the output value of the data WD or the cell C0 is written into the cell C1.

  After all, in this cell set, by designating the mask signal (mask bit) MASK, the write data is written from the outside or the cell on the opposite side of the own cell in the cell set (if the own cell is the cell C0). For example, data on the cell C1 side) can be switched and written.

  A vector computer has an operation mask function that can specify whether or not an operation can be performed for each operation element, and a vector mask target instruction that is an instruction that does not change the value of the masked element. Therefore, the renaming mechanism in the vector computer needs to consider the masked “no change” data. When the physical registers VRR100 and VRR108 correspond to the logical register VR0, an information passing path is required between the logical vector register VR0 and the corresponding elements of the physical vector registers VRR100 and VRR108.

  By using the cell set of this embodiment, if the original data is contained in any of the VRR (physical vector register) cells in the cell set, the value can be inherited when the cell on the opposite side is updated. Thus, both the renaming operation and the mask operation can be achieved. In the present embodiment, such a cell set exists for the size of the logical vector register. For example, in an architecture having a 64-bit configuration and eight logically 256 vector registers, 64 × 256 × 8 = 131,072 cell sets described above are prepared. If each cell set is composed of two cells, there will be 262,144 physical cells.

  FIG. 2 shows an example of the configuration of a vector computer that performs register renaming by using the above-described cell set. This vector computer includes an instruction supply unit 1 including a general instruction cache, a decoder 2 that decodes an instruction from the instruction supply unit 1, an issue control unit 3 that performs issue control of the decoded instruction, and issue control. And a resource management unit 4 that manages resources used by instructions issued by the unit 3. The resource management unit 4 prepares a correspondence table 41 of logical vector register numbers and physical vector register numbers for instructions issued by the issue control unit 3, particularly for the register renaming function. FIG. 3 shows an example of the contents of the correspondence table 41.

  Here, the VRR 10 is a vector renaming register, and is an actual register group in the case of logically configuring the vector registers VR0 to VR7, and includes 16 physical vector registers VRR100 to VRR115. Each physical vector register includes 256 entries of data registers having a 64-bit width. A control signal 31 is supplied from the issue control unit 3 to the vector renaming register VRR10.

  The physical value of the logical register VR0 is stored in either the physical vector register VRR100 or the physical vector register VRR108. Similarly, the physical value of the logical register VR1 is stored in either the physical vector register VRR101 or the physical vector register VRR109. Similarly, the logical register and the physical vector register are associated with each other.

  The vector computer is provided with FMAC (arithmetic unit) 70 and FMAC 73 for performing addition and multiplication, FDV (divider) 71 and FDV 74 for performing division, FLOGIC (logical arithmetic unit) 72 and FLOGIC 75 for performing logical operation, In addition, a data write control unit 9 to which each calculation result is sent is provided. The data write control unit 9 obtains, as a calculation result, an appropriate location of the vector renaming register VRR10 from the correspondence between the logical vector register number and the assigned physical vector register number (that is, VRR100 to VRR115) and the mask information. Written data or data already written in the physical vector registers VRR100 to 115.

  Note that a selector 80 is provided to select one of the outputs of the paired physical vector registers, and vector data read from the physical vector register selected by the selector 80 is FMAC70, FDV71, FLOGIC ( Logic unit) 72, FMAC 73, FDV 74, and FLOGIC 75. The selector 80 is controlled by a selection signal 42 from the resource management unit 4. For example, one of the physical vector register VRR100 and the physical vector register VRR108 is selected by the selector 80.

  Further, the vector computer is provided with an LS unit 5 and an external storage memory 6. The LS unit 6 manages the operation of storing data from the physical vector registers VRR100 to 115 in the external storage memory 6, and the operation of loading data from the external storage memory 6 and writing to any of the physical vector registers VRR100 to 115. .

  Next, the register renaming operation in this vector computer will be described.

  In the following description, “vector” means a data string containing a plurality of element data. Here, it is assumed that the vector has a maximum of 256 64-bit element data. Hereinafter, processing when the instruction sequence shown in FIG. 4 is executed will be described. In the instruction sequence shown in FIG. 4, “VADD” is an instruction for performing addition for each element of vector data stored in two logical vector registers specified by operands and storing the result in the destination vector register.

  “VSUB” is an instruction that performs subtraction for each element between the vector data stored in the two logical vector registers specified by the operand, and stores the result in the destination vector register.

  Here, in both the VADD instruction and the VSUB instruction, it is possible to selectively specify (that is, apply a mask) an element on which an operation is not performed. The VFMK instruction is an instruction for changing a vector mask. The number of elements (VL; vector length) in which the vector operation is actually performed can be changed between 0 and 256 by software. The LVL instruction is an instruction for changing the number of vector elements to be calculated. For example, when VL is specified as 10 by the LVL instruction, vector operation is performed on only 10 elements from the top among the elements included in the vector register.

  First, in the instruction group shown in FIG. 4, the instruction LVL in the first row is supplied from the instruction supply unit 1, decoded by the decoder 2, the LVL instruction is issued by the issue control unit 3, and the vector length VL is set to 4. Is done. Since 4 is designated as VL in the LVL instruction, the vector operation will be performed on the first four elements included in the vector register below. FIG. 5 shows values of the correspondence table 41, mask information, VL, and renaming registers (physical vector registers) VRR100, VRR101, VRR102, and VRR108 in the resource management unit 4 at the end of the LVL instruction. As shown in FIG. 5, a value of 4 is set in VL. At this time, the VRR 100 is allocated as a physical vector register for the logical vector register VR0. This indicates that the value of the physical vector register VRR100 at this time is the value of the logical register VR0.

  Next, the instruction VFMK in the second row in the instruction group shown in FIG. 4 is supplied from the instruction supply unit 1 and decoded by the decoder 2. The issue control unit 3 issues an LFMK instruction and sets “0101” in the vector mask. The VFMK instruction whose operand is “0101” is an instruction that applies a mask that does not perform an operation on the element whose mask is “1”, in this case, the second element and the fourth element. is there.

  FIG. 6 shows values of the correspondence table 41, mask information, VL, and renaming registers VRR100, VRR101, VRR102, and VRR108 in the resource management unit 4 at the end of the VFMK instruction. As shown in FIG. 6, the value “0101” is set in the mask information.

  Next, the instruction VADD in the third row is supplied from the instruction supply unit 1 and decoded by the decoder 2. In the illustrated example, this instruction VADD performs vector addition of values stored in the logical vector registers VR1 and VR2 and stores the result in the logical vector register VR0.

  The issue control unit 3 issues a VADD instruction. At this time, the resource management unit 4 assigns the physical vector register VRR108 side to the logical register VR0 to which the result of the VADD instruction is written, and rewrites the correspondence information in the resource management unit 4 to the physical vector register VRR108. The VADD instruction is executed by the FMAC 70, and the calculation result is sent to the data write control unit 9.

  The operation of writing the result of executing the VADD instruction is performed by the data write control unit 9. FIG. 7 shows control data from the data write control unit 9. From the data write control unit 9, the element number, the register name of the write physical vector register VRR, the write data WD as the calculation result, and the mask information MASK are sent to the renaming vector register VRR10. Then, appropriate writing is performed in the corresponding register in the renaming vector register VRR10, that is, in the cell set in the physical vector register VRR108.

  For example, regarding the operation result of element 0, since the mask information is “0”, the calculation result “12” is written to the cell on the physical vector register VRR 100 side as write data WD. In the cell set shown in FIG. 1, if the data of the physical vector register VRR100 is written on the cell C0 side and the data of the physical vector register VR108 is written on the cell C1 side, the write enable signal WE1 becomes “1” and MASK The signal remains “0” and “12”, which is the write data WD, is written to the cell C1.

  Regarding the operation result of element 1, since the mask information is “1”, that is, active, “1”, which is data on the physical vector register VRR 100 side, is written in the cell on the opposite physical vector register VRR 108 side. In the cell set of FIG. 1, if the data on the physical vector register VRR100 side is written on the cell C0 side and the data on the physical vector register VR108 side is written on the cell C1 side, the write enable signal WE1 becomes “1”, and The MASK signal becomes “1”, and “1” which is the stored value of the cell C0 is written into the cell C1.

  FIG. 8 shows values of the correspondence table 41, mask information, VL, and renaming registers VRR100, VRR101, VRR102, and VRR108 in the resource management unit 4 at the end of execution of the VADD instruction. As shown in FIG. 8, the execution result of the VADD instruction is stored in the allocated physical vector register VRR 108 in a form reflecting the mask information.

  Finally, the VSUB instruction in the fourth row is supplied from the instruction supply unit 1 and decoded by the decoder 2. In the illustrated example, this VSUB instruction subtracts the content of the logical vector register VR1 from the content of the logical vector register VR2 and stores the result in the logical vector register VR0.

  The issue control unit 3 issues a VSUB instruction. At this time, the resource management unit 4 assigns the physical vector register VRR100 side to the logical register VR0 to which the result of the VSUB instruction is written, and rewrites the correspondence information in the resource management unit 4 to the physical vector register VRR100. The VSUB instruction is executed by the FMAC 70, and the calculation result is sent to the data write control unit 9.

  As in the case of the VADD instruction described above, the write operation of the execution result of this VSUB instruction is performed by the data write control unit 9. FIG. 9 shows control data from the data write control unit 9. Appropriate writing is performed in the corresponding register in the physical vector register VRR100, that is, in the cell set in the physical vector register VRR100.

  For example, for the operation result of element 0, since the mask information is “0”, the calculation result “4” is written in the cell on the physical vector register VRR 100 side as write data WD. In the cell set of FIG. 1, if the data on the V physical vector register RR100 side is written on the cell C0 side and the data on the physical vector register VRR108 side is written on the cell C1, the write enable signal WE0 becomes “1”. In addition, the MASK signal remains “0”, and “12”, which is the write data WD, is written into the cell C0.

  Regarding the operation result of element 1, since the mask information is “1”, “1”, which is data on the physical vector register VRR 100 side, is written to the cell on the physical vector register VRR 108 side. In the cell set of FIG. 1, if the data of the physical vector register VRR100 is written to the cell C0 side and the data of the physical vector register VR108 side is written to the cell C1, the write enable signal WE0 becomes “1” and MASK The signal becomes “1”, and “1” which is the stored value of the cell C1 is written into the cell C0.

  FIG. 10 shows the correspondence table 41 in the resource management unit 4, mask information, VL, and values of the renaming registers VRR100, VRR101, VRR102, and VRR108 at the end of the VSUB instruction. As shown in FIG. 10, the execution result of the VSUB instruction is stored in the allocated physical vector register VRR100 in a form reflecting the mask information.

  In this way, according to the present embodiment, even if a mask operation is performed in the vector computer, it can be ensured that a normal result is written also to the renamed vector register side.

  In the above description, an example in which each instruction operates in a non-pipeline is described. However, as a matter of course, each instruction operates in a pipeline, and a part of each instruction operation overlaps each other. May be.

It is a circuit diagram which shows the cell set used with the vector renaming system of one Embodiment of this invention. It is a block diagram which shows schematic structure of the vector computer of one Embodiment of this invention. It is a figure which shows an example of the content of the corresponding | compatible table provided in a resource management part. It is a figure which shows an example of the command group given to a vector computer. It is a figure which shows the value of a correspondence table, mask information, VL, and a renaming register at the time of completion | finish of a LVL instruction | indication. It is a figure which shows the value of a correspondence table, mask information, VL, and a renaming register at the time of completion | finish of a VFMK instruction | indication. It is a figure which shows the control data from a data writing control part. It is a figure which shows the value of a correspondence table, mask information, VL, and a renaming register at the time of completion | finish of a VADD instruction | indication. It is a figure which shows the control data from a data writing control part. It is a figure which shows the value of a correspondence table, mask information, VL, and a renaming register at the time of completion | finish of a VSUB instruction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Instruction supply part 2 Decoder 3 Issue control part 4 Resource management part 5 LS unit 6 External storage memory 9 Data write control part 31 Control signal 41 Correspondence table 42 Selection signal 80, S0, S1 Selector 70, 73 FMAC (arithmetic unit)
71,74 FDV (divider)
72,75 FLOGIC (logic operator)
C0, C1 cell VR logical register VRR physical vector register

Claims (3)

A vector renaming method that enables register renaming while realizing a mask operation function in a vector computer,
Comprising a plurality of renaming register constituting a pair mutually with corresponding logical vector register,
Each of the renaming registers includes a cell that holds 1-bit data, and a selector provided for each cell.
The selector supplies write data or a value held by another cell in the set to a corresponding cell according to a mask signal,
A vector renaming method in which a cell value is copied between the cells when a mask is set, and the write data is written to any cell when the mask is not set. The vector renaming method according to claim 1, wherein two physical vector registers are provided as the plurality of renaming registers for each logical vector register. A vector calculator,
Control means for controlling register renaming;
A plurality of renaming register constituting a pair mutually with corresponding logical vector register,
An arithmetic unit;
A first selector which is controlled by the control means and supplies an output of one of the plurality of renaming registers to the computing unit;
Write control means for inputting a calculation result of the calculator and storing it in any of the plurality of renaming registers;
With
Each of the renaming registers includes a cell that holds 1-bit data, and a second selector provided for each cell,
The second selector supplies write data from the write control means or a value held by another cell in the set to a corresponding cell according to a mask signal,
A vector calculator that copies a cell value between the cells when a mask is set, and writes the write data to any cell when the mask is not set.

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