JPH06187140A - Processor - Google Patents

Abstract

PURPOSE:To perform the processing with a corrected program by making a correction program routine execute at the time of partially correcting and executing the source program stored in a ROM. CONSTITUTION:This processor is provided with a battery backup memory (BBM) 101 for storing the interruption address of the source program to be changed and a program routine to be changed and an interruption signal generation part 120 for generating interruption signals at a set address while the source program is operated other than the ROM 2 for storing application programs. Then, the interruption signal generation part 120 reads the interruption address beforehand and compares it with the address of the source program at all times while the source program is operated. In the case of coincidence, an interruption code is outputted to a data bus 5 and data output from the ROM 2 to the data bus 5 is prohibited at the same time. When the interruption code generated by the interruption signal generation part 120 is detected, a change routine stored in the BBM 101 is read and executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device having a ROM storing a program, and more particularly to a processing device constructed so that a program stored in the ROM can be partially modified.

[0002]

2. Description of the Related Art In recent years, as all devices have been electrified and higher performance is required, CP
The number of control units represented by U, which are configured to operate according to a program recorded in ROM, is increasing more and more. This is increasing more and more because a CPU called a one-chip microcomputer is available at a relatively low cost.

FIG. 2 is a block diagram of a one-chip microcomputer as an example. In the figure, the one-chip microcomputer has a CPU 1, a ROM 2, and a RAM 3, which are interconnected by an address bus 4 and a data bus 5.

The CPU 1 performs processing according to the program read from the ROM 2. The ROM 2 stores an application program, that is, a program to be actually processed as data. In addition to application programs, this ROM 2 stores other necessary programs such as an initial setting program for the apparatus itself. R
The AM3 is used to temporarily store data temporarily generated during program operation and data input from the outside.

For example, an instruction to add 1 to the data stored at the address 1000 of the RAM 3 is the ROM 2 as data.
Stored in the memory, the CPU 1 reads the data consisting of this instruction code from the ROM 2 as described above,
Decode as a program instruction. As a result, the CPU 1 determines that the instruction is to add 1 to the data stored in the address 1000 of the RAM 3, and outputs 1000 to the address bus 4 to transfer the value stored in the address 1000 of the RAM 3 to the data bus 5. Data is added to the address 1000 of the RAM 3 by reading out via the address, adding 1 to this value, and outputting 1000 to the address bus again.

In this way, the CPU 1 executes the instruction to be executed by R
When the execution address data is output to the address bus 4 for reading by the OM 2, the ROM 2 outputs one instruction of the program stored as data at the selected address to the data bus 5 as data. The CPU 1 takes in this data as an instruction, decodes it, and executes it.

[0007]

However, in the above-described processing device, when the contents of the ROM 2, that is, the contents of the program, are changed, the values stored in the address 2000 of the RAM 2 instead of the address 1000 are changed in the above example. When it is desired to change the program so that 1 is added, there has been a problem that the ROM changed to the program in which 1 is added to the value stored at the address 2000 must be replaced with the current ROM. Also, if this is a one-chip microcomputer, it is impossible to replace only the ROM, and it is necessary to replace all the microcomputers.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a ROM storing a program and the ROM are sequentially output by outputting the address of the ROM to an address bus. In a processing device having a CPU for operating a program stored in, a writable and readable non-volatile memory;
An interrupt signal generator that constantly compares the value of the address bus with a predetermined interrupt address value during execution of the program stored in the OM and outputs an interrupt code to the data bus, and the interrupt code. And a control means for executing the program stored in the non-volatile memory.

[0009]

Since the present invention is constructed as described above, it operates as follows. First, an address of an original program to be changed and a change routine are stored in advance in a non-volatile memory such as a BBM, and when the original program is operated, the CPU sequentially generates addresses on the address bus and R
The data consisting of the program stored in the OM is read, decoded as a program instruction, and executed. At this time, for example, the interrupt address previously stored in this non-volatile memory is read out, and during the original program operation,
Always compare with the address of the original program. When they match, the interrupt code is output to the data bus. CP
When U detects the interrupt code generated by the interrupt signal generator, the control program reads the data consisting of the change routine stored in the non-volatile memory, decodes it as a program command, and executes it. By operating in this manner, the original program can be modified by the program including the change routine, and the modified program can be continuously operated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a processing device according to the present invention, and FIG.
Is a memory map of the battery backup memory used in the present invention, FIG. 4 is a flowchart of an initialization program that is operated before operating the application program, FIG. 5 is a flowchart of interrupt processing, and FIG. 6 is a flowchart for explaining interrupt processing. It is a memory map.

In FIG. 1, the processing device is a CPU 1, RO
It has an M2, a RAM 3, an address bus 4 and a data bus 5. Although these configurations are almost the same as the configurations of the conventional processing device, the ROM 2 has a function of an interrupt process when a program is modified, in addition to an initialization program and an application program (hereinafter referred to as an original program). It has a program routine for setting.

The processing device further includes a non-volatile memory, for example, a battery backup memory (hereinafter, referred to as B), which stores a program routine for changing (hereinafter, referred to as change routine).
(Referred to as BM) 101, an interrupt program setting unit 110 having a switch group for setting whether or not to write an interrupt program to the BBM 101 or to operate a program stored in the BBM 101, which is set during operation of the original program. It has an interrupt signal generating unit 120 for generating an interrupt signal at the address.

The outline of the operation of the present invention will be described below. First, the address of the original program to be changed to the BBM 2 (hereinafter referred to as an interrupt address) and the change routine are stored in advance. When the original program is operated, the CPU 1 sequentially outputs addresses to the address bus 4
Data that is generated in the ROM 3 and stored in the ROM 3 is read through the data bus 5, decoded as a program command, and executed. The interrupt signal generator 120 reads out the interrupt address stored in the BBM 101 in advance through the data bus 5, and during the operation of the original program,
Always compare with the address of the original program. If they match, the interrupt code is output to the data bus 5 and the data output from the ROM 2 to the data bus 5 is prohibited. When the CPU 1 detects the interrupt code generated by the interrupt signal generator, the CPU 1 reads the data consisting of the change routine stored in the BBM 101, decodes it as a program command, and executes it. When the change routine stored in the BBM 101 is completed, the processing returns to the predetermined address of the original program and the processing by the original program is restarted.

Next, the details of each component will be described. BBM10
1 has the configuration shown in FIG. In the figure, BBM1
01 is assigned from the predetermined address n, and the data write pointer 301, n + is assigned to the n address.
An interrupt address 302 is stored in the first address, and a change routine is stored in the n + 2 and subsequent addresses. Then, at the end of the change routine, a jump instruction 304 composed of a return address to the original program when the processing of the change routine is completed is stored. Note that not limited to the BBM 101, any writable non-volatile memory may be used. For example, an EEPROM may be used. As described above, when the EEPROM is used as the non-volatile memory, it is possible to obtain a one-chip microcomputer whose program can be easily modified later. On the other hand, when the BBM is used as in the present embodiment, the reading speed is high, so that a processing device that operates without changing the processing speed of the program can be obtained. At this time, the CPU 1, the ROM 2, the RAM 3, the buses 4 and 5, and the interrupt signal generating circuit 120 may be configured in one chip, and the other parts may be provided outside the chip.

The interrupt program setting section 110, as shown in FIG. 1, has a data switch section 111, an interrupt address setting switch 112, and an interrupt address valid switch 113.
, A data write switch 114, and a switch detection circuit 115 for detecting the states of these switches. The data switch unit 111 sets a data value for writing data to a predetermined address of the BBM 101, and is provided in a number corresponding to the number of bits of each address of the BBM 101. The interrupt address setting switch 112 is B
Set whether or not to allow writing of data to the BM 101. The interrupt address enable switch 113 is a BBM.
Set whether or not to execute the program operation by the change routine stored in 101. Data write switch 1
14 sets writing / not writing of the data set by the data switch unit 111 to the BBM 101.

As shown in FIG. 1, the interrupt signal generator 120 compares a detection register 121 that stores an interrupt address, and the address data of the interrupt address of the detection register 121 with the address output to the address bus 4. Bowl 122
From the logic circuits of the inverter circuit 123, AND circuits 124 and 125, which generate a predetermined logic by combining the output of the comparator 122 and the output from the memory read terminal R of the CPU 1, and the interrupt code generation circuit 126. Composed. The detection register 121 reads out and stores the interrupt address 302 stored in the BBM 101, and requires at least the same number of bits as the address data.
The comparator 122 compares the value of the interrupt address stored in the detection register 121 with the address value output by the CPU 1 for reading the original program stored in the ROM 2, and if they match, a logic "1" is output from the output O. Is output, and if they do not match, a logical "0" is output. The AND circuit 124
The memory read signal R of the CPU 1 and the output signal of the comparator 122 are input, and only when both are logic "1", the logic "1" is output to the interrupt code generation circuit 126. The interrupt code generation circuit 126 outputs an interrupt code to the data bus 5 when a logic “1” is input to the input E. That is, CPU1
Generates a read command for the ROM 2 and generates an interrupt code when the interrupt address 302 matches the address in the ROM 2 of the original program to be executed. A
The ND circuit 125 inputs the memory read signal R of the CPU 1 and the inverted output signal of the comparator 122, and both are logic "
Only in the case of 1 ", the logic" 1 "is output to the ROM 2. RO
M2 outputs the data of the address designated by the address bus 4 to the data bus 5 when the logic "1" is input to the input E. Therefore, even when the CPU 1 issues a read command for the ROM 2, when the interrupt address 302 matches the address in the ROM 2 of the original program to be executed, the data in the ROM 2 is not output to the data bus 5.

The operation will be described in more detail below. First,
The setting of the changing routine to the BBM 101 will be described. There are several ways to set this. The simplest setting method can be achieved by replacing the BBM 101 itself. In such a case, as BBM101,
If a memory card with a battery backup power source is used, or if a memory card made of an EEPROM is used instead of the memory card, the replacement operation itself becomes easy. When the processing device can be connected to a communication terminal or a disk device, a change program or the like can be set in the BBM through this. Further, in the case of a model that can be connected to the keyboard device, it is possible to input from the keyboard device.

However, in the processing device that does not have the convenient structure as described above, some switch groups as shown in the interrupt program setting unit 110 shown in FIG. 1 are prepared, and input and setting are performed from here. It is also possible to do so. A dip switch can be used for these switch groups. The interrupt program setting unit 110 includes a data switch unit 111, an interrupt address setting switch 112, an interrupt address valid switch 113, a data write switch 114, and a switch detection circuit 115 that detects the states of these switches. Composed.

The setting of the interrupt program using the interrupt program setting unit 110 is set by the change setting processing routine 409 shown in FIG. First, when the power is turned on, the data write pointer 30 of the BBM 101 shown in FIG.
1 is set to the address n + 1 (step 401). As a result, both reading and writing of the address n + 1 are possible.

Interrupt address setting switch 11 shown in FIG.
The state of No. 2 is read from the switch detection circuit 115, and if it is on, the routine proceeds to the routine for inputting the interrupt address 302 and the change routine from the data switch unit 111 (step 402).

Access to the BBM 101 is prohibited by reading the state of the data write switch 114, and if the state is off, the state of the switch 114 is continuously detected (step 403). As a result, even if the data switch unit 111 is set, there is no adverse effect such as writing wrong data to the BBM 101. On the other hand, if it is on, the set value of the data switch unit 111 set while the switch 114 is off is written to the address indicated by the data write pointer 301 shown in FIG. 3 at the value of the BBM 101 (step 404). First, data write pointer 3
Since the value of 01 is set to the address n + 1, the value of the interrupt address is set.

The data pointer is updated to the next address (step 405), the program code of the sequential change routine is input, and the setting is completed.

The operation of the processing apparatus having the change routine set as described above is performed as follows.
First, as shown in FIG. 4, the power is turned on and the data pointer is set in step 401 described above. This processing is not important when the operation of the processing device that does not write data to the BBM 101 is executed.

When the interrupt address setting switch 112 shown in FIG. 1 is turned off in step 402, the interrupt setting routine 410 initializes the interrupt processing. The state of the interrupt address valid switch 113 is read from the switch detection circuit 115 (step 406),
If it is off, the data in the detection register 121 is cleared (step 407). As a result, the value of the detection register 121 and the data of the address bus 4 do not coincide with each other, and the processing is performed assuming that the program is not changed by the BBM 101. On the other hand, if it is on, BB
The interrupt address 408 stored in M101 is read and set in the detection register 121.

After that, the original program stored in the ROM 2 is activated to start the processing.

The above-described processing may be stored as a program in the ROM 2, for example, and may be set to operate before the application program (original program) is started.
Further, it may be configured to be activated as one function of the OS.
By performing the above processing before starting the original program, it is possible to set an interrupt address to the original program and interrupt at this address.

Next, an interrupt to the change routine during execution of the original program will be described. FIG. 5 is a flow chart for explaining the interrupt processing, and FIG. 6 is a correspondence map of the contents of the stack area at the time of the interrupt processing and the ROM address at that time.

When the value of the interrupt address 302 stored in the detection register 121 shown in FIG. 1 and the read address of the ROM 2 output to the address bus 4 match during the original program operation, the interrupt code generation circuit 126 interrupts. It generates an embedded code and prohibits reading of data from the ROM 2.

When the CPU 1 detects this interrupt code,
As shown in FIG. 5, the process shifts to software interrupt processing, and FIG.
The address indicated by the stack pointer 601 shown in
BBM1 from address a + 1 next to interrupt address a of OM2
The start address n + 2 of the change routine stored in 01 (see FIG.
Refer to). After that, the change routine 305 is executed. When the processing of the change routine 305 ends, n
The return instruction 304 to the original program at the address +1 is executed. The return instruction 305 to the original program is a jump instruction to the address a + n shown in FIG. 6, and thus the change area 602 of the original program is not executed.

Although the case where there is one interrupt has been described above as an example, a plurality of interrupts can be made by changing this processing device as follows.

The detection register and the comparator shown in FIG. 1 are provided for the number of interrupts, and the outputs thereof are similarly input to the inverter circuit 123 and the AND circuit 124. BBM1
In the address configuration of 01, an interrupt address and a changing routine are arranged for every predetermined address, for example, every 1000 addresses. When the original program is executed and the specified address and the set interrupt address match, an interrupt code is generated and it is determined which comparator has output, and the change routine following the matched interrupt address is executed in the same manner. To When the change routine is not stored in the BBM 101 in the fixed length as described above but is stored in the variable length, it is preferable to prepare a table that associates the first address of the change routine with the comparator number.

[0032]

As described above, according to the present invention, R
When it is desired to partially change the original program stored in the OM, an interrupt circuit is provided and a program change routine for changing to a rewritable nonvolatile memory is stored. Since the modification routine stored in the non-volatile memory is executed when a predetermined address is detected during execution of the original program, it is possible to execute the modified program without replacing the ROM. Become.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a processing device according to the present invention.

FIG. 2 is a block diagram of a conventional processing device.

FIG. 3 is a memory map for explaining the contents of BBM

FIG. 4 is a flowchart showing an initialization routine for operating the processing device.

FIG. 5 is a flowchart of interrupt processing.

FIG. 6 is a memory map of ROM and stack area.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 Address Bus 5 Data Bus 101 Battery Backup Memory (BBM) 110 Interrupt Program Setting Unit 111 Data Switch Unit 112 Interrupt Address Setting Switch 113 Interrupt Address Effective Switch 114 Data Write Switch 115 Switch Detection Circuit 120 Interrupt signal generation unit 121 Detection register 122 Comparator 123 Inverter circuit 124 AND circuit 125 AND circuit 126 Interrupt code generation circuit

Claims (1)

[Claims] 1. A non-volatile processor capable of writing and reading, in a processing device having a ROM storing a program and a CPU for sequentially operating the programs stored in the ROM by outputting an address of the ROM to an address bus. A memory and an interrupt signal generator for constantly comparing the value of the address bus and the value of a predetermined interrupt address during execution of the program stored in the ROM and outputting an interrupt code to the data bus when they match. A processing device configured to decode the interrupt code and execute a program stored in the nonvolatile memory.